CDCLVD2102RGTR

CDCLVD2102 www.ti.com SCAS904A – MAY 2010 – REVISED JUNE 2010 Dual 1:2 Low Additive Jitter LVDS Buffer Check for Samples: CDCLVD2102 FEATURES 1 • • • • • • • • • • • • Dual 1:2 Differential Buffer Low Additive Jitter 3000 V Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions” is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability. The outputs can handle permanent short. RECOMMENDED OPERATING CONDITIONS Device supply voltage, VCC Ambient temperature, TA MIN TYP MAX 2.375 2.5 2.625 –40 85 UNITS V oC Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): CDCLVD2102 3 CDCLVD2102 SCAS904A – MAY 2010 – REVISED JUNE 2010 www.ti.com THERMAL INFORMATION CDCLVD2102 THERMAL METRIC (1) RGT UNITS 16 PINS qJA Junction-to-ambient thermal resistance 51.3 qJC(top) Junction-to-case(top) thermal resistance 85.4 qJB Junction-to-board thermal resistance 20.1 yJT Junction-to-top characterization parameter 1.3 yJB Junction-to-board characterization parameter 19.4 qJC(bottom) Junction-to-case(bottom) thermal resistance 6 (1) °C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. ELECTRICAL CHARACTERISTICS: At VCC = 2.375 V to 2.625 V and TA = –40°C to 85°C (unless otherwise noted). PARAMETER TEST CONDITIONS MIN TYP MAX UNIT EN PIN INPUT CHARACTERISTICS VdI3 3-State VdIH Input high voltage Open VdIL Input low voltage IdIH Input high current VCC = 2.625 V, VIH = 2.625 V IdIL Input low current VCC = 2.625 V, VIL = 0 V Rpull(EN) Input pull-up/ pull-down resistor 0.5×VCC V 0.7×VCC V 0.2×VCC V 30 mA –30 mA 200 kΩ 2.5V LVCMOS (see Figure 7) INPUT CHARACTERISTICS fIN Input frequency External threshold voltage applied to complementary input Vth Input threshold voltage VIH Input high voltage VIL Input low voltage IIH Input high current VCC = 2.625 V, VIH = 2.625 V IIL Input low current VCC = 2.625 V, VIL = 0 V ΔV/ΔT Input edge rate 20% – 80% CIN Input capacitance 200 MHz 1.5 V Vth + 0.1 VCC V 0 Vth – 0.1 V 10 mA 1.1 –10 1.5 mA V/ns 2.5 pF DIFFERENTIAL INPUT CHARACTERISTICS fIN Input frequency Clock input VIN, Differential input voltage peak-to-peak VICM = 1.25 V VICM Input common-mode voltage range VIN, DIFF, PP > 0.4V IIH Input high current VCC = 2.625 V, VIH = 2.625 V IIL Input low current VCC = 2.625 V, VIL = 0 V ΔV/ΔT Input edge rate 20% to 80% CIN Input capacitance 4 DIFF 800 MHz 0.3 1.6 VP-P 1 VCC – 0.3 V 10 mA –10 mA 0.75 V/ns 2.5 Submit Documentation Feedback pF Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): CDCLVD2102 CDCLVD2102 www.ti.com SCAS904A – MAY 2010 – REVISED JUNE 2010 ELECTRICAL CHARACTERISTICS: (continued) At VCC = 2.375 V to 2.625 V and TA = –40°C to 85°C (unless otherwise noted). PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 250 450 mV –15 15 mV 1.1 1.375 –15 15 LVDS OUTPUT CHARACTERISTICS |VOD| Differential output voltage magnitude ΔVOD Change in differential output voltage magnitude VOC(SS) Steady-state common mode output voltage ΔVOC(SS) Steady-state common mode output voltage VIN, DIFF, PP = 0.6 V,RL = 100 Ω Vring Output overshoot and undershoot Percentage of output amplitude VOD VOS Output ac common mode VIN, DIFF, PP = 0.6 V, RL = 100 Ω IOS Short-circuit output current VOD = 0 V tPD Propagation delay VIN, DIFF, PP = 0.3 V tSK, PP Part-to-part skew tSK, O_WB Within bank output skew tSK,O_BB Bank-to-bank output skew Both inputs are phase aligned tSK,P Pulse skew(with 50% duty cycle input) Crossing-point-to-crossing-point distortion tRJIT Random additive jitter (with 50% duty cycle input) Edge speed = 0.75V/ns, 10 kHz – 20 MHz tR/tF Output rise/fall time 20% to 80%,100 Ω, 5 pF 300 ps ICCSTAT Static supply current Outputs unterminated, f = 0 Hz 27 45 mA ICC100 Supply current All outputs enabled, RL = 100 Ω, f = 100 MHz 49 77 mA ICC800 Supply current All outputs enabled, RL = 100 Ω, f = 800 MHz 76 106 mA 1.25 1.35 V VIN, DIFF, PP = 0.3 V,RL = 100 Ω V mV 10% 25 1.5 –50 70 mVPP ±24 mA 2.5 ns 600 ps 15 ps 100 ps 50 ps 0.3 ps, RMS 50 VAC_REF CHARACTERISTICS VAC_REF Reference output voltage VCC = 2.5 V, Iload = 100 µA 1.1 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): CDCLVD2102 5 CDCLVD2102 SCAS904A – MAY 2010 – REVISED JUNE 2010 www.ti.com Typical Additive Phase Noise Characteristics for 100 MHz Clock PARAMETER MIN TYP MAX UNIT phn100 Phase noise at 100 Hz offset -132.9 dBc/Hz phn1k Phase noise at 1 kHz offset -138.8 dBc/Hz phn10k Phase noise at 10 kHz offset -147.4 dBc/Hz phn100k Phase noise at 100 kHz offset -153.6 dBc/Hz phn1M Phase noise at 1 MHz offset -155.2 dBc/Hz phn10M Phase noise at 10 MHz offset -156.2 dBc/Hz phn20M Phase noise at 20 MHz offset -156.6 dBc/Hz tRJIT Random additive jitter from 10 kHz to 20 MHz 171 fs, RMS Typical Additive Phase Noise Characteristics for 737.27 MHz Clock PARAMETER phn100 Phase noise at 100 Hz offset phn1k Phase noise at 1 kHz offset phn10k Phase noise at 10 kHz offset phn100k MIN TYP MAX UNIT -80.2 dBc/Hz -114.3 dBc/Hz -138 dBc/Hz Phase noise at 100 kHz offset -143.9 dBc/Hz phn1M Phase noise at 1 MHz offset -145.2 dBc/Hz phn10M Phase noise at 10 MHz offset -146.5 dBc/Hz phn20M Phase noise at 20 MHz offset -146.6 dBc/Hz tRJIT Random additive jitter from 10 kHz to 20 MHz 65 fs, RMS 6 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): CDCLVD2102 CDCLVD2102 www.ti.com SCAS904A – MAY 2010 – REVISED JUNE 2010 TYPICAL CHARACTERISTICS INPUT CLOCK AND OUTPUT CLOCK PHASE NOISES vs FREQUENCY FROM THE CARRIER (TA = 25°C and VCC = 2.5V) Input clock jitter is 32 fs from 10 kHz to 20 MHz and additive RMS jitter is 152 fs Figure 3. 100 MHz Input and Output Phase Noise Plot Differential Output Voltage vs Frequency VOD − Differential Output Voltage − mV 350 TA = 25oC 340 2.625V 330 320 2.5V 310 300 2.375V 290 280 270 260 250 0 100 200 300 400 500 600 700 800 Frequency − MHz Figure 4. Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): CDCLVD2102 7 CDCLVD2102 SCAS904A – MAY 2010 – REVISED JUNE 2010 www.ti.com TEST CONFIGURATIONS Oscilloscope 100 W LVDS Figure 5. LVDS Output DC Configuration During Device Test Phase Noise Analyzer LVDS 50 W Figure 6. LVDS Output AC Configuration During Device Test Figure 7. DC Coupled LVCMOS Input During Device Test VOH OUTNx VOD OUTPx VOL 80% VOUT,DIFF,PP (= 2 x VOD) 20% 0V tr tf Figure 8. Output Voltage and Rise/Fall Time 8 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): CDCLVD2102 CDCLVD2102 www.ti.com SCAS904A – MAY 2010 – REVISED JUNE 2010 INNx INPx tPLH0 tPHL0 tPLH1 tPHL1 OUTN0 OUTP0 OUTN1 OUTP1 tPLH2 tPHL2 OUTN2 OUTP2 OUTN3 tPLH3 tPHL3 OUTP3 A. Output skew is calculated as the greater of the following: As the difference between the fastest and the slowest tPLHn or the difference between the fastest and the slowest tPHLn (n = 0, 1, 2, 3). B. Part-to-part skew is calculated as the greater of the following: As the difference between the fastest and the slowest tPLHn or the difference between the fastest and the slowest tPHLn across multiple devices (n = 0, 1, 2, 3). C. Both inputs (IN0 and IN1) are phase aligned. Figure 9. Output Skew and Part-to-Part Skew Vring OUTNx VOD 0V Differential OUTPx Figure 10. Output Overshoot and Undershoot VOS GND Figure 11. Output AC Common Mode Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): CDCLVD2102 9 CDCLVD2102 SCAS904A – MAY 2010 – REVISED JUNE 2010 www.ti.com APPLICATION INFORMATION THERMAL MANAGEMENT For reliability and performance reasons, the die temperature should be limited to a maximum of 125°C. The device package has an exposed pad that provides the primary heat removal path to the printed circuit board (PCB). To maximize the heat dissipation from the package, a thermal landing pattern including multiple vias to a ground plane must be incorporated into the PCB within the footprint of the package. The Thermal Pad must be soldered down to ensure adequate heat conduction to of the package. Figure 12 shows a recommended land and via pattern. Figure 12. Recommended PCB Layout POWER-SUPPLY FILTERING High-performance clock buffers are sensitive to noise on the power supply, which can dramatically increase the additive jitter of the buffer. Thus, it is essential to reduce noise from the system power supply, especially when jitter/phase noise is critical to applications. Filter capacitors are used to eliminate the low-frequency noise from the power supply, where the bypass capacitors provide the very low impedance path for high-frequency noise and guard the power-supply system against the induced fluctuations. These bypass capacitors also provide instantaneous current surges as required by the device and should have low equivalent series resistance (ESR). To properly use the bypass capacitors, they must be placed very close to the power-supply pins and laid out with short loops to minimize inductance. It is recommended to add as many high-frequency (for example, 0.1 mF) bypass capacitors as there are supply pins in the package. It is recommended, but not required, to insert a ferrite bead between the board power supply and the chip power supply that isolates the high-frequency switching noises generated by the clock driver; these beads prevent the switching noise from leaking into the board supply. Choose an appropriate ferrite bead with very low dc resistance because it is imperative to provide adequate isolation between the board supply and the chip supply, as well as to maintain a voltage at the supply pins that is greater than the minimum voltage required for proper operation. Board Supply Chip Supply Ferrite Bead 1 µF 10 µF 0.1 µF Figure 13. Power-Supply Decoupling 10 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): CDCLVD2102 CDCLVD2102 www.ti.com SCAS904A – MAY 2010 – REVISED JUNE 2010 LVDS OUTPUT TERMINATION The proper LVDS termination for signal integrity over two 50 Ω lines is 100 Ω between the outputs on the receiver end. Either dc-coupled termination or ac-coupled termination can be used for LVDS outputs. It is recommended to place termination resister close to the receiver. If the receiver is internally biased to a voltage different than the output common mode voltage of the CDCLVD2102, ac-coupling should be used. If the LVDS receiver has internal 100 ohm termination, external termination must be omitted. Unused outputs can be left open without connecting any trace to the output pins. Z = 50 W 100 W CDCLVD2102 LVDS Z = 50 W Figure 14. Output DC Termination 100 nF Z = 50 W 100 W CDCLVD2102 LVDS Z = 50 W 100 nF Figure 15. Output AC Termination With Receiver Internally Biased INPUT TERMINATION The CDCLVD2102 inputs can be interfaced with LVDS, LVPECL, or LVCMOS drivers. LVDS Driver can be connected to CDCLVD2102 inputs with dc or ac coupling as shown Figure 16 and Figure 17, respectively. Z = 50 W 100 W LVDS CDCLVD2102 Z = 50 W Figure 16. LVDS Clock Driver Connected to CDCLVD2102 Input (DC Coupled) 100 nF Z = 50 W LVDS CDCLVD2102 Z = 50 W 100 nF 50 W 50 W VAC_REF Figure 17. LVDS Clock Driver Connected to CDCLVD2102 Input (AC Coupled) Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): CDCLVD2102 11 CDCLVD2102 SCAS904A – MAY 2010 – REVISED JUNE 2010 www.ti.com Figure 18 shows how to connect LVPECL inputs to the CDCLVD2102. The series resistors are required to reduce the LVPECL signal swing if the signal swing is >1.6 VPP. 75 W 100 nF Z = 50 W CDCLVD2102 LVPECL Z = 50 W 100 nF 75 W 150 W 150 W 50 W 50 W VAC_REF Figure 18. LVPECL Clock Driver Connected to CDCLVD2102 Input Figure 19 illustrates how to couple a 2.5 V LVCMOS clock input to the CDCLVD2102 directly. The series resistance (RS) should be placed close to the LVCMOS driver if needed. 3.3 V LVCMOS clock input swing needs to be limited to VIH ≤ VCC. RS LVCMOS (2.5V) Z = 50 W CDCLVD2102 V V Vth = IH + IL 2 Figure 19. 2.5V LVCMOS Clock Driver Connected to CDCLVD2102 Input If one of the buffers is used, then the other unused buffer should be disabled through the EN pin, and the unused input pins should be grounded by 1kΩ resistors. 12 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): CDCLVD2102 CDCLVD2102 www.ti.com SCAS904A – MAY 2010 – REVISED JUNE 2010 REVISION HISTORY Changes from Original (May 2010) to Revision A Page • Changed Features bullet From: ESD Protection Exceeds 2kV HBM, 500V CDM To: ESD Protection Exceeds 3 kV HBM, 1 kV CDM ................................................................................................................................................................... 1 • Electrostatic discharge was