CDCLVP1204RGTR

Product Folder Sample & Buy Support & Community Tools & Software Technical Documents Reference Design CDCLVP1204 SCAS880F – AUGUST 2009 – REVISED SEPTEMBER 2015 CDCLVP1204 Four LVPECL Output, High-Performance Clock Buffer 1 Features 3 Description • • • The CDCLVP1204 is a highly versatile, low additive jitter buffer that can generate four copies of LVPECL clock outputs from one of two selectable LVPECL, LVDS, or LVCMOS inputs for a variety of communication applications. It has a maximum clock frequency up to 2 GHz. The CDCLVP1204 features an on-chip multiplexer (MUX) for selecting one of two inputs that can be easily configured solely through a control terminal. The overall additive jitter performance is less than 0.1 ps, RMS from 10 kHz to 20 MHz, and overall output skew is as low as 15 ps, making the device a perfect choice for use in demanding applications. 1 • • • • • • • • • • • 2:4 Differential Buffer Selectable Clock Inputs Through Control Terminal Universal Inputs Accept LVPECL, LVDS, and LVCMOS/LVTTL Four LVPECL Outputs Maximum Clock Frequency: 2 GHz Maximum Core Current Consumption: 45 mA Very Low Additive Jitter: