Sample &
Buy
Product
Folder
Support &
Community
Tools &
Software
Technical
Documents
CDCLVP2104
SCAS889B – OCTOBER 2009 – REVISED JANUARY 2016
CDCLVP2104 Eight-LVPECL Output, High-Performance Clock Buffer
1 Features
3 Description
•
•
•
The CDCLVP2104 is a highly versatile, low additive
jitter buffer that can generate eight copies of LVPECL
clock outputs from two LVPECL, LVDS, or LVCMOS
inputs for a variety of communication applications. It
has a maximum clock frequency up to 2 GHz. Each
buffer block consists of one input that feeds two
LVPECL outputs. The overall additive jitter
performance is less than 0.1 ps, RMS from 10 kHz to
20 MHz, and overall output skew is as low as 15 ps,
making the device a perfect choice for use in
demanding applications.
1
•
•
•
•
•
•
•
•
•
•
•
•
Dual 1:4 Differential Buffer
Two Clock Inputs
Universal Inputs Can Accept LVPECL, LVDS,
LVCMOS/LVTTL
Eight LVPECL Outputs
Maximum Clock Frequency: 2 GHz
Maximum Core Current Consumption: 78 mA
Very Low Additive Jitter:
很抱歉,暂时无法提供与“CDCLVP2104RHDT”相匹配的价格&库存,您可以联系我们找货
免费人工找货