CDCM1804
www.ti.com
SCAS697E – JULY 2003 – REVISED MAY 2005
1:3 LVPECL CLOCK BUFFER + ADDITIONAL
LVCMOS OUTPUT AND PROGRAMMABLE DIVIDER
S1
VDD0
17
VDD1
IN
3
16
Y1
IN
4
15
Y1
VDDPECL
5
14
VDD1
VBB
6
VDD3
(1)
VSS(1)
7
8
9
13
10 11 12
Thermal pad must be connected to VSS.
P0024-01
S2
VDD0
Y0
Y0
VDD0
S1
24
23
22
21
20
19
RTH PACKAGE
(TOP VIEW)
EN
1
18
S0
VDDPECL
2
17
VDD1
IN
3
16
Y1
IN
4
15
Y1
VDDPECL
5
14
VDD1
VBB
6
13
VDD3
(1)
7
8
9
10
11
12
VDD2
Y2
Y2
VDD2
Y3
VSS(1)
VSS
The CDCM1804 has three control terminals, S0, S1,
and S2, to select different output mode settings. The
S[2:0] terminals are 3-level inputs and therefore allow
up to 33 = 27 combinations. Additionally, an enable
terminal (EN) is provided to disable or enable all
outputs simultaneously. The EN terminal is a 3-level
input as well and extends the number of settings to
2 × 27 = 54. See Table 1 for details.
Y0
2
DESCRIPTION
The CDCM1804 clock driver distributes one pair of
differential clock inputs to three pairs of LVPECL
differential clock outputs Y[2:0] and Y[2:0], with minimum skew for clock distribution. The CDCM1804 is
specifically designed for driving 50-Ω transmission
lines. Additionally, the CDCM1804 offers a
single-ended LVCMOS output Y3. This output is
delayed by 1.6 ns over the three LVPECL output
stages to minimize noise impact during signal transitions.
Y0
VDDPECL
S0
Y3
•
•
•
24 23 22 21 20 19
18
VDD2
•
1
Y2
•
EN
Y2
•
•
RGE PACKAGE
(TOP VIEW)
VDD0
•
For use in single-ended driver applications, the
CDCM1804 also provides a VBB output terminal that
can be directly connected to the unused input as a
common-mode voltage reference.
VDD2
•
Distributes One Differential Clock Input to
Three LVPECL Differential Clock Outputs and
One LVCMOS Single-Ended Output
Programmable Output Divider for Two
LVPECL Outputs and LVCMOS Output
Low-Output Skew 15 ps (Typical) for
Clock-Distribution Applications for LVPECL
Outputs; 1.6-ns Output Skew Between
LVCMOS and LVPECL Transitions Minimizing
Noise
VCC Range 3 V–3.6 V
Signaling Rate Up to 800-MHz LVPECL and
200-MHz LVCMOS
Differential Input Stage for Wide
Common-Mode Range
Provides VBB Bias Voltage Output for
Single-Ended Input Signals
Receiver Input Threshold ±75 mV
24-Terminal QFN Package (4 mm × 4 mm)
Accepts Any Differential Signaling:
LVDS, HSTL, CML, VML, SSTL-2, and
Single-Ended: LVTTL/LVCMOS
S2
•
The CDCM1804 is characterized for operation from
–40°C to 85°C.
VSS
FEATURES
Thermal pad must be connected to VSS.
P0025-01
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2003–2005, Texas Instruments Incorporated
CDCM1804
www.ti.com
SCAS697E – JULY 2003 – REVISED MAY 2005
FUNCTIONAL BLOCK DIAGRAM
Y0
IN
LVPECL
Y0
IN
LVCMOS
Y3
Div 1
Div 2
Div 4
Div 8
Div 16
Y1
LVPECL
Y1
VBB
Bias
Generator
VDD − 1.3 V
(Imax < 1.5 mA)
Y2
LVPECL
Y2
Control
S1
S2
S0
EN
B0059-01
2
CDCM1804
www.ti.com
SCAS697E – JULY 2003 – REVISED MAY 2005
TERMINAL FUNCTIONS
TERMINAL
NAME
EN
NO.
1
I/O
I
(with 60-kΩ pullup)
DESCRIPTION
ENABLE: Enables or disables all outputs simultaneously. The EN terminal offers three
different configurations: tied to GND (logic 0), external 60-kΩ pulldown resistor (pull to
VDD/2), or left floating (logic 1);
EN = 1: outputs on according to S[2:0] settings
EN = VDD/2: outputs on according to S[2:0] settings
EN = 0: outputs Y[3:0] off (high impedance)
See Table 1 for details.
IN, IN
3, 4
I (differential)
Differential input clock: Input stage is sensitive and has a wide common-mode range.
Therefore, almost any type of differential signal can drive this input (LVPECL, LVDS,
CML, HSTL). Because the input is high-impedance, it is recommended to terminate the
PCB transmission line before the input (e.g., with 100 Ω across input). Input can also be
driven by single-ended signal if the complementary input is tied to VBB. A
more-advanced scheme for single-ended signals is given in the Application Information
section near the end of this document.
The inputs employ an ESD structure protecting the inputs in case of an input voltage
exceeding the rails by more than ~0.7 V. Reverse biasing of the IC through these inputs
is possible and must be prevented by limiting the input voltage < VDD.
S[2:0]
VBB
18, 19, 24
I
(with 60-kΩ pullup)
6
O
Select mode of operation: Defines the output configuration of Y[3:0]. Each terminal
offers three different configurations: tied to GND (logic 0), external 60-kΩ pulldown
resistor (pull to VDD/2), or left floating (logic 1); see Table 1 for details.
Bias voltage output to be used to bias unused complementary input IN for single-ended
input signals.
The output voltage of VBB is VDD – 1.3 V. When driving a load, the output current drive
is limited to about 1.5 mA.
VSS
VDDPECL
VDD[2:0]
7
Supply
Device ground
2, 5
Supply
Supply voltage LVPECL input + internal logic
8, 11, 14,
17, 20, 23
Supply
LVPECL output supply voltage for output Y[2:0]. Each output can be disabled by pulling
the corresponding VDDx to GND.
CAUTION: In this mode, no voltage from outside may be forced, because internal
diodes could be forced in forward direction. Thus, it is recommended to disconnect the
output.
VDD3
13
Supply
Supply voltage LVCMOS output. The LVCMOS output can be disabled by pulling VDD3
to GND.
CAUTION: In this mode, no voltage from outside may be forced because internal
diodes could be forced in a forward direction. Thus, it is recommended to leave Y3
unconnected, tied to GND, or terminated into GND.
Y[2:0]
Y[2:0]
Y3
9, 15, 21
10, 16, 22
O (LVPECL)
12
O
LVPECL clock outputs. These outputs provide low-skew copies of IN or down-divided
copies of clock IN based on selected mode of operation S[2:0]. If an output is unused,
the output can simply be left open to save power and minimize noise impact to the
remaining outputs.
LVCMOS clock output. This output provides copy of IN or down-divided copy of clock IN
based on selected mode of operation S[2:0]. Also, this output can be disabled when
VDD3 becomes tied to GND.
CONTROL TERMINAL SETTINGS
The CDCM1804 has three control terminals (S0, S1, and S2) and an enable terminal (EN) to select different
output mode settings. All four inputs (S0, S1, S2, and EN) are 3-level inputs offering 54 different combinations. In
addition, the EN input allows the disabling of all outputs and forcing them into a high-z (or 3-state) output state
when pulled to GND.
Each control input incorporates a 60-kΩ pullup resistor. Thus, it is easy to choose the input setting by designing
a resistor pad between the control input and GND. To choose a logic zero, the resistor value must be zero.
Setting the input high requires leaving the resistor pad empty (no resistor installed). For setting the input to
VDD/2, the installed resistor must be a 60-kΩ pulldown to GND with a 10% tolerance or better.
3
CDCM1804
www.ti.com
SCAS697E – JULY 2003 – REVISED MAY 2005
Setting for Mode 13:
EN = 1
S2 = VDD/2
S1 = VDD/2
S0 = 0
CDCM1804
REN = Open
EN
RS2 = 60 kΩ
S2
RS1 = 60 kΩ
S1
RS0 = 0 Ω
S0
S0084-01
Figure 1. Control Terminal Setting for Example
Table 1. Selection Mode Table
LVPECL (1)
(1)
4
MODE
EN
S2
S1
S0
Y0
0
0
x
x
x
1
1
0
0
0
÷1
2
1
0
0
VDD/2
÷1
3
1
0
0
1
÷1
4
1
0
VDD/2
0
5
1
0
VDD/2
VDD/2
6
1
0
VDD/2
7
1
0
8
1
9
1
10
LVCMOS
Y1
Y2
Y3
÷1
÷1
Off (high-z)
Off (high-z)
Off (high-z)
÷4
÷1
Off (high-z)
÷4
÷1
÷2
Off (high-z)
÷4
÷1
÷4
Off (high-z)
÷4
1
÷1
÷8
Off (high-z)
÷4
1
0
÷1
Off (high-z)
÷1
÷4
0
1
VDD/2
÷1
÷1
÷1
÷4
0
1
1
÷1
÷2
÷1
÷4
1
VDD/2
0
0
÷1
÷4
÷1
÷4
11
1
VDD/2
0
VDD/2
÷1
÷8
÷1
÷4
12
1
VDD/2
0
1
÷1
Off (high-z)
÷2
÷4
13
1
VDD/2
VDD/2
0
÷1
÷1
÷2
÷4
14
1
VDD/2
VDD/2
VDD/2
÷1
÷2
÷2
÷4
15
1
VDD/2
VDD/2
1
÷1
÷4
÷2
÷4
16
1
VDD/2
1
0
÷1
÷8
÷2
÷4
17
1
VDD/2
1
VDD/2
÷1
Off (high-z)
÷4
÷4
18
1
VDD/2
1
1
÷1
÷1
÷4
÷4
19
1
1
0
0
÷1
÷2
÷4
÷4
20
1
1
0
VDD/2
÷1
÷4
÷4
÷4
21
1
1
0
1
÷1
÷8
÷4
÷4
22
1
1
VDD/2
0
÷1
Off (high-z)
÷8
÷4
23
1
1
VDD/2
VDD/2
÷1
÷1
÷8
÷4
24
1
1
VDD/2
1
÷1
÷2
÷8
÷4
25
1
1
1
0
÷1
÷4
÷8
÷4
Off (high-z)
The LVPECL outputs are open-emitter stages. Thus, if you leave the unused LVPECL outputs Y0, Y1, or Y2 unconnected, then the
current consumption is minimized and noise impact to remaining outputs is neglectable. Also, each output can be individually disabled
by connecting the corresponding VDD input to GND.
CDCM1804
www.ti.com
SCAS697E – JULY 2003 – REVISED MAY 2005
Table 1. Selection Mode Table (continued)
LVPECL (1)
LVCMOS
MODE
EN
S2
S1
S0
Y0
Y1
Y2
Y3
26
1
1
1
VDD/2
÷1
÷8
÷8
÷4
27
1
1
1
1
÷1
Off (high-z)
÷ 16
÷4
28
VDD/2
0
0
0
÷1
÷1
÷ 16
÷4
29
VDD/2
0
0
VDD/2
÷1
÷2
÷ 16
÷4
30
VDD/2
0
0
1
÷1
÷4
÷ 16
÷4
31
VDD/2
0
VDD/2
0
÷1
÷8
÷ 16
÷4
32
VDD/2
0
VDD/2
VDD/2
÷1
Off (high-z)
Off (high-z)
÷1
33
VDD/2
0
VDD/2
1
÷1
÷1
Off (high-z)
÷1
34
VDD/2
0
1
0
÷1
÷2
Off (high-z)
÷1
35
VDD/2
0
1
VDD/2
÷1
÷1
Off (high-z)
÷2
36
VDD/2
0
1
1
÷1
÷2
Off (high-z)
÷2
37
VDD/2
VDD/2
0
0
÷1
Off (high-z)
Off (high-z)
÷2
38
VDD/2
VDD/2
0
VDD/2
÷1
÷1
÷1
÷2
39
VDD/2
VDD/2
0
1
÷1
÷2
÷8
÷2
40
VDD/2
VDD/2
VDD/2
0
÷1
÷2
÷8
÷8
41
VDD/2
VDD/2
VDD/2
VDD/2
÷1
÷4
Off (high-z)
÷1
42
VDD/2
VDD/2
VDD/2
1
÷1
÷8
Off (high-z)
÷1
43
VDD/2
VDD/2
1
0
÷1
÷4
Off (high-z)
÷2
44
VDD/2
VDD/2
1
VDD/2
÷1
÷8
Off (high-z)
÷2
45
VDD/2
VDD/2
1
1
÷1
÷1
÷2
÷2
46
VDD/2
1
0
0
÷1
Off (high-z)
Off (high-z)
÷8
47
VDD/2
1
0
VDD/2
÷1
÷4
Off (high-z)
÷8
48
VDD/2
1
0
1
÷1
÷4
÷8
÷8
49
VDD/2
1
VDD/2
0
÷1
÷8
Off (high-z)
÷8
50
VDD/2
1
VDD/2
VDD/2
÷1
÷2
÷8
÷ 16
Rsv
VDD/2
1
VDD/2
1
Reserved
Reserved
Reserved
Reserved
Rsv
VDD/2
1
1
0
N/A
Low
Low
Low
53
VDD/2
1
1
VDD/2
÷1
÷1
÷1
÷1
54
VDD/2
1
1
1
÷1
÷1
÷1
÷1
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature (unless otherwise noted) (1)
VDD
Supply voltage
VI
Input voltage
–0.2 V to (VDD + 0.2 V)
VO
Output voltage
–0.2 V to (VDD + 0.2 V)
Differential short-circuit current, Yn, Yn, IOSD
Electrostatic discharge (HBM 1.5 kΩ, 100 pF), ESD
Moisture level 24-terminal QFN package (solder reflow temperature of 235°C) MSL
Tstg
Storage temperature
TJ
Maximum junction temperature
(1)
–0.3 V to 3.8 V
Continuous
>2000 V
2
–65°C to 150°C
125°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
5
CDCM1804
www.ti.com
SCAS697E – JULY 2003 – REVISED MAY 2005
RECOMMENDED OPERATING CONDITIONS
VDD
Supply voltage
TA
Operating free-air temperature
MIN
TYP
MAX
3
3.3
3.6
V
85
°C
–40
UNIT
ELECTRICAL CHARACTERISTICS
over recommended operating free-air temperature range (unless otherwise noted)
LVPECL INPUT IN, IN
MAX
UNIT
fclk
Input frequency
PARAMETER
0
800
MHz
VCM
High-level input common mode
1
VDD – 0.3
IN (1)
500
1300
Input voltage swing between IN and IN (2)
150
1300
Input voltage swing between IN and
VIN
IIN
Input current
RIN
Input impedance
CI
Input capacitance at IN, IN
(1)
(2)
TEST CONDITIONS
MIN
TYP
±10
VI = VDD or 0 V
300
V
mV
µA
kΩ
1
pF
Is required to maintain ac specifications
Is required to maintain device functionality
LVPECL OUTPUT DRIVER Y[2:0], Y[2:0]
PARAMETER
TEST CONDITIONS
MIN
TYP
UNIT
800
MHz
Output frequency, see Figure 4
VOH
High-level output voltage
Termination with 50 Ω to VDD – 2 V
VDD – 1.18
VDD – 0.81
V
VOL
Low-level output voltage
Termination with 50 Ω to VDD – 2 V
VDD – 1.98
VDD – 1.55
V
VO
Output voltage swing between Y and
Termination with 50 Ω to VDD – 2 V
Y, see Figure 4.
500
IOZL
Output 3-state current
IOZH
0
MAX
fclk
VDD = 3.6 V, VO = 0 V
5
VDD = 3.6 V, VO = VDD – 0.8 V
tr/tf
Rise and fall time
20% to 80% of VOUTPP, see Figure 9.
tskpecl(o)
Output skew between any LVPECL
output Y[2-0] and Y[2-0]
See Note A in Figure 8.
tDuty
Output duty-cycle distortion (1)
Crossing point-to-crossing point distortion
tsk(pp)
Part-to-part skew
Any Y, see Note B in Figure 8.
CO
Output capacitance
VO = VDD or GND
LOAD
Expected output load
(1)
mV
10
200
15
–50
µA
350
ps
30
ps
50
ps
50
ps
1
pF
50
Ω
For an 800-MHz signal, the 50-ps error would result in a duty-cycle distortion of ±4% when driven by an ideal clock input signal.
LVPECL INPUT-TO-LVPECL OUTPUT PARAMETERS
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
LVPECL INPUT-TO-LVPECL OUTPUT PARAMETER
tpd(lh)
Propagation delay rising edge
VOX to VOX
320
600
ps
tpd(hl)
Propagation delay falling edge
VOX to VOX
320
600
ps
tsk(p)
LVPECL pulse skew
VOX to VOX, see Note C in Figure 8.
100
ps
6
CDCM1804
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SCAS697E – JULY 2003 – REVISED MAY 2005
LVCMOS OUTPUT PARAMETER, Y3
PARAMETER
TEST CONDITIONS
fclk
OUTPUT frequency, see Figure
tskLVCMOS(o)
Output skew between the LVCMOS output Y3 and LVPECL outputs Y[2:0]
VOX to VDD/2, see Figure 8.
tsk(pp)
Part-to-part skew
Y3, see Note B in Figure 8.
VOH
TYP
MAX
UNIT
200
MHz
2.1
ns
0
High-level output voltage
VOL
MIN
5 (1).
Low-level output voltage
1.3
1.6
300
ps
VDD = min to max
IOH = –100 µA
VDD = 3 V
IOH = –6 mA
VDD = 3 V
IOH = –12 mA
VDD = min to max
IOL = 100 µA
0.1
VDD = 3 V
IOL = 6 mA
0.5
VDD = 3 V
IOL = 12 mA
0.8
VDD – 0.1
2.4
V
2
IOH
High-level output current
VDD = 3.3 V
VO = 1.65 V
–29
IOL
Low-level output current
VDD = 3.3 V
VO = 1.65 V
37
IOZ
High-impedance-state output current
VDD = 3.6 V
VO = VDD or 0 V
CO
Output capacitance
VDD = 3.3 V
tDuty
Output duty cycle distortion (2)
Measured at VDD/2
V
mA
mA
±5
2
µA
pF
–150
150
ps
tpd(lh)
Propagation delay rising edge from IN to
VOX to VDD/2 load, see Figure 10.
Y3
1.6
2.6
ns
tpd(hl)
Propagation delay falling edge from IN
to Y3
VOX to VDD/2 load, see Figure 10.
1.6
2.6
ns
tr
Output rise slew rate
20% to 80% of swing, see Figure 10.
1.4
2.3
V/ns
tf
Output fall slew rate
80% to 20% of swing, see Figure 10.
1.4
2.3
V/ns
(1)
(2)
Operating the CDCM1804 LVCMOS output above the maximum frequency does not cause a malfunction to the device, but the Y3
output will not achieve enough signal swing to meet the output specification. Therefore, the CDCM1804 can be operated at higher
frequencies, while the LVCMOS output Y3 becomes unusable.
For a 200-MHz signal, the 150-ps error would result in a duty cycle distortion of ±3% when driven by an ideal clock input signal.
JITTER CHARACTERISTICS
PARAMETER
tjitterLVPECL
tjitterLVCMOS
TEST CONDITIONS
12 kHz to 20 MHz,
fout = 250 MHz to 800 MHz,
divide-by-1 mode
Additive phase jitter from input to
LVPECL output Y[2:0], see Figure 2. 50 kHz to 40 MHz,
fout = 250 MHz to 800 MHz,
divide-by-1 mode
Additive phase jitter from input to
LVCMOS output Y3, see Figure 3.
MIN
TYP
MAX
UNIT
0.15
ps rms
0.25
12 kHz to 20 MHz, fout = 250 MHz,
divide-by-1 mode
0.25
50 kHz to 40 MHz, fout = 250 MHz,
divide-by-1 mode
0.4
ps rms
7
CDCM1804
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SCAS697E – JULY 2003 – REVISED MAY 2005
ADDITIVE PHASE NOISE
vs
FREQUENCY OFFSET FROM CARRIER – LVPECL
ADDITIVE PHASE NOISE
vs
FREQUENCY OFFSET FROM CARRIER – LVCMOS
−110
−120
−110
−125
−130
−135
−140
−145
−150
−115
−120
−125
−130
−135
−140
−145
−150
−155
−160
10
VDD = 3.3 V
TA = 25°C
f = 250 MHz
÷1 Mode
−105
Additive Phase Noise − dBc/Hz
Additive Phase Noise − dBc/Hz
−115
−100
VDD = 3.3 V
TA = 25°C
f = 622 MHz
÷1 Mode
−155
100
1k
10k
100k
1M
10M
−160
10
100M
f − Frequency Offset From Carrier − Hz
100
1k
10k
100k
1M
10M
100M
f − Frequency Offset From Carrier − Hz
G001
G002
Figure 2.
Figure 3.
LVPECL OUTPUT SWING
vs
FREQUENCY
LVCMOS OUTPUT SWING
vs
FREQUENCY
3.5
0.90
0.85
VDD = 3.6 V
VDD3 = 3.6 V
3.0
LVCMOS Output Swing − V
LVPECL Output Swing − V
0.80
0.75
0.70
VDD = 3 V
0.65
0.60
0.55
VDD = 3.3 V
2.5
VDD3 = 3 V
2.0
VDD = 3.3 V
1.5
1.0
0.50
TA = 25°C
Load = See Figure 10
0.5
0.45
0.40
0.1
TA = 25°C
Load = 50 Ω to VDD − 2 V
0.3
0.5
0.7
0.0
0.9
1.1
1.3
1.5
f − Frequency − GHz
25
75
125 175 225 275 325 375 425 475
f − Frequency − MHz
G003
Figure 4.
8
G004
Figure 5.
CDCM1804
www.ti.com
SCAS697E – JULY 2003 – REVISED MAY 2005
SUPPLY CURRENT ELECTRICAL CHARACTERISTICS
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
Full load
Supply current
IDD
TYP MAX
Supply current saving per LVPECL
output stage disabled, no load
f = 800 MHz for LVPECL output, VDD = 3.3 V
Supply current, 3-state
All outputs in the high-impedance state by control logic, f = 0
Hz,
VDD = 3.6 V
UNIT
160
mA
Outputs enabled, no output load, f = 800 MHz for LVPECL
outputs and 200 MHz for LVCMOS, VDD = 3.6 V
No load
110
10
mA
0.5
mA
SUPPLY CURRENT
vs
FREQUENCY
180
170
IDD − Supply Current − mA
IDDZ
MIN
All outputs enabled and terminated with 50 Ω to
VDD – 2 V on LVPECL outputs and 10 pF on LVCMOS
output, f = 800 MHz for LVPECL outputs and 200 MHz for
LVCMOS, VDD = 3.3 V
160
150
VDD = 3.3 V
TA = 25°C
Load = 10 pF/1k/1k for LVCMOS
50 Ω to VDD − 2 V for LVPECL
3 LVPECL Outputs (÷1),
LVCMOS Output (÷4)
3 LVPECL Outputs (÷1)
Running, LVCMOS Output Off
140
130
2 LVPECL Outputs (÷1),
LVCMOS Output (÷4)
120
110
100
300
500
700
900
1100
1300
1500
f − Frequency − MHz
G005
Figure 6.
9
CDCM1804
www.ti.com
SCAS697E – JULY 2003 – REVISED MAY 2005
PACKAGE THERMAL RESISTANCE
PARAMETER
RθJA-1
RθJA-2
(1)
QFN-24 package thermal
TEST CONDITIONS
resistance (1)
QFN-24 package thermal resistance
with thermal vias in PCB (1)
MIN
TYP
4-layer JEDEC test board (JESD51-7),
airflow = 0 ft/min
4-layer JEDEC test board (JESD51-7) with four
thermal vias of 22-mil diameter each,
airflow = 0 ft/min
MAX
UNIT
106.6
°C/W
55.4
°C/W
It is recommended to provide four thermal vias to connect the thermal pad of the package effectively with the PCB and ensure a good
heat sink.
Example:
Calculation of the junction-lead temperature with a 4-layer JEDEC test board using four thermal vias:
TChassis = 85°C (temperature of the chassis)
Peffective = Imax × Vmax = 110 mA × 3.6 V = 396 mW (maximum power consumption inside the package)
θTJunction = RθJA-2 × Peffective = 55.45°C/W × 396 mW = 21.96°C
TJunction = θTJunction + TChassis = 21.96°C + 85°C = 107°C (the maximum junction temperature of
Tdie-max = 125°C is not violated)
CONTROL INPUT CHARACTERISTICS
over recommended operating free-air temperature range
PARAMETER
TEST CONDITIONS
tsu
Setup time, S0, S1, S2, and EN terminals before clock IN
th
Hold time, S0, S1, S2, and EN terminals after clock IN
t(disable)
Time between latching the EN low transition and when all
outputs are disabled (how much time is required until the
outputs turn off)
t(enable)
Time between latching the EN low-to-high transition and when
outputs are enabled based on control settings (how much time
passes before the outputs carry valid signals)
Rpullup
Internal pullup resistor on S[2:0] and EN inputs
Three-level input high, S0, S1, S2, and EN
VIM(M)
Three-level input MID, S0, S1, S2, and EN terminals
VIL(L)
Three-level input low, S0, S1, S2, and EN terminals
(1)
MAX
0
ns
10
ns
1
µs
60
78
0.9 VDD
kΩ
V
0.3 VDD
VI = GND
UNIT
ns
0.7 VDD
V
0.1 VDD
V
–5
µA
85
µA
MAX
UNIT
VI = VDD
Input current, S0, S1, S2, and EN terminals
IIL
TYP
25
42
terminals (1)
VIH(H)
IIH
MIN
38
Leaving this terminal floating automatically pulls the logic level high to VDD through an internal pullup resistor of 60 kΩ.
BIAS VOLTAGE VBB
over recommended operating free-air temperature range
PARAMETER
VBB
10
Output reference voltage
TEST CONDITIONS
VDD = 3 V–3.6 V, IBB = –0.2 mA
MIN
VDD – 1.4
TYP
VDD – 1.2
V
CDCM1804
www.ti.com
SCAS697E – JULY 2003 – REVISED MAY 2005
OUTPUT REFERENCE VOLTAGE (VBB)
vs
LOAD
4.0
VDD = 3.3 V
VBB − Output Reference Voltage − V
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
−5
0
5
10
15
20
25
30
35
I − Load − mA
G006
Figure 7.
11
CDCM1804
www.ti.com
SCAS697E – JULY 2003 – REVISED MAY 2005
PARAMETER MEASUREMENT INFORMATION
IN
IN
Y0
Y0
tpd(LH1)
Y1
Y1
tpd(LH2)
Y2
Y2
Y3
0.5 × VDD3
tskLVCMOS(o)
NOTES: A. Output skew, tsk(o), is calculated as the greater of:
− The difference between the fastest and the slowest tpd(LH)n (n = 0…2)
− The difference between the fastest and the slowest tpd(HL)n (n = 0…2)
B. Part-to-part skew, tsk(pp), is calculated as the greater of:
− The difference between the fastest and the slowest tpd(LH)n (n = 0…2 for LVPECL, n = 3 for LVCMOS) across multiple devices
− The difference between the fastest and the slowest tpd(HL)n (n = 0…2 for LVPECL, n = 3 for LVCMOS) across multiple devices
C. Pulse skew, tsk(p), is calculated as the magnitude of the absolute time difference between the high-to-low (tpd(HL) and the low-to-high
(tpd(LH)) propagation delays when a single switching input causes one or more outputs to switch, tsk(p) = | tpd(HL) − tpd(LH) |. Pulse skew
is sometimes referred to as pulse width distortion or duty cycle skew.
T0067-01
Figure 8. Waveforms for Calculation of tsk(o) and tsk(pp)
Yn
VOH
Yn
VOL
80%
VOUT(pp)
0V
20%
|YnYn|
tr
tf
T0058-02
Figure 9. LVPECL Differential Output Voltage and Rise/Fall Time
12
CDCM1804
www.ti.com
SCAS697E – JULY 2003 – REVISED MAY 2005
PARAMETER MEASUREMENT INFORMATION (continued)
CDCM1804
1 kΩ
LVCMOS
Y3
1 kΩ
10 pF
S0079-02
Figure 10. LVCMOS Output Loading During Device Test
PCB DESIGN FOR THERMAL FUNCTIONALITY
It is recommended to take special care of the PCB design for good thermal flow from the QFN-24 terminal
package to the PCB.
Due to the three LVPECL outputs, the current consumption of the CDCM1804 is fixed.
JEDEC JESD51-7 specifies thermal conductivity for standard PCB boards.
Modeling the CDCM1804 with a standard 4-layer JEDEC board results in a 67.22°C maximum temperature with
RθJA of 106.62°C/W for 25°C ambient temperature.
When deploying four thermal vias (one per quadrant), the thermal flow improves significantly, yielding 46.94°C
maximum temperature with RθJA of 55.4°C/W for 25°C ambient temperature.
To ensure sufficient thermal flow, it is recommended to design with four thermal vias in applications enabling all
four outputs at once.
13
CDCM1804
www.ti.com
SCAS697E – JULY 2003 – REVISED MAY 2005
PARAMETER MEASUREMENT INFORMATION (continued)
Package Thermal Pad
(Underside)
Thermal Via
Dia 0.020 In.
Top Side
Island
Heat
Dissipation
VSS Copper Plane
VSS Copper Plane
M0029-01
Figure 11. Recommended Thermal Via Placement
See the application reports Quad Flatpack No-Lead Logic Packages (SCBA017) and QFN/SON PCB Attachment
(SLUA271) for further package-related information.
14
CDCM1804
www.ti.com
SCAS697E – JULY 2003 – REVISED MAY 2005
APPLICATION INFORMATION
LVPECL RECEIVER INPUT TERMINATION
The input of the CDCM1804 has a high impedance and comes with a large common-mode voltage range.
For optimized noise performance, it is recommended to properly terminate the PCB trace (transmission line). If a
differential signal drives the CDCM1804, then a 100-Ω termination resistor is recommended to be placed as
close as possible across the input terminals. An even better approach is to install 2 × 50 Ω, with the center tap
connected to a capacitor (C) to terminate odd-mode noise and make up for transmission-line mismatches. The
VBB output can also be connected to the center tap to bias the input signal to (VDD – 1.3 V) (see Figure 12).
CDCM1804
CAC
IN
50 Ω
LVPECL
50 Ω
150 Ω
50 Ω
CAC
IN
50 Ω
VBB
150 Ω
C
S0085-01
Figure 12. Recommended AC-Coupling LVPECL Receiver Input Termination
CDCM1804
130 Ω
IN
50 Ω
LVPECL
83 Ω
130 Ω
IN
50 Ω
83 Ω
S0086-01
Figure 13. Recommended DC-Coupling LVPECL Receiver Input Termination
The CDCM1804 can also be driven by single-ended signals. Typically, the input signal becomes connected to
one input, while the complementary input must be properly biased to the center voltage of the incoming input
signal. For LVCMOS signals, this would be VCC/2, realized by a simple voltage divider (e.g., two 10-kΩ resistors).
The best option (especially if the dc offset of the input signal might vary) is to ac-couple the input signal and then
rebias the signal using the VBB reference output. See Figure 14.
15
CDCM1804
www.ti.com
SCAS697E – JULY 2003 – REVISED MAY 2005
APPLICATION INFORMATION (continued)
CDCM1804
CAC
IN
CLK
Rdc
IN
VBB
CCT
NOTE: CAC − AC-coupling capacitor (e.g., 10 nF)
CCT − Capacitor keeps voltage at IN constant (e.g., 10 nF)
Rdc − Load and correct duty cycle (e.g., 50 Ω)
VBB − Bias voltage output
S0087-01
Figure 14. Typical Application Setting for Single-Ended Input Signals Driving the CDCM1804
DEVICE BEHAVIOR DURING RESET AND CONTROL-TERMINAL SWITCHING
Output Behavior From Enabling the Device (EN = 0 → 1)
In disable mode (EN = 0), all output drivers are switched in high-Z mode. The S[2:0] control inputs are also
switched off. In the same mode, all flip-flops are reset. The typical current consumption is below 500 µA.
When the device is enabled again, it takes typically 1 µs for the settling of the reference voltage and currents.
During this time, the outputs Y[2:0] and Y[2:0] drive a high signal. Y3 is unknown (could be high or low). After the
settle time, the outputs go into the low state. Due to the synchronization of each output driver signal with the
input clock, the state of the waveforms after enabling the device is as shown in Figure 15. The inverting input
and output signal are not included. The Y:/1 waveform is the undivided output driver state.
16
CDCM1804
www.ti.com
SCAS697E – JULY 2003 – REVISED MAY 2005
APPLICATION INFORMATION (continued)
1 µs
EN
IN
Y:/1
High-Z
Undefined
Y:/2
High-Z
Undefined
Y:/4
High-Z
Undefined
Low
Low
Low
Signal State After the Device is Enabled (IN = Low)
1 µs
Undivided State is Valid After the First
Positive Transition of the Input Clock
EN
IN
Y:/1
High-Z
Undefined
Y:/2
High-Z
Undefined
Y:/4
High-Z
Undefined
Low
Low
Low
Signal State After the Device is Enabled (IN = High)
T0068-01
Figure 15. Waveforms
Enabling a Single Output Stage
If a single output stage becomes enabled:
• Y[2:0] is either low or high (undefined).
• Y[2:0] is the inverted signal of Y[2:0].
With the first positive clock transition, the undivided output becomes the input clock state. The divided output
states are equal to the actual internal divider. The internal divider is not reset while enabling single-output drivers.
17
CDCM1804
www.ti.com
SCAS697E – JULY 2003 – REVISED MAY 2005
APPLICATION INFORMATION (continued)
ENABLE Yx:
Disabled
Enabled
Undivided State is Valid After the First
Positive Transition of the Input Clock
IN
Yx:/1
High-Z
Undefined
Yx:/x
High-Z
Undefined
Divider State
T0069-01
Figure 16. Signal State After an Output Driver Becomes Enabled While IN = 0
ENABLE Yx:
Disabled
Undivided State is Valid After the First
Positive Transition of the Input Clock
Enabled
IN
Yx:/1
High-Z
Undefined
Yx:/x
High-Z
Undefined
Divider State
T0070-01
Figure 17. Signal State After an Output Driver Becomes Enabled While IN = 1
18
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
CDCM1804RGER
ACTIVE
VQFN
RGE
24
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
CDCM
1804
CDCM1804RGET
ACTIVE
VQFN
RGE
24
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
CDCM
1804
SN0305042RTHR
ACTIVE
VQFN
RGE
24
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
CDCM
1804
SN0305042RTHT
ACTIVE
VQFN
RGE
24
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
CDCM
1804
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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