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CDCM6208V1F
SCAS943 – MAY 2015
CDCM6208V1F 2:8 Clock Generator, Jitter Cleaner with Fractional Dividers
1 Features
2 Applications
•
•
•
•
•
•
1
•
•
•
•
•
•
Superior Performance with Low Power:
– Low Noise Synthesizer (265 fs-rms Typical
Jitter) or Low Noise Jitter Cleaner (1.6 ps-rms
Typical Jitter)
– 0.5 W Typical Power Consumption
– High Channel-to-Channel Isolation and
Excellent PSRR
– Device Performance Customizable Through
Flexible 1.8 V, 2.5 V and 3.3 V Power
Supplies, Allowing Mixed Output Voltages
Flexible Frequency Planning:
– 4x Integer Down-divided Differential Clock
Outputs Supporting LVPECL-like, CML, or
LVDS-like Signaling
– 4x Fractional or Integer Divided Differential
Clock Outputs Supporting HCSL, LVDS-like
Signaling, or Eight CMOS Outputs
– Fractional Output Divider Achieve 0 ppm to < 1
ppm Frequency Error and Eliminates need for
Crystal Oscillators and Other Clock Generators
– Output frequencies up to 800 MHz
Two Differential Inputs, XTAL Support, Ability for
Smart Switching
SPI, I2C™, and Pin Programmable
Professional user GUI for Quick Design
Turnaround
7 x 7 mm 48-QFN package (RGZ)
-40 °C to 85 °C temperature range
Base Band Clocking (Wireless Infrastructure)
Networking and Data Communications
Keystone C66x Multicore DSP Clocking
Storage Server, Portable Test Equipment,
Medical Imaging, High End A/V
3 Description
The CDCM6208V1F is a highly versatile, low jitter,
low-power frequency synthesizer that can generate
eight low jitter clock outputs, selectable between
LVPECL-like high-swing CML, normal-swing CML,
LVDS-like low-power CML, HCSL, or LVCMOS, from
one of two inputs that can feature a low frequency
crystal or CML, LVPECL, LVDS, or LVCMOS signals
for a variety of wireless infrastructure baseband,
wireline data communication, computing, low power
medical imaging and portable test and measurement
applications. The CDCM6208V1F also features an
innovative fractional divider architecture for four of its
outputs that can generate any frequency with better
than 1ppm frequency accuracy. The CDCM6208V1F
can be easily configured through I2C or SPI
programming interface and in the absence of serial
interface, pin mode is also available that can set the
device in 1 of 32 distinct pre-programmed
configurations using control pins.
Device Information(1)
PART NUMBER
PACKAGE
CDCM6208V1F
BODY SIZE (NOM)
VQFN (48)
7.00 mm × 7.00 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
Timing
DR
Packet
Accel
PCIe
Core
Packet
network
Synthesizer
Mode
TMS320TCI6616/18
DSP
AIF
ALT
CORE
FBADC
SyncE
Eth
CDCM6208
Server
4 Simplified Schematics
e
ern
RXADC
TXDAC
t
GPS receiver
1pps
DPLL
Ethernet
IEEE1588
timing extract
1pps
CDCM6208
RF LO
APLL
RF LO
Pico Cell Clocking
SRIO
Base Band DSP
Clocking
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
CDCM6208V1F
SCAS943 – MAY 2015
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Simplified Schematics...........................................
Revision History.....................................................
Description (continued).........................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
1
2
3
3
6
8.20
8.21
8.22
8.23
8.24
9
Characteristics ......................................................... 15
Device Individual Block Current Consumption...... 16
Worst Case Current Consumption ........................ 17
I2C TIMING .......................................................... 18
SPI Timing Requirements ..................................... 19
Typical Characteristics ......................................... 20
Parameter Measurement Information ................ 22
9.1 Characterization Test Setup ................................... 22
10 Detailed Description ........................................... 28
8.1
8.2
8.3
8.4
8.5
8.6
8.7
8.8
8.9
Absolute Maximum Ratings ..................................... 6
ESD Ratings.............................................................. 6
Recommended Operating Conditions....................... 7
Thermal Information, Airflow = 0 LFM ..................... 7
Thermal Information, Airflow = 150 LFM ................. 8
Thermal Information, Airflow = 250 LFM ................. 8
Thermal Information, Airflow = 500 LFM ................. 8
Single Ended Input Characteristics .......................... 9
Single Ended Input Characteristics (PRI_REF,
SEC_REF) ................................................................. 9
8.10 Differential Input Characteristics (PRI_REF,
SEC_REF) ............................................................... 10
8.11 Crystal Input Characteristics (SEC_REF) ............. 10
8.12 Single Ended Output Characteristics (STATUS1,
STATUS0, SDO, SDA) ............................................ 11
8.13 PLL Characteristics ............................................... 11
8.14 LVCMOS Output Characteristics .......................... 12
8.15 LVPECL (High-Swing CML) Output
Characteristics ......................................................... 13
8.16 CML Output Characteristics.................................. 13
8.17 LVDS (Low-Power CML) Output Characteristics. 14
8.18 HCSL Output Characteristics............................... 14
8.19 Output Skew and Sync to Output Propagation Delay
10.1
10.2
10.3
10.4
10.5
10.6
Overview ...............................................................
Functional Block Diagram .....................................
Feature Description...............................................
Device Functional Modes......................................
Programming.........................................................
Register Maps .......................................................
28
28
29
30
38
42
11 Application and Implementation........................ 53
11.1 Application Information.......................................... 53
11.2 Typical Applications .............................................. 53
12 Power Supply Recommendations ..................... 72
12.1 Power Rail Sequencing, Power Supply Ramp Rate,
and Mixing Supply Domains .................................... 72
13 Layout................................................................... 74
13.1 Layout Guidelines ................................................. 74
13.2 Layout Example .................................................... 74
14 Device and Documentation Support ................. 80
14.1
14.2
14.3
14.4
Trademarks ...........................................................
Documentation Support .......................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
80
80
80
80
15 Mechanical, Packaging, and Orderable
Information ........................................................... 80
5 Revision History
2
DATE
REVISION
NOTES
May 2015
*
Initial release.
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6 Description (continued)
In synthesizer mode, the overall output jitter performance is less than 0.5 ps-rms (10 k - 20 MHz) or 20 ps-pp
(unbound) on output using integer dividers and is between 50 to 220 ps-pp (10 k - 40 MHz) on outputs using
fractional dividers depending on the prescaler output frequency.
In jitter cleaner mode, the overall output jitter is less than 2.1 ps-rms (10 k - 20 MHz) or 40 ps-pp on output
using integer dividers and is less than 70 ps to 240 ps-pp on outputs using fractional dividers. The
CDCM6208V1F is packaged in a small 48-pin 7 mm x 7 mm QFN package.
7 Pin Configuration and Functions
Y7_N
VDD_Y4
SEC_REFP
11
26
Y4_P
SEC_REFN
12
25
Y4_N
Y2_P
VDD_Y2_Y3
VDD_Y2_Y3
VDD _Y0_Y1
24
27
23
10
Y3_P
Y5_N
VDD_SEC_REF
22
28
Y3_N
9
Y2_N
Y5_P
PRI_REFN
21
PRI_REFP
29
20
VDD_Y5
8
19
VDD_Y6
30
VDD_Y2_Y3
31
7
VDD_Y0_Y1
6
VDD_PRI_REF
18
Y6_P
17
32
Y1_P
5
REF_SEL
16
SCL/PIN4
Y0_N
Y6_N
Y1_N
33
15
4
14
VDD_Y7
SCS/AD1/PIN3
Y0_P
Y7_P
34
13
35
3
VDD_Y0_Y1
2
VDD_SECI_REF
VDD_PRI_REF
SDI/SDA/PIN1
SDO/AD0/PIN2
VDD_Y7
37
36
VDD_Y6
VDD_PLL1
38
1
VDD_Y5
VDD_PLL2
39
SI_MODE0
VDD_Y4
REG_CAP
VDD_VCO
40
ELF
41
42
PDN
RESETN/PWR
44
SYNCN
STATUS1/PIN0
45
43
SI_MODE1
STATUS0
46
DVDD
48
DVDD
47
RGZ Package
48 Pin VQFN
Top View
Pin Functions
PIN
NAME
NO.
I/O
TYPE
DESCRIPTION
PRI_REFP
8
Input
Universal
Primary Reference Input +
PRI_REFN
9
Input
Universal
Primary Reference Input –
VDD_PRI_REF
7
PWR
Analog
Supply pin for reference inputs to set between 1.8 V, 2.5 V, or 3.3 V or connect to
VDD_SEC_REF.
SEC_REFP
11
Input
Universal
Secondary Reference Input +
SEC_REFN
12
Input
Universal
Secondary Reference Input –
VDD_SEC_REF
10
PWR
Analog
(1)
Supply pin for reference inputs to set between 1.8 V, 2.5 V, or 3.3 V or connect to
VDD_PRI_REF (1).
If Secondary input buffer is disabled (Register 4 Bit 5 = 0), it is possible to connect VDD_SEC_REF to GND.
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Pin Functions (continued)
PIN
NAME
I/O
TYPE
LVCMOS
w/ 50kΩ pull-up
REF_SEL
6
Input
DESCRIPTION
Manual Reference Selection MUX for PLL. In SPI or I2C mode the reference
selection is also controlled through Register 4 bit 12.REF_SEL = 0 (≤ VIL): selects
PRI_REFREF_SEL = 1 (≥ VIH): selects SEC_REF (when Reg 4.12 = 1). See
Table 36 for detail.
ELF
41
Output
Analog
Y0_P
14
Output
Universal
Output 0 Positive Terminal
Y0_N
15
Output
Universal
Output 0 Negative Terminal
External loop filter pin for PLL
Y1_P
17
Output
Universal
Output 1 Positive Terminal
Y1_N
16
Output
Universal
Output 1 Negative Terminal
VDD_Y0_Y1 (2
pins)
13,
18
PWR
Analog
Supply pin for outputs 0, 1 to set between 1.8 V, 2.5 V or 3.3 V
Y2_P
20
Output
Universal
Output 2 Positive Terminal
Y2_N
21
Output
Universal
Output 2 Negative Terminal
Y3_P
23
Output
Universal
Output 3 Positive Terminal
Output 3 Negative Terminal
Y3_N
22
Output
Universal
VDD_Y2_Y3 (2
pins)
19,
24
PWR
Analog
Supply pin for outputs 2, 3 to set between 1.8 V, 2.5 V or 3.3 V
Y4_P
26
Output
Universal
Output 4 Positive Terminal
Y4_N
25
Output
Universal
Output 4 Negative Terminal
VDD_Y4
27
PWR
Analog
Supply pin for output 4 to set between 1.8 V, 2.5 V or 3.3 V
Y5_P
29
Output
Universal
Output 5 Positive Terminal
Y5_N
28
Output
Universal
Output 5 Negative Terminal
VDD_Y5
30
PWR
Analog
Y6_P
32
Output
Universal
Output 6 Positive Terminal
Output 6 Negative Terminal
Supply pin for output 5 to set between 1.8 V, 2.5 V or 3.3 V
Y6_N
33
Output
Universal
VDD_Y6
31
PWR
Analog
Y7_P
35
Output
Universal
Output 7 Positive Terminal
Output 7 Negative Terminal
Supply pin for output 6 to set between 1.8 V, 2.5 V or 3.3 V
Y7_N
36
Output
Universal
VDD_Y7
34
PWR
Analog
Supply pin for output 7 to set between 1.8 V, 2.5 V or 3.3 V
VDD_VCO
39
PWR
Analog
Analog power supply for PLL/VCO; This pin is sensitive to power supply noise; The
supply of this pin and the VDD_PLL2 supply pin can be combined as they are both
analog and sensitive supplies;
VDD_PLL1
37
PWR
Analog
Analog Power Supply Connections
VDD_PLL2
38
PWR
Analog
Analog Power Supply Connections; This pin is sensitive to power supply noise; The
supply of VDD_PLL2 and VDD_VCO can be combined as these pins are both
power-sensitive, analog supply pins
DVDD
48
PWR
Analog
Digital Power Supply Connections; This is also the reference supply voltage for all
control inputs and must match the expected input signal swing of control inputs.
GND
PAD
PWR
Analog
Power Supply Ground and Thermal Pad
STATUS0
46
Output
LVCMOS
STATUS1/PIN0
45
Output
and
Input
LVCMOS
no pull resistor
SI_MODE1
47
Input
LVCMOSw
50kΩ pull-up
SI_MODE0
1
LVCMOSw
50kΩ pull-down
2
LVCMOS in
Open drain out
LVCMOS in
no pull resistor
SDI/SDA/PIN1
4
NO.
I/O
Status pin 0 (see Table 7 for details)
STATUS1: Status pin in SPI/I2C modes. For details see Table 6 for pin modes and
Table 7 for status mode. PIN0: Control pin 0 in pin mode.
Serial Interface Mode or Pin mode selection.SI_MODE[1:0]=00: SPI
mode;SI_MODE[1:0]=01: I2C mode;SI_MODE[1:0]=10: Pin Mode (No serial
programming);SI_MODE[1:0]=11: RESERVED
SDI: SPI Serial Data Input SDA: I2C Serial Data (Read/Write bi-directional), open
drain output; requires a pull-up resistor in I2C mode;PIN1: Control pin 1 in pin mode
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SCAS943 – MAY 2015
Pin Functions (continued)
PIN
I/O
TYPE
3
Output/I
nput
LVCMOS out
LVCMOS in
LVCMOS in
no pull resistor
SDO: SPI Serial Data AD0: I2C Address Offset Bit 0 inputPIN2: Control pin 2 in pin
mode
SCS/AD1/PIN 3
4
Input
LVCMOS no pull
resistor
SCS: SPI Latch EnableAD1: I2C Address Offset Bit 1 inputPIN3: Control pin 3 in pin
mode
SCL/PIN4
5
Input
LVCMOS no pull
resistor
SCL: SPI/I2C ClockPIN4: Control pin 4 in pin mode
In SPI/I2C programming mode, external RESETN signal (active low).
RESETN = V IL: device in reset (registers values are retained)
RESETN = V IH: device active. The device can be programmed via SPI while
RESETN is held low (this is useful to avoid any false output frequencies at power
up). (2)
In Pin mode this pin controls device core and I/O supply voltage setting. 0 = 1.8 V, 1
= 2.5/3.3 V for the device core and I/O power supply voltage. In pin mode, it is not
possible to mix and match the supplies. All supplies should either be 1.8 V or 2.5/3.3
V.
NAME
NO.
SDO/AD0/PIN2
DESCRIPTION
RESETN/PWR
44
Input
LVCMOS
w/ 50kΩ pull-up
REG_CAP
40
Output
Analog
Power Down Active low. When PDN = VIH is normal operation. When PDN = VIL, the
device is disabled and current consumption minimized. Exiting power down resets
the entire device and defaults all registers. It is recommended to connect a capacitor
to GND to hold the device in power-down until the digital and PLL related power
supplies are stable. See section on power down in the application section.
Active low. Device outputs are synchronized on a low-to-high transition on the
SYNCN pin. SYNCN held low disables all outputs.
(2)
Regulator Capacitor; connect a 10 µF cap with ESR below 1 Ω to GND at
frequencies above 100 kHz
PDN
43
Input
LVCMOS
w/ 50kΩ pull-up
SYNCN
42
Input
LVCMOS
w/ 50kΩ pull-up
Note: the device cannot be programmed in I2C while RESETN is held low.
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8 Specifications
8.1 Absolute Maximum Ratings (1)
over operating free-air temperature range (unless otherwise noted)
MIN
MAX
UNIT
Supply Voltage Range, VDD_PRI, VDD_SEC, VDD_Yx_Yy, VDD_PLL[2:1], DVDD
PARAMETER
-0.5
4.6
V
Input Voltage Range CMOS control inputs, VIN
-0.5
4.6
and
V DVDD+ 0.5
V
4.6
and
Input Voltage Range PRI/SEC inputs
V
VVDDPRI.SEC+ 0.5
Output Voltage Range, VOUT
-0.5
VYxYy+ 0.5
V
Input Current, IIN
20
mA
Output Current, IOUT
50
mA
Junction Temperature, TJ
125
°C
150
°C
Storage temperature range, Tstg
(1)
-65
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute—maximum—rated conditions for extended periods may affect device reliability.
8.2 ESD Ratings
VALUE
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins
V(ESD)
(1)
(2)
6
Electrostatic discharge
(1)
UNIT
±2000
Charged device model (CDM), per JEDEC specification JESD22-C101, all
pins (2)
±500
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
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8.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
UNIT
VDD_Yx_Yy
Output Supply Voltage
1.71
1.8/2.5/3.3
3.465
V
VDD_PLL1
VDD_PLL2
Core Analog Supply Voltage
1.71
1.8/2.5/3.3
3.465
V
DVDD
Core Digital Supply Voltage
1.71
1.8/2.5/3.3
3.465
V
VDD_PRI,
VDD_SEC
Reference Input Supply Voltage
1.71
1.8/2.5/3.3
3.465
V
ΔVDD/Δt
VDD power-up ramp time (0 to 3.3 V) PDN left open, all VDD tight
together PDN low-high is delayed (1)
TA
Ambient Temperature
SDA and SCL in I
VI
2
50 < tPDN
ms
-40
85
°C
DVDD = 1.8 V
–0.5
2.45
V
DVDD = 3.3 V
–0.5
3.965
V
C MODE (SI_MODE[1:0] = 01)
Input Voltage
100
400
dR
Data Rate
VIH
High-level input voltage
VIL
Low-level input voltage
CBUS_I2C
Total capacitive load for each bus line
(1)
kbps
0.7 x
DVDD
V
0.3 x DVDD
V
400
pF
For fast power up ramps under 50 ms and when all supply pins are driven from the same power supply source, PDN can be left floating.
For slower power up ramps or if supply pins are sequenced with uncertain time delays, PDN needs to be held low until DVDD,
VDD_PLLx, and VDD_PRI/SEC reach at least 1.45V supply voltage. See application section on mixing power supplies and particularly
Figure 58 for details.
8.4 Thermal Information, Airflow = 0 LFM (1)
(2) (3) (4)
CDCM6208
THERMAL METRIC
(1)
RGZ
UNIT
48 PINS VQFN
RθJA
Junction-to-ambient thermal resistance
30.27
RθJC(top)
Junction-to-case (top) thermal resistance
16.58
RθJB
Junction-to-board thermal resistance
6.83
ψJT
Junction-to-top characterization parameter
0.23
ψJB
Junction-to-board characterization parameter
6.8
RθJC(bot)
Junction-to-case (bottom) thermal resistance
1.06
(1)
(2)
(3)
(4)
°C/W
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
The package thermal resistance is calculated in accordance with JESD 51 and JEDEC2S2P (high-k board).
Connected to GND with 36 thermal vias (0.3 mm diameter).
θJB (junction to board) is used for the QFN package, the main heat flow is from the junction to the GND pad of the QFN.
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8.5 Thermal Information, Airflow = 150 LFM (1)
(2) (3) (4)
CDCM6208
THERMAL METRIC (1)
RGZ
UNIT
48 PINS
RθJA
Junction-to-ambient thermal resistance
RθJC(top)
Junction-to-case (top) thermal resistance
RθJB
Junction-to-board thermal resistance
6.61
ψJT
Junction-to-top characterization parameter
0.37
ψJB
Junction-to-board characterization parameter
RθJC(bot)
Junction-to-case (bottom) thermal resistance
(1)
(2)
(3)
(4)
21.8
°C/W
1.06
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
The package thermal resistance is calculated in accordance with JESD 51 and JEDEC2S2P (high-k board).
Connected to GND with 36 thermal vias (0.3 mm diameter).
θJB (junction to board) is used for the QFN package, the main heat flow is from the junction to the GND pad of the QFN.
8.6 Thermal Information, Airflow = 250 LFM (1)
(2) (3) (4)
CDCM6208
THERMAL METRIC (1)
RGZ
UNIT
48 PINS
RθJA
Junction-to-ambient thermal resistance
RθJC(top)
Junction-to-case (top) thermal resistance
RθJB
Junction-to-board thermal resistance
6.6
ψJT
Junction-to-top characterization parameter
0.45
ψJB
Junction-to-board characterization parameter
RθJC(bot)
Junction-to-case (bottom) thermal resistance
(1)
(2)
(3)
(4)
19.5
°C/W
1.06
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
The package thermal resistance is calculated in accordance with JESD 51 and JEDEC2S2P (high-k board).
Connected to GND with 36 thermal vias (0.3 mm diameter).
θJB (junction to board) is used for the QFN package, the main heat flow is from the junction to the GND pad of the QFN.
8.7 Thermal Information, Airflow = 500 LFM (1)
(2) (3) (4)
CDCM6208
THERMAL METRIC
(1)
RGZ
UNIT
48 PINS
RθJA
Junction-to-ambient thermal resistance
RθJC(top)
Junction-to-case (top) thermal resistance
RθJB
Junction-to-board thermal resistance
6.58
ψJT
Junction-to-top characterization parameter
0.58
ψJB
Junction-to-board characterization parameter
RθJC(bot)
Junction-to-case (bottom) thermal resistance
(1)
(2)
(3)
(4)
8
17.7
°C/W
1.05
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
The package thermal resistance is calculated in accordance with JESD 51 and JEDEC2S2P (high-k board).
Connected to GND with 36 thermal vias (0.3 mm diameter).
θJB (junction to board) is used for the QFN package, the main heat flow is from the junction to the GND pad of the QFN.
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8.8 Single Ended Input Characteristics
(SI_MODE[1:0], SDI/SDA/PIN1, SCL/PIN4, SDO/ADD0/PIN2, SCS/ADD1/PIN3, STATUS1/PIN0, RESETN/PWR, PDN,
SYNCN, REF_SEL), DVDD = 1.71V to 1.89V, 2.375V to 2.625V, 3.135V to 3.465V, TA = –40°C to 85°C
PARAMETER
VIH
Input High Voltage
VIL
Input Low Voltage
TEST CONDITIONS
MIN
TYP
MAX
UNIT
0.8 x DVDD
IIH
Input High Current
DVDD = 3.465V, VIH = 3.465 V (pull-up
resistor excluded)
IIL
Input Low Current
DVDD = 3.465V, VIL= 0 V
ΔV/ΔT
PDN, RESETN, SYNCN, REF_SEL Input
Edge Rate
20% - 80%
minPulse
PDN, RESETN, SYNCN low pulse to
trigger proper device reset
C IN
Input Capacitance
V
0.2 x DVDD
V
30
µA
-30
µA
0.75
V/ns
10
ns
2.25
pF
RESETN, PWR, SYNCN, PDN, REF_SEL, SI_MODE[1:0]:
R
Input Pullup and Pulldown Resistor
35
50
65
kΩ
SDA and SCL in I 2 C Mode (SI_MODE[1:0]=01)
DVDD = 1.8 V
VHYS_I2C
Input hysteresis
IH
High-level input current
VI = DVDD
VOL
Output Low Voltage
IOL= 3mA
CIN
Input Capacitance terminal
8.9
DVDD = 2.5/3.3 V
0.1 VDVDD
V
0.05 VDVDD
V
–5
5
µA
0.2 x DVDD
V
5
pF
Single Ended Input Characteristics (PRI_REF, SEC_REF)
VDD_PRI, VDD_SEC = 1.71 V to 1.89 V, 2.375 V to 2.625 V, 3.135 V to 3.465 V, TA = –40°C to 85°C
PARAMETER
fIN
Reference and Bypass Input
Frequency
MAX
UNIT
VDD_PRI/SEC = 1.8 V
TEST CONDITIONS
0.008
MIN
TYP
200
MHz
VDD_PRI/SEC = 3.3 V
0.008
250
MHz
0.8 x
VDD_PRI/V
DD_SEC
VIH
Input High Voltage
VIL
Input Low Voltage
VHYST
Input hysteresis
IIH
Input High Current
VDD_PRI/VDD_SEC = 3.465 V, VIH = 3.465 V
IIL
Input Low Current
VDD_PRI/VDD_SEC = 3.465 V, VIL = 0 V
ΔV/ΔT
Reference Input Edge Rate
20% - 80%
0.75
IDC SE
Reference Input Duty Cycle
f PRI ≤ 200MHz
40%
200 ≤ fPRI ≤ 250 MHz
43%
CIN
Input Capacitance
V
0.2 x
VDD_PRI/V
DD_SEC
20
65
150
mV
30
µA
-30
60%
60%
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V/ns
2.25
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V
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8.10 Differential Input Characteristics (PRI_REF, SEC_REF)
VDD_PRI, VDD_SEC = 1.71 V to 1.89 V, 2.375 V to 2.625 V, 3.135 V to 3.465 V, TA = –40°C TO 85°C
PARAMETER
fIN
TEST CONDITIONS
MAX
UNIT
0.008
250
MHz
VDD_PRI/SEC = 2.5/3.3 V
0.2
1.6
VPP
VDD_PRI/SEC = 1.8 V
0.2
1
VPP
VDD_PRI/V
DD_SEC0.4
VDD_PRI/V
DD_SEC0.1
V
1.5
V
Reference and Bypass Input Frequency
Differential Input Voltage Swing, Peak-toPeak
VI
MIN
TYP
VICM
Input Common Mode Voltage
CML input signaling, R4[7:6] = 00
VICM
Input Common Mode Voltage
LVDS, VDD_PRI/SEC
= 1.8/2.5/3.3 V,
R4[7:6] = 01, R4.1 = d.c.,
R4.0 = d.c.
0.8
VHYST
Input hysteresis
LVDS (Q4[7:6,4:3] = 01)
15
65
mVpp
CML (Q4[7:6,4:3] = 00)
20
85
mVpp
IIH
Input High Current
VDD_PRI/SEC = 3.465 V, VIH = 3.465 V
30
µA
IIL
Input Low Current
VDD_PRI/SEC = 3.465V, VIL = 0 V
ΔV/ΔT
Reference Input Edge Rate
20% - 80%
IDCDIFF
Reference Input Duty Cycle
CIN
Input Capacitance
1.2
-30
0.75
µA
V/ns
30%
70%
2.7
pF
8.11 Crystal Input Characteristics (SEC_REF)
VDD_SEC = 1.71 to 1.89 V, 2.375 V to 2.625 V, 3.135 V to 3.465 V,TA = –40°C to 85°C
PARAMETER
MIN
MODE OF OSCILLATION
Frequency
Equivalent Series Resistance (ESR)
On-chip load capacitance
Drive Level
(1)
(2)
(3)
(4)
(5)
(6)
10
TYP
MAX
UNIT
FUNDAMENTAL
See note
(1)
10
30.72
MHz
See note
(2)
30.73
50
MHz
10 MHz
150 (3)
25 MHz
70 (4)
50 MHz
30 (5)
1.8 V / 3.3 V SEC_REFP
3.5
4.5
5.5
1.8 V SEC_REFN
5.5
7.25
8.5
3.3 V SEC_REFN
6.5
7.34
8.5
See note
(6)
200
Ω
pF
µW
Verified with crystals specified for a load capacitance of CL=8pF, the pcb related capacitive load was estimated to be 2.3pF, and
completed with a load capacitors of 4pF on each crystal terminal connected to GND. XTALs tested: NX3225GA 10MHz EXS00ACG02813 CRG, NX3225GA 19.44MHz EXS00A-CG02810 CRG, NX3225GA 25MHz EXS00A-CG02811 CRG, and NX3225GA
30.72MHz EXS00A-CG02812 CRG.
For 30.73 MHz to 50 MHz, it is recommended to verify sufficient negative resistance and initial frequency accuracy with the crystal
vendor. The 50 MHz use case was verified with a NX3225GA 50MHz EXS00A-CG02814 CRG. To meet a minimum frequency error, the
best choice of the XTAL was one with CL = 7pF instead of CL = 8pF.
With NX3225GA_10M the measured remaining negative resistance on the EVM is 6430 Ω (43 x margin)
With NX3225GA_25M the measured remaining negative resistance on the EVM is 1740 Ω (25 x margin)
With NX3225GA_50M the measured remaining negative resistance on the EVM is 350 Ω (11 x margin)
Maximum drive level measured was 145 µW; XTAL should at least tolerate 200 µW
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8.12 Single Ended Output Characteristics (STATUS1, STATUS0, SDO, SDA)
VDD_Yx_Yy, VDD_PRI, VDD_SEC, VDD_PLLx, DVDD, VDD_VCO = 1.71V to 1.89V, 2.375V to 2.625V, 3.135V to 3.465V;
TA = –40°C to 85°C (Output load capacitance 10 pF unless otherwise noted)
PARAMETER
TEST CONDITIONS
VOH
Output High Voltage
Status 1, Status 0, and SDO only;
SDA is open drain and relies on
external pullup for high output; IOH =
1 mA
VOL
Output Low Voltage
IOL = 1 mA
Vslew
Output slew rate
30% - 70%
IOZH
3-stat Output High Current
DVDD = 3.465 V, VIH = 3.465 V
IOZL
3-stat Output Low Current
DVDD = 3.465 V, VIL = 0 V
tLOS
Status Loss of Signal Detection
Time
LOS_REFfvco
tLOCK
Status PLL Lock Detection Time
MIN
TYP
MAX
UNIT
0.8 x
DVDD
V
0.2 x
DVDD
0.5
V/ns
1
Detect lock
5
µA
-5
µA
2
1/f PFD
2304
Detect unlock
V
1/f PFD
512
8.13 PLL Characteristics
VDD_PLLx, VDD_VCO = 1.71 V to 1.89 V, 2.375 V to 2.625 V, 3.135 V to 3.465 V, TA = –40°C TO 85°C
PARAMETER
fVCO
VCO Frequency Range
KVCO
VCO Gain
fPFD
PFD Input Frequency
ICP-L
High Impedance Mode Charge
Pump Leakage
fFOM
Estimated PLL Figure of Merit
(FOM)
tSTARTUP
Startup time (see Figure 42 )
TEST CONDITIONS
MIN
TYP
2.39
2.39 GHz
178
2.50 GHz
204
2.55 GHz
213
0.008
Measured in-band phase noise at
the VCO output minus 20log(Ndivider) at the flat region
MAX
UNIT
2.55
GHz
MHz/V
100
MHz
±700
nA
–224
dBc/Hz
12.8
ms
12.85
ms
Power supply ramp time of 1ms from
0 V to 1.7 V, final frequency
accuracy of 10 ppm, fPFD = 25 MHz,
CPDN_to_GND = 22nF
w/ PRI input signal
w/ NDK 25 MHz crystal
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8.14 LVCMOS Output Characteristics
VDD_Yx_Yy = 1.71 V to 1.89V, 2.375 V to 2.625 V, 3.135 V to 3.465 V, TA = –40°C TO 85°C
PARAMETER
TEST CONDITIONS
Fract Out divVDD_Yx_Yy = 2.5/3.3 V
fOUT-F
Output Frequency
Integer out divVDD_Yx_Yy = 2.5/3.3 V
Int or frac out divVDD_Yx_Yy = 1.8 V
fACC-F
Output Frequency Error
(1)
Fractional Output Divider
VOH
Output High Voltage (normal mode)
VDD_Yx = min to max, IOH = -1 mA
VOL
Output Low Voltage(normal mode)
VDD_Yx = min to max, IOL = 100 µA
VOH
Output High Voltage (slow mode)
VDD_Yx = min to max, IOH = -100 µA
VOL
Output Low Voltage(slow mode)
VDD_Yx = min to max, IOL = 100 µA
IOH
Output High Current
MIN
TYP
MAX
0.78
250
1.55
250
0.78/1.5
200
–1
1
0.8 x
VDD_Yx_Yy
UNIT
MHz
ppm
V
0.2 x
VDD_Yx_Yy
0.7 x
VDD_Yx_Yy
V
V
0.3 x
VDD_Yx_Yy
V
V OUT = VDD_Yx_Yy/2
Normal mode
–50
-8
mA
Slow mode
–45
-5
mA
Normal mode
10
55
mA
Slow mode
5
40
mA
V OUT = VDD_Yx_Yy/2
IOL
Output Low Current
Output Rise/Fall Slew Rate (normal
mode)
20% to 80%, VDD_Yx_Yy = 2.5/3.3 V,
CL = 5 pF
5.37
V/ns
Output Rise/Fall Slew Rate (normal
mode)
20% to 80%, VDD_Yx_Yy = 1.8 V,
CL = 5 pF
2.62
V/ns
Output Rise/Fall Slew Rate (slow
mode)
20% to 80%, VDD_Yx_Yy = 2.5/3.3 V,
CL = 5 pF
4.17
V/ns
Output Rise/Fall Slew Rate (slow
mode)
20% to 80%, VDD_Yx_Yy = 1.8 V,
CL = 5 pF
1.46
V/ns
PN-floor
Phase Noise Floor
fOUT = 122.88 MHz
ODC
Output Duty Cycle
Not in bypass mode
ROUT
Output Impedance
tSLEW-RATE-N
tSLEW-RATE-S
–159.5
45%
–154
dBc/Hz
55%
V OUT = VDD_Yx/2
(1)
12
Normal mode
Slow mode
30
45
50
74
90
130
Ω
The User's GUI calculates exact frequency error. It is a fixed, static offset. If the desired output target frequency is with the exact reach
of a multiple 1 over 220, the actual output frequency error is 0.
Note: In LVCMOS Mode, positive and negative outputs are in phase.
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8.15
SCAS943 – MAY 2015
LVPECL (High-Swing CML) Output Characteristics
VDD_Yx_Yy = 1.71 V to 3.465 V, VDD_PRI, VDD_SEC, VDD_PLLx, DVDD, VDD_VCO = 1.71 V to 1.89 V, 2.375 V to 2.625
V, 3.135 V to 3.465 V, TA = –40°C TO 85°C
PARAMETER
fOUT-I
VCM-DC
TEST CONDITIONS
Output frequency
MIN
Integer Output Divider
Output DC coupled common mode
voltage
TYP
1.55
MAX
UNIT
800
MHz
VDD_Yx
_
Yy – 0.4
DC coupled with 50 Ω external termination to VDD_Yx_Yy
V
100 Ω diff load AC coupling (See Figure 12), fOUT ≤ 250 MHz
|VOD|
Differential output voltage
VDD_Yx_Yy ≤ 1.89 V
0.45
0.75
1.12
V
VDD_Yx_Yy ≥ 2.375 V
0.6
0.8
1.12
V
100 Ω diff load AC coupling (See Figure 12), fOUT ≥ 250 MHz
VDD_Yx_Yy ≤ 1.89 V
0.73
VDD_Yx_Yy ≥ 2.375 V
0.55
VOUT
Differential output peak-to-peak
voltage
tR/tF
Output rise/fall time
tslew
Output rise/fall slew rate
PN-floor
Phase noise floor
VDD_Yx_Yy = 3.3 V (See Figure 54)
ODC
Output duty cycle
Not in bypass mode
ROUT
Output impedance
measured from pin to VDD_Yx_Yy
0.75
V
1.12
V
2 x |VOD|
±200 mV around crossing point
109
20% to 80% VOD
V
217
ps
5.1
7.3
V/ns
–161.4
–155.8
211
3.7
47.5%
ps
dBc/Hz
52.5%
Ω
50
8.16 CML Output Characteristics
VDD_Yx_Yy, VDD_PRI, VDD_SEC, VDD_PLLx, DVDD, VDD_VCO = 1.71V to 1.89V, 2.375V to 2.625V, 3.135V to 3.465V,
TA = –40°C to 85°C
PARAMETER
TEST CONDITIONS
MIN
TYP
1.55
MAX
UNIT
800
MHz
fOUT-I
Output frequency
Integer Output Divider
VCM-AC
Output AC coupled common
mode voltage
AC coupled with 50 Ω receiver termination
VDD_Yx_Yy – 0.46
V
VCM-DC
Output DC coupled common
mode voltage
DC coupled with 50 Ω on-chip termination
to VDD_Yx_Yy
VDD_Yx_Yy – 0.2
V
|VOD|
Differential output voltage
100 Ω diff load AC coupling, (See Figure 12)
VOUT
Differential output peak-to-peak
voltage
tR/tF
Output rise/fall time
0.3
0.45
0.58
2 x |VOD|
20% to 80%
V
V
VDDYx = 1.8 V
100
151
300
VDDYx = 2.5 V/3.3 V
100
143
200
–161.2
–155.8
dBc/Hz
–161.2
–153.8
dBc/Hz
VDD_Yx_Yy = 1.8 V
PN-floor
Phase noise floor at > 5 Hz offset
fOUT = 122.88 MHz
ODC
Output duty cycle
Not in bypass mode
ROUT
Output impedance
measured from pin to VDD_Yx_Yy
VDD_Yx_Yy = 3.3 V
47.5%
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ps
52.5%
50
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Ω
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LVDS (Low-Power CML) Output Characteristics
VDD_Yx_Yy, VDD_PRI, VDD_SEC, VDD_PLLx, DVDD, VDD_VCO = 1.71 V to 1.89 V, 2.375 V to 2.625 V, 3.135V to
3.465V, TA = –40°C to 85°C
PARAMETER
fOUT-I
TEST CONDITIONS
Output frequency
fOUT-F
(1)
MAX
UNIT
Integer output divider
1.55
MIN
TYP
400
MHz
Fractional output divider
0.78
400
MHz
Fractional output divider
-1
1
ppm
fACC-F
Output frequency error
VCM-AC
Output AC coupled
common mode voltage
AC coupled with 50 Ω receiver termination
VDD_Yx_Yy – 0.76
V
VCM-DC
Output DC coupled
common mode voltage
DC coupled with 50 Ω on-chip termination to VDD_Yx_Yy
VDD_Yx_Yy – 0.13
V
|VOD|
Differential output voltage
100 Ω diff load AC coupling, (See Figure 12)
VOUT
Differential output peak-topeak voltage
tR/tF
Output rise/fall time
PN-floor
Phase noise floor
0.34
0.454
2 x |VOD|
±100mV around crossing point
fOUT= 122.88 MHz
VDD_Yx = 2.5/3.3 V
Y[3:0]
47.5%
Y[7:4]
45%
Output duty cycle
Not in bypass mode
ROUT
Output impedance
Measured from pin to VDD_Yx_Yy
V
V
300
VDD_Yx = 1.8 V
ODC
(1)
0.247
ps
–159.3
–154.5
dBc/Hz
–159.1
–154.9
dBc/Hz
52.5%
55%
Ω
167
The User's GUI calculates exact frequency error. It is a fixed, static offset. If the desired output target frequency is with the exact reach
of a multiple of 1 over 220, the actual output frequency error is 0.
8.18
HCSL Output Characteristics
VDD_Yx_Yy, VDD_PRI, VDD_SEC, VDD_PLLx, DVDD, VDD_VCO = 1.71 to 1.89 V, 2.375 V to 2.625 V,3.135 V to 3.465 V,
TA = –40°C to 85°C
PARAMETER
fOUT-I
TEST CONDITIONS
Output frequency
fOUT-F
fACC-F
Output Frequency Error
VCM
(1)
Output Common Mode Voltage
|VOD|
Differential Output Voltage
VOUT
Differential Output Peak-to-peak
Voltage
tR/tF
Output Rise/Fall Time
MAX
UNIT
Integer Output Divider
1.55
400
MHz
Fractional Output Divider
0.78
400
MHz
Fractional Output Divider
-1
1
ppm
VDD_Yx_Yy = 2.5/3.3 V
0.2
0.34
0.55
V
VDD_Yx_Yy = 1.8 V
0.2
0.33
0.55
V
VDD_Yx_Yy = 2.5/3.3 V
0.4
0.67
1.0
V
VDD_Yx_Yy = 1.8 V
0.4
0.65
1.0
V
VDD_Yx_Yy = 2.5/3.3 V
1.0
2.1
V
VDD_Yx_Yy = 1.8 V
2 x|VOD|
V
100
167
250
Measured from VDIFF= –100 mV to
VDIFF= +100 mV, VDD_Yx_Yy = 1.8 V
120
192
295
Phase Noise Floor
fOUT = 122.88 MHz
ODC
Output Duty Cycle
Not in bypass mode
14
TYP
Measured from VDIFF= –100 mV to
VDIFF = +100mV, VDD_Yx_Yy = 2.5/3.3 V
PN-floor
(1)
MIN
ps
VDD_Yx_Yy = 1.8 V
–158.8
–153 dBc/Hz
VDD_Yx = 2.5/3.3 V
–157.6
–153 dBc/Hz
45%
55%
The User's GUI calculates exact frequency error. It is a fixed, static offset. If the desired output target frequency is with the exact reach
of A 1/220 multiple, the actual output frequency error is 0.
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8.19 Output Skew and Sync to Output Propagation Delay Characteristics
VDD_Yx_Yy = 1.71 to 1.89 V, 2.375 V to 2.625 V, 3.135V to 3.465 V, TA = –40°C to 85°C
PARAMETER
tPD-PS
ΔtPD-PS
TEST CONDITIONS
Propagation delay SYNCN↑ to output
f VCO = 2.5 GHz
toggling high
Part-to-Part Propagation delay
variation SYNCN↑ to output toggling
high (1)
MIN
TYP MAX
UNIT
PS_A = 4
9
10.5
11
1/fPS_A
PS_A = 5
9
10.2
11
1/fPS_A
PS_A = 6
9
10.0
11
1/fPS_A
Fixed supply voltage, temp, and device setting (1)
0
1 1/f PS_A
OUTPUT SKEW – ALL OUTPUTS USE IDENTICAL OUTPUT SIGNALING, INTEGER DIVIDERS ONLY; PS_A = PS_B = 6, OutDiv = 4
tSK,LVDS
Skew between Y[7:4] LVDS
Y[7:4] = LVDS
40
ps
tSK,LVDS
Skew between Y[3:0] LVDS
Y[3:0] = LVDS
40
ps
tSK,LVDS
Skew between Y[7:0] LVDS
Y[7:0] = LVDS
80
ps
tSK,CML
Skew between Y[3:0] CML
Y[3:0] = CML
40
ps
tSK,PECL
Skew between Y[3:0] PECL
Y[3:0] = LVPECL
40
ps
tSK,HCSL
Skew between Y[7:4] HCSL
Y[7:4] = HCSL
40
ps
tSK,SE
Skew between Y[7:4] CMOS
Y[7:4] = CMOS
50
ps
OUTPUT SKEW - MIXED SIGNAL OUTPUT CONFIGURATION, INTEGER DIVIDERS ONLY; PS_A = PS_B = 6, OutDiv = 4
tSK,CMOS-LVDS
Skew between Y[7:4] LVDS and
CMOS mixed
Y[4] = CMOS, Y[7:5] = LVDS
2.5
ns
tSK,CMOS-PECL
Skew between Y[7:0] CMOS and
LVPECL mixed
Y[7:4] = CMOS, Y[3:0] = LVPECL
2.5
ns
tSK,PECL-LVDS
Skew between Y[3:0] LVPECL and
LVDS mixed
Y[0] = LVPECL, Y[3:1] = LVDS
120
ps
tSK,PECL-CML
Skew between Y[3:0] LVPECL and
CML mixed
Y[0] = LVPECL, Y[3:1] = CML
40
ps
tSK,LVDS-PECL
Skew between Y[7:0] LVDS and
LVPECL mixed
Y[7:4] = LVDS, Y[3:0] = LVPECL
180
ps
tSK,LVDS-HCSL
Skew between Y[7:4] LVDS and
HCSL mixed
Y[4] = LVDS, Y[7:5] = HCSL
250
ps
200
ps
OUTPUT SKEW - USING FRACTIONAL OUTPUT DIVISION; PS_A = PS_B = 6, OutDiv = 3.125
tSK,DIFF, frac
(1)
Skew between Y[7:4] LVDS using all
fractional divider with the same
divider setting
Y[7:4] = LVDS
SYNC is toggled 10,000 times for each device. Test is repeated over process voltage and temperature (PVT).
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8.20 Device Individual Block Current Consumption
VDD_Yx_Yy, VDD_PRI, VDD_SEC, VDD_PLLx, DVDD, VDD_VCO = 1.8 V, 2.5 V, or 3.3 V, TA = –40°C to 85°C, Output
Types = LVPECL/CML/LVDS/LVCMOS/HCSL
BLOCK
CONDITION
Core
TYPICAL CURRENT CONSUMPTION (mA)
CDCM6208V1F Core, active mode, PS_A = PS_B = 4
75
CML output, AC coupled w/ 100 Ω diff load
24.25
LVPECL, AC coupled w/ 100 Ω diff load
40
LVCMOS output, transient, 'C L' load, 'f' MHz output
frequency, 'V' output swing
Output Buffer
1.8 + V x f OUT x (C L+ 12 x 10 -12) x 10 3
LVDS output, AC coupled w/ 100 Ω diff load
Output Divide Circuitry
19.7
HCSL output, 50 Ω load to GND on each output pin
31
Integer Divider Bypass (Divide = 1)
3
Integer Divide Enabled, Divide > 1
8
Fractional Divider Enabled
12
additional current when PS_A differs from PS_B
15
Total Device, CDCM6208V1F
Device Settings (V2)
1. PRI input enabled, set to LVDS mode
2. SEC input XTAL
3. Input bypass off, PRI only sent to PLL
4. Reference clock 30.72 MHz
5. PRI input divider set to 1
6. Reference input divider set to 1
7. Charge Pump Current = 2.5 mA
8. VCO Frequency = 3.072 GHz
9. PS_A = PS_B divider ration = 4
10. Feedback divider ratio = 25
11. Output divider ratio = 5
12. Fractional divider pre-divider = 2
13. Fractional divider core input frequency = 384 MHz
14. Fractional divider value = 3.84, 5.76, 3.072, 7.68
15. CML outputs selected for CH0-3 (153.6 MHz)
LVDS outputs selected for CH4-7 (100 MHz, 66.66 MHz,
125 MHz, 50 MHz)
Total Device, CDCM6208V1F
Power Down (PDN = '0')
(excl. I termination_resistors)
(1.8 V: 251 mA
2.5 V: 254 mA
3.3 V: 257 mA)
(incl. I termination_resistors)
(1.8 V: 310 mA
2.5 V: 313 mA
3.3 V: 316 mA)
0.35
Helpful Note: The CDCM6208V1F User GUI does an excellent job estimating the total device current
consumption based on the actual device configuration. Therefore, it is recommended to use the GUI to estimate
device power consumption.
The individual supply terminal current consumption for Pin mode P23 was measured to come out the following:
Customer EVM
Table 1. Individual Supplies Measured
16
PWR PIN 39 = GND
VPRI = 1.8 V
VOUT = 1.8 V
Y0-1
Y2-3
Y4
Y5
Y6
Y7
61 mA
40 mA
21 mA
29 mA
30 mA
31 mA
SEC
(VSEC = 1.8V)
SEC
(VSEC = 2.5V)
12 mA
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PRI
PLL1
PLL2
70 mA
VCO
DVDD
TOTAL
1.5 mA
295.5 mA
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8.21 Worst Case Current Consumption
VDD_Yx_Yy, VDD_PRI, VDD_SEC, VDD_PLLx, DVDD, VDD_VCO = 3.45 V, TA = T-40°C to 85°C, Output Types = maximum
swing, all blocks including duty cycle correction and fractional divider enabled and operating at maximum operation
BLOCK
Total Device, CDCM6208V1F
CONDITION
All conditions over PVT, AC coupled outputs with all outputs
terminated, device configuration:
Device Settings (V2)
1. PRI input enabled, set to LVDS mode
2. SEC input XTAL
3. Input bypass off, PRI only sent to PLL
4. Reference clock 30.72 MHz
5. PRI input divider set to 1
6. Reference input divider set to 1
7. Charge Pump Current = 2.5 mA
8. VCO Frequency = 3.072 GHz
9. PS_A = PS_B divider ration = 4
10. Feedback divider ratio = 25
11. Output divider ratio = 5
12. Fractional divider pre-divider = 2
13. Fractional divider core input frequency = 384 MHz
14. Fractional divider value = 3.84, 5.76, 3.072, 7.68
15. CML outputs selected for CH0-3 (153.6 MHz)
LVDS outputs selected for CH4-7 (100MHz, 66.66 MHz, 125
MHz, 50 MHz)
CURRENT CONSUMPTION
TYP / MAX
1.8 V: 310 mA / +21% (excl term)
3.3 V: 318 mA / +21% (excl term)
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8.22 I2C TIMING (1)
PARAMETER
STANDARD MODE
MIN
MAX
0
100
FAST MODE
MIN
MAX
0
400
UNIT
fSCL
SCL Clock Frequency
tsu(START)
START Setup Time (SCL high before SDA low)
4.7
0.6
μs
th(START)
START Hold Time (SCL low after SDA low)
4.0
0.6
μs
tw(SCLL)
SCL Low-pulse duration
4.7
1.3
μs
tw(SCLH)
SCL High-pulse duration
4.0
0.6
μs
(2)
SDA Hold Time (SDA valid after SCL low)
0
tsu(SDA)
SDA Setup Time
250
tr-in
SCL / SDA input rise time
1000
300
ns
tf-in
SCL / SDA input fall time
300
300
ns
tf-out
SDA Output fall time from VIH min to VIL max with a bus
capacitance from 10 pF to 400 pF
250
250
ns
tsu(STOP)
STOP Setup Time
4.0
tBUS
Bus free time between a STOP and START condition
4.7
tglitch_filter
Pulse width of spikes suppressed by the input glitch filter
75
(2)
0
μs
th(SDA)
(1)
3.45
kHz
0.9
100
ns
μs
0.6
μs
1.3
300
75
300
ns
2
For additional information, refer to the I C-Bus specification, Version 2.1 (January 2000); the CDCM6208V1F meets the switching
characteristics for standard mode and fast mode transfer.
The I2C master must internally provide a hold time of at least 300 ns for the SDA signal to bridge the undefined region of the falling edge
of SCL.
t4
t1
t5
SCL
t2
SDI
A31
t3
A30
D1
D0
'21¶7&$5(
t6
SDO
'21¶7&$5(
D15
D1
tri-state
D0
t7
SCS
t8
Figure 2. CDCM6208V1F SPI Port Timing
18
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8.23 SPI Timing Requirements
PARAMETER
fClock
MIN
NOM
Clock Frequency for the SCL
MAX
UNIT
20
MHz
t1
SPI_LE to SCL setup time
10
ns
t2
SDI to SCL setup time
10
ns
t3
SDO to SCL hold time
10
ns
t4
SCL high duration
25
ns
t5
SCL low duration
25
ns
t6
SCL to SCS Setup time
10
ns
t7
SCS Pulse Width
20
ns
t8
SDI to SCL Data Valid (First Valid Bit after SCS)
10
ns
STOP
ACK
START
tW(SCLL)
tW(SCLH)
tr(SM)
STOP
tf(SM)
~
~
VIH(SM)
SCL
VIL(SM)
~
~
th(START)
tSU(START)
tBUS
tr(SM)
tSU(SDATA)
th(SDATA)
tf(SM)
tSU(STOP)
~
~
~
~
VIH(SM)
SDA
~
~
VIL(SM)
Figure 3. I2C Timing Diagram
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8.24 Typical Characteristics
Using Divide by x.73 Example
fFRAC = 300 MHz
Figure 5. Fractional Divider Input Frequency Impact on Jitter
Figure 4. Fractional Divider Bit Selection Impact on Jitter
200 ps-pp
200
all zero, (0) typ
MSB, (1/2) typ
180 ps-pp
180
MSB-1, (1/4) typ
160 ps-pp
MSB-2, (1/8) typ
MSB-9, (1/1024) typ
MSB-3, (1/16) typ
140 ps-pp
MSB-4, (1/32) typ
Jitter
MSB-5, (1/54) typ
120 ps-pp
Jitter
MSB-9, (1/1024) max
160
MSB-6, (1/128) typ
100 ps-pp
MSB-7, (1/256) typ
MSB-9, (1/1024) typ
80 ps-pp
140
MSB-4, (1/32) max
120
MSB-13, (1/16384) max
MSB-13, (1/16384) typ
100
LSB, (1/1048576) max
80
LSB, (1/1048576) typ
MSB-13, (1/16384) typ
60 ps-pp
60
LSB, (1/1048576) typ
0x50A33D (÷x.315) typ
40 ps-pp
MSB, (1/2) max
MSB, (1/2) typ
40
0x828F5 (÷x.51) typ
20 ps-pp
0xBAE14 (÷x.73) typ
0 ps-pp
200 220 240 260 280 300 320
340 360 380
all zero, (0) max
20
0
200
400
250
300
350
400
Frequency (MHz)
Frequency (MHz)
Figure 7. Fractional Divider Bit Selection Impact on TJ
(Maximum Jitter Across Process, Voltage & Temperature)
Figure 6. Fractional Divider Bit Selection Impact on TJ
(Typical)
-50
-55
9.2 ps
-60
2.9 ps
-70
-75
0.92 ps
Jitter
PSRR (dBc)
-65
-80
0.29 ps
-85
-90
0.092 ps
-95
-100
100
1000
10K
100k
1M
10M
Frequency (Hz)
f OUT = 122 MHz
Figure 8. PSRR (in dBc and DJ [ps]) Over Frequency [Hz] and Output Signal Format
20
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8.24.1 Fractional Output Divider Jitter Performance
The fractional output divider jitter performance is a function of the fraction output divider input frequency as well
as actual fractional divide setting itself. To minimize the fractional output jitter, it is recommended to use the least
number of fractional bits and the highest input frequency possible into the divider. As observable in Figure 4, the
largest jitter contribution occurs when only one fractional divider bit is selected, and especially when the bits in
the middle range of the fractional divider are selected. Tested using a LeCroy 40 Gbps RealTime scope over a
time window of 200 ms. The RJ impact on TJ is estimated for a BERT 10(–12) – 1. This measurement result is
overly pessimistic, as it does not bandwidth limit the high-frequencies. In a real system, the SERDES TX will BW
limit the jitter through its PLL roll-off above the TX PLL bandwidth of typically bit rate divided by 10.
8.24.2 Power Supply Ripple Rejection (PSRR) versus Ripple Frequency
See Figure 8 for reference.
Many system designs become increasingly more sensitive to power supply noise rejection. In order to simplify
design and cost, the CDCM6208V1F has built in internal voltage regulation, improving the power supply noise
rejection over designs with no regulators. As a result, the following output rejection is achieved:
The DJ due to PSRR can be estimated using Equation 1:
(spur/20)
Deterministic Jitter (psp-p ) = 2 x 10
x 10-12
p x fCLK
(1)
Example: Therefore, if 100 mV noise with a frequency of 10 kHz were observed at the output supply, the
according output jitter for a 122.88 MHz output signal with LVDS signaling could be estimated with DJ = 0.7ps.
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9 Parameter Measurement Information
9.1 Characterization Test Setup
This section describes the characterization test setup of each block in the CDCM6208V1F.
High impedance probe
CDCM6208
LVCMOS
Oscilloscope
5pF
Figure 9. LVCMOS Output AC Configuration During Device Test (VOH, VOL, tSLEW)
High impedance probe
CDCM6208
LVCMOS
Oscilloscope
1mA
High impedance probe
VDD_Yx
1mA
CDCM6208
Oscilloscope
LVCMOS
Figure 10. LVCMOS Output DC Configuration During Device Test
CDCM6208
LVCMOS
Phase Noise/
Spectrum
Analyzer
50
Figure 11. LVCMOS Output AC Configuration During Device Phase Noise Test
22
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Characterization Test Setup (continued)
50 O
YP
CDCM6208
50
YN
50
Set to one of the following signaling
levels: LVPECL, CML, LVDS
Phase Noise/
Spectrum
Analyzer
50
Balun
Figure 12. LVDS, CML, and LVPECL Output AC Configuration During Device Test
High impedance differential probe
HCSL
CDCM6208
Oscilloscope
HCSL
50
50
Figure 13. HCSL Output DC Configuration During Device Test
HCSL
CDCM6208
Balun
HCSL
50
Phase Noise/
Spectrum
50
Analyzer
50
Figure 14. HCSL Output AC Configuration During Device Test
Offset = VDD_PRI/SEC/2
Signal
Generator
LVCMOS
CDCM6208
50
Figure 15. LVCMOS Input DC Configuration During Device Test
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Characterization Test Setup (continued)
CML
Signal
Generator
CDCM6208
CML
50
50
VDD_PRI/SEC
Figure 16. CML Input DC Configuration During Device Test
LVDS
Signal
Generator
CDCM6208
100
LVDS
Figure 17. LVDS Input DC Configuration During Device Test
LVPECL
Signal
Generator
CDCM6208
LVPECL
50
50
VDD_PRI/SEC - 2
Figure 18. LVPECL Input DC Configuration During Device Test
VDD_PRI/SEC
100
Signal
Generator
100
CDCM6208
Differential
100
100
Figure 19. Differential Input AC Configuration During Device Test
24
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Characterization Test Setup (continued)
Crystal
CDCM6208
Figure 20. Crystal Reference Input Configuration During Device Test
Sine wave
Modulator
Signal
Generator
Reference
Input
CDCM6208
Device Output
50
Balun
Phase Noise/
Spectrum
50
Analyzer
Balun
Phase Noise/
Spectrum
50
Analyzer
50
Figure 21. Jitter transfer Test Setup
Sine wave
Modulator
Power Supply
Signal
Generator
Reference
Input
CDCM6208
Device Output
50
50
Figure 22. PSNR Test Setup
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Characterization Test Setup (continued)
Yx_P
VOD
Yx_N
80%
VOUT,DIFF,PP = 2 x VOD
0V
20%
tR
tF
Figure 23. Differential Output Voltage and Rise and Fall Time
80%
VOUT,SE
OUT_REFx/2
20%
tR
tF
Figure 24. Single Ended Output Voltage and Rise and Fall Time
26
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Characterization Test Setup (continued)
VCXO_P
Single Ended
VCXO_P
Differential
VCXO_N
tPD,DIFF
Yx_P
Differential, Integer Divide
Yx_N
tSK,DIFF,INT
Yx_P
Differential, Integer Divide
Yx_N
tSK,DIFF,FRAC
Yx_P
Differential, Fractional Divide
Yx_N
tSK,SE-DIFF,INT
Single Ended, Integer Divide
Yx_P/N
tPD, SE
tSK,SE,INT
Yx_P/N
Single Ended, Integer Divide
tSK,SE,FRAC
Single Ended, Fractional Divide
Yx_P/N
Figure 25. Differential and Single Ended Output Skew and Propagation Delay
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10 Detailed Description
10.1 Overview
Supply Voltage: The CDCM6208V1F supply is internally regulated. Therefore each core and I/O supply can be
mixed and matched in any order according to the application needs. The device jitter performance is independent
of supply voltage.
Frequency Range: The PLL includes dual reference inputs with input multiplexer, charge pump, loop filter, and
VCO that operates from 2.39 GHz to 2.55 GHz.
Reference inputs: The primary and secondary reference inputs support differential and single ended signals from
8 kHz to 250 MHz. The secondary reference input also supports crystals from 10 MHz to 50 MHz. There is a 4bit reference divider available on the primary reference input. The input mux between the two references
supports simply switching or can be configured as Smart MUX and supports glitchless input switching.
Divider and Prescaler: In addition to the 4-bit input divider of the primary reference a 14-b input divider at the
output of input MUX and a cascaded 8-b and 10-b continuous feedback dividers are available. Two independent
prescaler dividers offer divide by /4, /5 and /6 options of the VCO frequency of which any combination can then
be chosen for a bank of 4 outputs (2 with fractional dividers and 2 that share an integer divider) through an
output MUX. A total of 2 output MUXes are available.
Phase Frequency Detector and Charge Pump: The PFD input frequency can range from 8 kHz to 100 MHz. The
charge pump gain is programmable and the loop filter consists of internal + partially external passive
components and supports bandwidths from a few Hz up to 400kHz.
10.2 Functional Block Diagram
REF_SEL
ELF
Fractional Div
Y4
20-b
LVDS/
LVCMOS/
HCSL
Y5
Fractional Div
20-b
R
4-b
Differential
LVCMOS/ SEC_REF
XTAL
Smat MUX
Y0
Differential/
LVCMOS PRI_REF
PreScaler PS_A
÷4, ÷5, ÷6
M
14-b
N
Y1
Y2
VCO:
(2.39-2.55) GHz
Input
PreScaler PS_B
÷4, ÷5, ÷6
PLL
8-b
Fractional Div
20-b
20-b
Power
Conditioning
CDCM6208
LVPECL/
CML/
LVDS
Integer Div
Fractional Div
Control
Host
Interface
8-b
Φ
8-b,10-b
Status/
Monitoring
Integer Div
Y3
Y6
Y7
LVDS/
LVCMOS/
HCSL
Output
Figure 26. High-Level Block Diagram of CDCM6208V1F
28
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10.3 Feature Description
Phase Noise: The Phase Noise performance of the device can be summarized to:
Table 2. Synthesizer Mode (Loop filter BW >250 kHz)
RANDOM JITTER (ALL OUTPUTS)
TYPICAL
(1)
(2)
TOTAL JITTER
MAXIMUM
MAXIMUM
10k-20MHz
12k-20MHz
10k-100MHz
0.27 ps-rms (Integer division)
0.7ps-rms (fractional div)
0.3 ps-rms (int div) (1)
0.625 ps-rms (int div)
Integer divider
DJ-unbound
RJ 10k-20MHz
20 ps-pp
Fractional divider
DJ 10k-40MHz
RJ 10k-20MHz
50-220 ps-pp,
see Figure 4
(2)
Integrated Phase Noise (12kHz - 20 MHz) for 156.25 MHz output clock measured at room temperature using a 25 MHz Low Noise
reference source
TJ = 20 pspp applies for LVPECL, CML, and LVDS signaling. TJ lab characterization measured 8 pspp, (typical) and 12 pspp (max) over
PVT.
Table 3. Jitter Cleaner Mode (Loop filter BW < 1 kHz)
RANDOM JITTER (ALL OUTPUTS)
TYPICAL
TOTAL JITTER
MAXIMUM
MAXIMUM
10k-20MHz
10k-20MHz
10k-100MHz
Integer divider
DJ unbound
RJ 10k-20MHz
1.6 ps-rms (Integer division)
2.3 ps-rms (fractional div) 10k-20MHz
2.1 ps-rms (int div)
2.14 ps-rms (int div)
40 ps-pp
Fractional divider
DJ 10k-40MHz
RJ 10k-20MHz
70-240 ps-pp,
see Figure 4
Spurious Performance: The spurious performance is as follows:
• Less than -80 dBc spurious from PFD/reference clocks at 122.88 MHz output frequency in the Nyquist range.
• Less than -68 dBc spurious from output channel-to-channel coupling on the victim output at differential
signaling level operated at 122.88 MHz output frequency in the Nyquist range.
Device outputs:
The Device outputs offer multiple signaling formats: high-swing CML (LVPECL like), normal-swing CML (CML),
low-swing CML (LVDS like), HCSL, and LVCMOS signaling.
Table 4. Device Outputs
Outputs
LVPECL
CML
LVDS
Y[3:0]
X
X
X
Y[7:4]
X
HCSL
X
LVCMOS
X
OUTPUT DIVIDER
FREQUENCY
RANGE
Integer only
1.55 - 800 MHz
Integer
1.55 - 800 MHz
Fractional
1.00 - 400 MHz
Outputs [Y0:Y3] are driven by 8-b continuous integer dividers per pair. Outputs [Y4:Y7] are each driven by 20-b
fractional dividers that can achieve any frequency with better than 1ppm frequency accuracy. The output skew is
typically less than 40 ps for differential outputs. The LVCMOS outputs support adjustable slew rate control to
control EMI. Pairs of 2 outputs can be operated at 1.8 V, 2.5 V or 3.3 V power supply voltage.
Device Configuration:32 distinct pin modes are available that cover many common use cases without the need
for any serial programming of the device. For maximum flexibility the device also supports SPI and I2C
programming. I2C offers 4 distinct addresses to support up to 4 devices on the same programming lines.
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10G
PHY
DPLL
PCIe
1G
PHY
DDR
CDCM6208
Synthesizer
Mode
4x10G Ethernet ASIC
10G
PHY
10G
PHY
10G
PHY
10G
PHY
10GbE
Figure 27. Typical Use Case: CDCM6208V1F Example in Wireless Infrastructure Baseband Application
10.4 Device Functional Modes
10.4.1 Control Pins Definition
In the absence of a host interface, the CDCM6208V1F can be powered up in one of 32 pre-configured settings
when the pins are SI_MODE[1:0] = 10. The CDCM6208V1F has 5 control pins identified to achieve commonly
used networking frequencies, and change output types. The Smart Input MUX for the PLL is set in most
configurations to manual mode in pin mode. Based on the control pins settings for the on-chip PLL, the device
generates the appropriate frequencies and appropriate output signaling types at start-up. In the case of the PLL
loop filter, "JC" denotes PLL bandwidths of ≤ 1 kHz and "Synth" denotes PLL bandwidths of ≥ 100 kHz.
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pin[4:0]
Use Case
fin(PRI_REF)
Type
fin(SEC_REF)
Type2
REF_SEL
f(PFD)
fout(Y0)
TYPE(Y0)
fout(Y1)
Type(Y1)
fout(Y2)
Type(Y2)
fout(Y3)
Type(Y3)
fout(Y4)
Type(Y4)
fout(Y5)
Type(Y5)
fout(Y6)
Type(Y6)
fout(Y7)
Type(Y7)
(2)
SI_MODE[1:0]
Table 5. Pre-Configured Settings of CDCM6208V1F Accessible by PIN[4:0] (1)
0
I/O
SPI
Default
25
Disable
25
Crystal
MANSEC
25
2500
125
PECL
125
PECL
125
PECL
125
PECL
25
HCSL
100
HCSL
100
Disable
100
Disable
1
I/O
I2C
Default
25
Disable
25
Crystal
MANSEC
25
2500
125
PECL
125
PECL
125
PECL
125
PECL
25
HCSL
100
HCSL
100
Disable
100
Disable
11
Reserv
ed
10
0x00
1-V1F
25
LVCM
OS
25
Crystal
MANSEC
25
2500
156.25
LVDS
156.25
LVDS
156.25
LVDS
156.25
LVDS
156.25
LVDS
156.25
LVDS
156.25
LVDS
156.25
LVDS
10
0x01
2-V1F
25
LVCM
OS
25
Crystal
MANSEC
25
2500
125
LVDS
125
LVDS
125
LVDS
125
LVDS
25
LVDS
25
LVDS
25
LVDS
25
LVDS
25
Crystal
MANSEC
25
2500
156.25
LVDS
156.25
LVDS
156.25
LVDS
156.25
LVDS
25
LVDS
25
LVDS
25
LVCM
OS-PN
25
LVCM
OS-PN
f(VCO)
10
0x02
3-V1F
25
LVCM
OS
10
0x03
4-V1F
25
LVCM
OS
25
Crystal
MANSEC
25
2500
125
LVDS
125
LVDS
125
LVDS
125
LVDS
156.25
LVDS
156.25
LVDS
25
LVDS
125
LVCM
OS-PN
10
0x04
5-V1F
25
LVCM
OS
25
Crystal
MANSEC
25
2500
156.25
LVDS
156.25
LVDS
156.25
LVDS
156.25
LVDS
25
LVDS
25
LVDS
125
LVCM
OS-PN
125
LVCM
OS-PN
10
0x05
6-V1F
25
LVCM
OS
25
Crystal
MANSEC
25
2500
100
PECL
100
PECL
156.25
PECL
156.25
PECL
25
LVDS
100
HCSL
156.25
LVDS
156.25
LVDS
10
0x06
7-V1F
25
LVCM
OS
25
Crystal
MANSEC
25
2500
125
LVDS
125
LVDS
125
LVDS
125
LVDS
125
LVCM
OS-PN
156.25
LVDS
156.25
LVDS
25
LVDS
10
0x07
8-V1F
25
LVCM
OS
25
Crystal
MANSEC
25
2500
156.25
PECL
156.25
PECL
25
PECL
25
PECL
125
LVCM
OS-PN
156.25
LVDS
100
HCSL
100
HCSL
10
0x08
9-V1F
25
LVCM
OS
25
Crystal
MANSEC
25
2500
156.25
PECL
156.25
PECL
100
PECL
100
PECL
156.25
LVDS
156.25
LVDS
100
HCSL
100
HCSL
10
0x09
10-V1F
25
LVCM
OS
25
Crystal
MANSEC
25
2500
100
PECL
100
PECL
156.25
CML
156.25
CML
25
LVDS
100
HCSL
156.25
LVDS
156.25
LVDS
10
0x0A
11-V1F
25
LVCM
OS
25
Crystal
MANSEC
25
2500
100
PECL
100
PECL
100
PECL
100
PECL
25
LVCM
OS-PN
125
LVCM
OS-PN
50
LVCM
OS-PN
12.000
000183
1055
LVCM
OS-PN
10
0x0B
12-V1F
25
LVCM
OS
25
Crystal
MANSEC
25
2400
25
PECL
25
PECL
100
CML
100
CML
25
LVCM
OS-PN
25
LVCM
OS-PN
100
HCSL
12
LVCM
OS-PN
10
0x0C
13-V1F
25
LVCM
OS
25
Crystal
MANSEC
25
2500
156.25
PECL
156.25
PECL
125
PECL
125
PECL
25
LVCM
OS-PN
25
LVCM
OS-PN
25
LVDS
100
HCSL
10
0x0D
14-V1F
25
LVCM
OS
25
Crystal
MANSEC
25
2500
25
PECL
25
PECL
156.25
PECL
156.25
PECL
100
HCSL
100
HCSL
156.25
LVDS
66.666
666666
6667
LVCM
OS-PN
10
0x0E
15-V1F
25
LVCM
OS
25
Crystal
MANSEC
25
2500
125
LVDS
125
LVDS
125
LVDS
125
LVDS
25
LVDS
25
LVDS
25
LVDS
33.333
333333
3333
LVCM
OS-PN
(1)
(2)
The functionality of the status 0 and status 1 pins in SPI and I2C mode is programmable.
The REF_SEL input pin selects the primary or secondary input in MANUAL mode. That is: If the system only uses a XTAL on the secondary input, REF_SEL should be tied to VDD. The
primary and secondary input stage power supply must be always connected.
For all pin modes, STATUS0 outputs the PLL_LOCK signal and STATUS1 the LOSS OF REFERENCE.
General Note: in all pin mode, all voltage supplies must either be 1.8 V or 2.5/3.3 V and the PWR pin number 44 must be set to 0 or 1 accordingly. In SPI and I2C mode, the supply
voltages can be "mixed and matched" as long as the corresponding register bits reflect the supply voltage setting for each desired 1.8 V or 2.5/3.3 V supply. Exception: inputs configured
for LVDS signaling (Type = LVDS) are supply agnostic, and therefore can be powered from 2.5 V/3.3 V or 1.8 V regardless of the supply select setting of pin number 44.
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SI_MODE[1:0]
pin[4:0]
Use Case
fin(PRI_REF)
Type
fin(SEC_REF)
Type2
REF_SEL
f(PFD)
fout(Y0)
TYPE(Y0)
fout(Y1)
Type(Y1)
fout(Y2)
Type(Y2)
fout(Y3)
Type(Y3)
fout(Y4)
Type(Y4)
fout(Y5)
Type(Y5)
fout(Y6)
Type(Y6)
fout(Y7)
Type(Y7)
Table 5. Pre-Configured Settings of CDCM6208V1F Accessible by PIN[4:0](1) (2) (continued)
10
0x0F
16-V1F
25
LVCM
OS
25
Crystal
MANSEC
25
2500
156.25
LVDS
156.25
LVDS
100
PECL
100
PECL
25
LVCM
OS-PN
25
LVDS
100
HCSL
100
HCSL
10
0x10
17-V1F
25
LVCM
OS
25
Crystal
MANSEC
25
2500
25
LVDS
25
LVDS
25
LVDS
25
LVDS
25
LVDS
156.25
LVDS
33.333
333333
3333
LVCM
OS-PN
33.333
333333
3333
LVCM
OS-PN
10
0x11
18-V1F
25
LVCM
OS
25
Crystal
MANSEC
25
2500
25
LVDS
25
LVDS
25
LVDS
25
PECL
25
LVDS
156.25
LVDS
156.25
LVDS
156.25
LVDS
10
0x12
19-V1F
25
LVCM
OS
25
Crystal
MANSEC
25
2500
100
CML
100
CML
100
CML
100
CML
100
HCSL
100
HCSL
100
HCSL
100
HCSL
25
Crystal
MANSEC
25
2500
156.25
PECL
156.25
PECL
125
PECL
125
PECL
156.25
HCSL
156.25
HCSL
100
HCSL
100
HCSL
f(VCO)
10
0x13
20-V1F
25
LVCM
OS
10
0x14
21-V1F
25
LVCM
OS
25
Crystal
MANSEC
25
2400
100
LVDS
100
LVDS
100
LVDS
100
LVDS
24
LVCM
OS-PN
100
LVDS
100
LVDS
133.33
333333
3333
LVCM
OS-PN
10
0x15
22-V1F
25
LVCM
OS
25
Crystal
MANSEC
25
2500
125
LVDS
125
LVDS
125
LVDS
125
LVDS
125
LVCM
OS-PN
156.25
LVDS
156.25
LVDS
100
LVCM
OS-PN
10
0x16
23-V1F
25
LVCM
OS
25
Crystal
MANSEC
25
2500
125
LVDS
125
LVDS
125
LVDS
125
LVDS
125
LVCM
OS-PN
156.25
LVDS
100
LVDS
100
LVCM
OS-PN
10
0x17
24-V1F
25
LVCM
OS
25
Crystal
MANSEC
25
2500
125
LVDS
125
LVDS
125
LVDS
125
LVDS
125
LVCM
OS-PN
125
LVDS
156.25
LVDS
100
LVCM
OS-PN
10
0x18
25-V1F
25
LVCM
OS
25
Crystal
MANSEC
25
2500
125
LVDS
125
LVDS
125
LVDS
125
LVDS
125
LVCM
OS-PN
125
LVDS
100
LVDS
100
LVCM
OS-PN
10
0x19
26-V1F
25
LVCM
OS
25
Crystal
MANSEC
25
2500
100
LVDS
100
LVDS
156.25
LVDS
156.25
LVDS
100
LVDS
100
HCSL
100
HCSL
100
HCSL
10
0x1A
27-V1F
25
LVCM
OS
25
Crystal
MANSEC
25
2500
100
LVDS
100
LVDS
156.25
LVDS
156.25
LVDS
100
LVDS
100
HCSL
156.25
LVDS
156.25
LVDS
10
0x1B
28-V1F
25
LVCM
OS
25
Crystal
MANSEC
25
2500
100
LVDS
100
LVDS
156.25
LVDS
156.25
LVDS
100
LVDS
100
HCSL
100
HCSL
156.25
LVDS
10
0x1C
29-V1F
25
LVCM
OS
25
Crystal
MANSEC
25
2500
100
LVDS
100
LVDS
100
LVDS
100
LVDS
23.999
999267
5781
LVCM
OS-PN
125
LVCM
OS-PN
125
LVDS
83.333
333333
3333
LVCM
OS-PN
10
0x1D
30-V1F
25
LVCM
OS
25
Crystal
MANSEC
25
2500
100
LVDS
100
LVDS
100
LVDS
100
LVDS
23.999
999267
5781
LVCM
OS-PN
125
LVCM
OS-PN
125
LVDS
100
LVCM
OS-PN
10
0x1E
31-V1F
25
LVCM
OS
25
Crystal
MANSEC
25
2500
100
LVDS
100
LVDS
100
LVDS
100
LVDS
23.999
999267
5781
LVCM
OS-PN
125
LVCM
OS-PN
125
LVDS
66.666
666666
6667
LVCM
OS-PN
10
0x1F
32-V1F
25
LVDS
25
Crystal
MANSEC
25
2500
156.25
LVDS
156.25
LVDS
100
LVDS
100
LVDS
125
LVDS
25
LVCM
OS-PN
100
LVDS
100
LVDS
32
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10.4.2 Loop Filter Recommendations for Pin Modes
The following two tables provide the internal charge pump and R3/C3 settings for pin modes. The designer can
either design their own optimized loop filter, or use the suggested loop filter in the Table 6.
Table 6. CDCM6208V1F Loop Filter Recommendation for Pin Mode
SI_MODE[1:0]
pin [4:0]
REF_SEL
Internal LPF
Components
Use Case
f(PFD)
(MHz)
0
I/O
SPI
Default
25
Disable
25
Crystal
MANSEC
25
2.5m
100pF/500Ohm/22nF
100
Ohm
242.5
1
I/O
I2C
Default
25
Disable
25
Crystal
MANSEC
25
2.5m
100pF/500Ohm/22nF
100
Ohm
242.5
11
Reserv
ed
10
0x00
1-V1F
25
LVCMOS
25
Crystal
MANSEC
25
2.5m
100pF/500Ohm/22nF
100
Ohm
242.5
10
0x01
2-V1F
25
LVCMOS
25
Crystal
MANSEC
25
2.5m
100pF/500Ohm/22nF
100
Ohm
242.5
10
0x02
3-V1F
25
LVCMOS
25
Crystal
MANSEC
25
2.5m
100pF/500Ohm/22nF
100
Ohm
242.5
10
0x03
4-V1F
25
LVCMOS
25
Crystal
MANSEC
25
2.5m
100pF/500Ohm/22nF
100
Ohm
242.5
10
0x04
5-V1F
25
LVCMOS
25
Crystal
MANSEC
25
2.5m
100pF/500Ohm/22nF
100
Ohm
242.5
10
0x05
6-V1F
25
LVCMOS
25
Crystal
MANSEC
25
2.5m
100pF/500Ohm/22nF
100
Ohm
242.5
10
0x06
7-V1F
25
LVCMOS
25
Crystal
MANSEC
25
2.5m
100pF/500Ohm/22nF
100
Ohm
242.5
10
0x07
8-V1F
25
LVCMOS
25
Crystal
MANSEC
25
2.5m
100pF/500Ohm/22nF
100
Ohm
242.5
10
0x08
9-V1F
25
LVCMOS
25
Crystal
MANSEC
25
2.5m
100pF/500Ohm/22nF
100
Ohm
337.5
10
0x09
10-V1F
25
LVCMOS
25
Crystal
MANSEC
25
2.5m
100pF/500Ohm/22nF
100
Ohm
242.5
10
0x0A
11-V1F
25
LVCMOS
25
Crystal
MANSEC
25
2.5m
100pF/500Ohm/22nF
100
Ohm
242.5
10
0x0B
12-V1F
25
LVCMOS
25
Crystal
MANSEC
25
2.5m
100pF/500Ohm/22nF
100
Ohm
242.5
10
0x0C
13-V1F
25
LVCMOS
25
Crystal
MANSEC
25
2.5m
100pF/500Ohm/22nF
100
Ohm
242.5
10
0x0D
14-V1F
25
LVCMOS
25
Crystal
MANSEC
25
2.5m
100pF/500Ohm/22nF
100
Ohm
242.5
10
0x0E
15-V1F
25
LVCMOS
25
Crystal
MANSEC
25
2.5m
100pF/500Ohm/22nF
100
Ohm
242.5
10
0x0F
16-V1F
25
LVCMOS
25
Crystal
MANSEC
25
2.5m
100pF/500Ohm/22nF
100
Ohm
242.5
10
0x10
17-V1F
25
LVCMOS
25
Crystal
MANSEC
25
2.5m
100pF/500Ohm/22nF
100
Ohm
242.5
10
0x11
18-V1F
25
LVCMOS
25
Crystal
MANSEC
25
2.5m
100pF/500Ohm/22nF
100
Ohm
242.5
10
0x12
19-V1F
25
LVCMOS
25
Crystal
MANSEC
25
2.5m
100pF/500Ohm/22nF
100
Ohm
242.5
10
0x13
20-V1F
25
LVCMOS
25
Crystal
MANSEC
25
2.5m
100pF/500Ohm/22nF
100
Ohm
242.5
10
0x14
21-V1F
25
LVCMOS
25
Crystal
MANSEC
25
2.5m
100pF/500Ohm/22nF
100
Ohm
242.5
10
0x15
22-V1F
25
LVCMOS
25
Crystal
MANSEC
25
2.5m
100pF/500Ohm/22nF
100
Ohm
242.5
10
0x16
23-V1F
25
LVCMOS
25
Crystal
MANSEC
25
2.5m
100pF/500Ohm/22nF
100
Ohm
242.5
PRI_REF
Freq
(MHz)
SEC_REF
Type
Freq
(MHz)
Type
ICP
(mA)
Recommended
Loop Filter
C1/R2/C2
R3
(Ohm)
C3
(pF)
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Table 6. CDCM6208V1F Loop Filter Recommendation for Pin Mode (continued)
SI_MODE[1:0]
pin [4:0]
REF_SEL
Internal LPF
Components
Use Case
f(PFD)
(MHz)
10
0x17
24-V1F
25
LVCMOS
25
Crystal
MANSEC
25
2.5m
100pF/500Ohm/22nF
100
Ohm
242.5
10
0x18
25-V1F
25
LVCMOS
25
Crystal
MANSEC
25
2.5m
100pF/500Ohm/22nF
100
Ohm
242.5
10
0x19
26-V1F
25
LVCMOS
25
Crystal
MANSEC
25
2.5m
100pF/500Ohm/22nF
100
Ohm
242.5
10
0x1A
27-V1F
25
LVCMOS
25
Crystal
MANSEC
25
2.5m
100pF/500Ohm/22nF
100
Ohm
242.5
10
0x1B
28-V1F
25
LVCMOS
25
Crystal
MANSEC
25
2.5m
100pF/500Ohm/22nF
100
Ohm
242.5
10
0x1C
29-V1F
25
LVCMOS
25
Crystal
MANSEC
25
2.5m
100pF/500Ohm/22nF
100
Ohm
242.5
10
0x1D
30-V1F
25
LVCMOS
25
Crystal
MANSEC
25
2.5m
100pF/500Ohm/22nF
100
Ohm
242.5
10
0x1E
31-V1F
25
LVCMOS
25
Crystal
MANSEC
25
2.5m
100pF/500Ohm/22nF
100
Ohm
242.5
10
0x1F
32-V1F
25
LVDS
25
Crystal
MANSEC
25
2.5m
100pF/500Ohm/22nF
100
Ohm
242.5
PRI_REF
Freq
(MHz)
SEC_REF
Type
Freq
(MHz)
Type
ICP
(mA)
Recommended
Loop Filter
C1/R2/C2
R3
(Ohm)
C3
(pF)
10.4.3 Status Pins Definition
The device vitals such as input signal quality, smart mux input selection, and PLL lock can be monitored by
reading device registers or at the status pins STATUS1, and STATUS0. Register 3[12:7] allows for customization
of which vitals are mapped to these two pins. Table 7 lists the three events that can be mapped to each status
pin and which can also be read in the register space.
Table 7. CDCM6208V1F Status Pin Definition List
STATUS
SIGNAL NAME
SIGNAL TYPE
SIGNAL NAME
SEL_REF
LVCMOS
STATUS0, 1
Reg 3.12
Reg 3.9
Indicates Reference Selected for PLL:
0 → Primary input selected to drive PLL
1 → Secondary input selected to drive PLL
LOS_REF
LVCMOS
STATUS0, 1
Reg 3.11
Reg 3.8
Loss of selected reference input observed at active input:
0 → Reference input present
1 → Loss of reference input
Important Note 1: For LOS_REF to operate properly, the secondary
input SEC_IN must be enabled. Set register Q4.5=1. If register
Q4.5 is set to zero, LOS_REF will output a static high signal
regardless of the actual input signal status on PRI_IN.
PLL_UNLOCK
LVCMOS
STATUS0, 1
Reg 3.10
Reg 3.7
Indicates unlock status for PLL (digital):
PLL locked → Q21.02 = 0 and VSTATUS0/1= VIH
PLL unlocked → Q21.2 = 1 and VSTATUS0/1= VILSee note (1)
Note 2: I f the smartmux is enabled and both reference clocks stall,
the STATUSx output signal will 98% of the time indicate the LOS
condition with a static high signal. However, in 2% of the cases, the
LOS detection engine erroneously stalls at a state where the
STATUSx output PLL lock indicator will signalize high for 511 out of
every 512 PFD clock cycles.
(1)
34
REGISTER BIT
NO.
DESCRIPTION
The reverse logic between the register Q21.2 and the external output signal on STATUS0 or STATUS1.
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NOTE
It is recommended to assert only one out of the three register bits for each of the status
pins. For example, to monitor the PLL lock status on STATUS0 and the selected reference
clock sources on STATUS1 output, the device register settings would be Q3.12 = Q3.7 =
1 and Q3.11 = Q3.10 = Q3.9 = Q3.8 = 0. If a status pin is unused, it is recommended to
set the according 3 register bits to zero (e.g. Q3[12:9] = 0 for STATUS0 = 0). If more than
one bit is enabled for each STATUS signal, the function becomes OR'ed. For example, if
Q3.11 = Q3.10 = 1 and Q3.12 = 0, the STATUS0 output would be high either if the device
goes out of lock or the selected reference clock signal is lost.
10.4.4 PLL Lock Detect
The PLL lock detection circuit is a digital detection circuit which detects any frequency error, even a single cycle
slip. The PLL unlock is signalized when a certain number of cycle slips have been exceeded, at which point the
counter is reset. A frequency error of 2% will cause PLL unlock to stay low. A 0.5% frequency error shows up as
toggling the PLL lock output with roughly 50% duty cycle at roughly 1/1000 th of the PFD update frequency to the
device. A frequency error of 1ppm would show up as rare toggling low for a duration of approximately 1000 PFD
update clock cycles. If the system plans using PLL lock to toggle a system reset, then consider adding an RC
filter on the PLL LOCK output (Status 1 or Status 0) to avoid rare cycle slips from triggering an entire system
reset.
10.4.5 Interface and Control
The host (DSP, Microcontroller, FPGA, etc) configures and monitors the CDCM6208V1F via the SPI or I2C port.
The host reads and writes to a collection of control/status bits called the register file. Typically, a hardware block
is controlled and monitored via a specific grouping of bits located within the register file. The host controls and
monitors certain device-wide critical parameters directly, via control/status pins. In the absence of a host, the
CDCM6208V1F can be configured to operate in pin mode where the control pins [PIN0-PIN4] can be set
appropriately to generate the necessary clock outputs out of the device.
SPI/
I2C
Port
Comm
Select
STATUS0
STATUS1/PIN0
Reg31
15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
Reg30
15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
Reg 23
15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
Reg 22
15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
PDN
RESETN/PWR
Device
Control
And
Status
SCL/PIN4
SDI/SDA/PIN1
SDO/AD0/PIN2
SCS/AD1/PIN3
SI_MODE0
SI_MODE1
SPI: SI_MODE[1:0]=00;
I2C: SI_MODE[1:0]=01;
Reg 21
15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
Reg 20
15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
Reg3
15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
Reg2
15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
Reg1
15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
Reg 0
15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
User Space
Control/
Status
Pins
TI only
space
REGISTER SPACE
Device
Hardware
Pin Mode: SI_MODE[1:0]=10
Figure 28. CDCM6208V1F Interface and Control Block
Within this register space, there are certain bits that have read/write access. Other bits are read-only (an attempt
to write to a read only bit will not change the state of the bit).
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10.4.5.1 Register File Reference Convention
Figure 29 shows the method this document employs to refer to an individual register bit or a grouping of register
bits. If a drawing or text references an individual bit, the format is to specify the register number first and the bit
number second. The CDCM6208V1F contains 21 registers that are 16 bits wide. The register addresses and the
bit positions both begin with the number zero (0). A period separates the register address and bit address. The
first bit in the register file is address 'R0.0' meaning that it is located in Register 0 and is bit position 0. The last
bit in the register file is address R31.15 referring to the 16thbit of register address 31 (the 32ndregister in the
device
Reg05
Register Number (s)
5
4
Bit Number(s)
3
2
R05 .2
Figure 29. CDCM6208V1F Register Reference Format
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10.4.5.2 SPI - Serial Peripheral Interface
To enable the SPI port, tie the communication select pins SI_MODE[1:0] to ground. SPI is a master/slave
protocol in which the host system is always the master; therefore, the host always initiates communication
to/from the device. The SPI interface consists of four signal pins. The device SPI address is 0000.
Table 8. Serial Port Signals in SPI Mode
PIN
NAME
NUMBER
I/O
DESCRIPTION
SDI/SDA/PIN1
2
Input
SDO/AD0/PIN2
3
Output
SDI: SPI Serial Data Input
SCS/AD1/PIN3
4
Input
SCS: SPI Latch Enable
SCL/PIN4
5
Input
SCL: SPI/I2C Clock
SDO: SPI Serial Data
The host must present data to the device MSB first. A message includes a transfer direction bit, an address field,
and a data field as depicted in Figure 30
3
4
5
6
7
0
0
0
0
A
10
A
9
R/W
First Out
MSB
1 2
Examples:
Fixed (4 bits)
LSB
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Order of Transmission
A A A A A A A A A D D D D D D D D D D D D D D D D
Bit Definition
8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Register Address (11 bits)
Data Payload (16 bits)
Message Field Definition
8
9
Read Register 4:
1|000 0|000 0000 0100| xxxx xxxx xxxx xxxx
Write 0xF0F1 to Register 5:
0|000 0|000 0000 0101| 1111 0000 1111 0001
Figure 30. CDCM6208V1F SPI Message Format
10.4.5.2.1 Configuring the PLL
The CDCM6208V1F allows configuring the PLL to accommodate various input and output frequencies either
through an I2C or SPI programming interface or in the absence of programming, the PLL can be configured
through control pins. The PLL can be configured by setting the Smart Input MUX, Reference Divider, PLL Loop
Filter, Feedback Divider, Prescaler Divider, and Output Dividers.
For the PLL to operate in closed loop mode, the following condition in Equation 2 has to be met when using
primary input for the reference clock, and the condition in Equation 3 has to be met when using secondary input
for the reference clock.
f
f
PRI_REF =
VCO
(M × R)
(N × PS_A)
(2)
f
f
SEC_REF =
VCO
M
(N × PS_A)
(3)
In Equation 2 and Equation 3, ƒPRI_REF is the reference input frequency on the primary input and ƒSEC_REF is the
reference input frequency on the secondary input, R is the reference divider, M is the input divider, N is the
feedback divider, and PS_A the prescaler divider A.
The output frequency, ƒOUT, is a function of ƒVCO, the prescaler A, and the output divider (O), and is given by
Equation 4. (Use PS_B in for outputs 2, 3, 6, and 7).
f
OSC
=
f
OUT (O × PS_A)
(4)
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When the output frequency plan calls for the use of some output dividers as fractional values, the following steps
are needed to calculate the closest achievable frequencies for those using fractional output dividers and the
frequency errors (difference between the desired frequency and the closest achievable frequency).
• Based on system needs, decide the frequencies that need to have best possible jitter performance.
• Once decided, these frequencies need to be placed on integer output dividers.
• Then a frequency plan for these frequencies with strict jitter requirements can be worked out using the
common divisor algorithm.
• Once the integer divider plans are worked out, the PLL settings (including VCO frequency, feedback divider,
input divider and prescaler divider) can be worked out to map the input frequency to the frequency out of the
prescaler divider.
• Then calculate the fractional divider values (whose values must be greater than 2) that are needed to support
the output frequencies that are not part of the common frequency plan from the common divisor algorithm
already worked out.
• For each fractional divider value, try to represent the fractional portion in a 20 bit binary scheme, where the
first fractional bit is represented as 0.5, the second fractional bit is represented as 0.25, third fractional bit is
represented as 0.125 and so on. Continue this process until the entire 20 bit fractional binary word is
exhausted.
• Once exhausted, the fraction can be calculated as a cumulative sum of the fractional bit x fractional value of
the fractional bit. Once this is done, the closest achievable output frequency can be calculated with the
mathematical function of the frequency out of the prescaler divider divided by the achievable fractional
divider.
• The frequency error can then be calculated as the difference between the desired frequency and the closest
achievable frequency.
10.5 Programming
10.5.1 Writing to the CDCM6208V1F
To initiate a SPI data transfer, the host asserts the SCS (serial chip select) pin low. The first rising edge of the
clock signal (SCL) transfers the bit presented on the SDI pin of the CDCM6208V1F. This bit signals if a read
(first bit high) or a write (first bit low) will transpire. The SPI port shifts data to the CDCM6208V1F with each
rising edge of SCL. Following the W/R bit are 4 fixed bits followed by 11 bits that specify the address of the
target register in the register file. The 16 bits that follow are the data payload. If the host sends an incomplete
message, (i.e. the host de-asserts the SCS pin high prior to a complete message transmission), then the
CDCM6208V1F aborts the transfer, and device makes no changes to the register file or the hardware. Figure 32
shows the format of a write transaction on the CDCM6208V1F SPI port. The host signals the CDCM6208V1F of
the completed transfer and disables the SPI port by de-asserting the SCS pin high.
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Programming (continued)
10.5.2 Reading from the CDCM6208V1F
As with the write operation, the host first initiates a SPI transfer by asserting the SCS pin low. The host signals a
read operation by shifting a logical high in the first bit position, signaling the CDCM6208V1F that the host is
imitating a read data transfer from the device. During the portion of the message in which the host specifies the
CDCM6208V1F register address, the host presents this information on the SDI pin of the device (for the first 15
clock cycles after the W/R bit). During the 16 clock cycles that follow, the CDCM6208V1F presents the data from
the register specified in the first half of the message on the SDO pin. The SDO output is 3-stated anytime SCS is
high, so that multiple SPI slave devices can be connected to the same serial bus. The host signals the
CDCM6208V1F that the transfer is complete by de-asserting the SCS pin high.
SCS
(#37)
0
&
0
SDO internal
enable signal
0
Data out
LVCMOS
SDO
(#34)
CDCM6208
Figure 31.
10.5.3 Block Write/Read Operation
The device supports a block write and block read operation. The host need only specify the lowest address of the
sequence of addresses that the host needs to access. The CDCM6208V1F will automatically increment the
internal register address pointer if the SCS pin remains low after the SPI port finishes the initial 32-bit
transmission sequence. Each transmission of 16 bits (a data payload width) results in the device automatically
incrementing the address pointer (provided the SCS pin remains active low for all sequences).
SCS
SCL
WRITE
SCI
A31 A30 A29 A28 A27 A26 A25 A24 A23 A22 A21 A20 A19 A18 A17 A16 D15 D14 D13 D12 D11 D10
SCI
A31 A30 A29 A28 A27 A26 A25 A24 A23 A22 A21 A20 A19 A18 A17 A16
D9
D8
D7
D6
D5
D4
D5
D4
D3
D2
D1
D0
D1
D0
'21¶7&$5(
READ
HI-Z
SCO
D15 D14 D13 D12 D11 D10
16-BIT COMMAND
D9
D8
D7
D6
D3
D2
16-BIT DATA
Figure 32. CDCM6208V1F SPI Port Message Sequencing
10.5.4 I2C Serial Interface
With SI_MODE1=0 and SI_MODE0=1 the CDCM6208V1F enters I 2C mode. The I2C port on the CDCM6208V1F
works as a slave device and supports both the 100 kHz standard mode and 400 kHz fast mode operations. Fast
mode imposes a glitch tolerance requirement on the control signals. Therefore, the input receivers ignore pulses
of less than 50 ns duration. The inputs of the device also incorporates a Schmitt trigger at the SDA and SCL
inputs to provide receiver input hysteresis for increased noise robustness.
NOTE
Communication through I2C is not possible while RESETN is held low.
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Programming (continued)
In an I2C bus system, the CDCM6208V1F acts as a slave device and is connected to the serial bus (data bus
SDA and clock bus SCL). The SDA port is bidirectional and uses an open drain driver to permit multiple devices
to be connected to the same serial bus. The CDCM6208V1F allows up to four unique CDCM6208V1F slave
devices to occupy the I2C bus in addition to any other I2C slave device with a different I2C address. These slave
devices are accessed via a 7-bit slave address transmitted as part of an I2C packet. Only the device with a
matching slave address responds to subsequent I2C commands. The device slave address is 10101xx (the two
LSBs are determined by the AD1 and AD0 pins). The five MSBs are hard-wired, while the two LSBs are set
through pins on device powerup.
SDA
Data out
Data in
CDCM6208
Figure 33.
During the data transfer through the I2C port interface, one clock pulse is generated for each data bit transferred.
The data on the SDA line must be stable during the high period of the clock. The high or low state of the data
line can change only when the clock signal on the SCL line is low. The start data transfer condition is
characterized by a high-to-low transition on the SDA line while SCL is high. The stop data transfer condition is
characterized by a low-to-high transition on the SDA line while SCL is high. The start and stop conditions are
always initiated by the master. Every byte on the SDA line must be eight bits long. Each byte must be followed
by an acknowledge bit and bytes are sent MSB first.
The acknowledge bit (A) or non-acknowledge bit (A) is the 9thbit attached to any 8-bit data byte and is always
generated by the receiver to inform the transmitter that the byte has been received (when A = 0) or not (when A
= 1). A = 0 is done by pulling the SDA line low during the 9thclock pulse and A = 1 is done by leaving the SDA
line high during the 9thclock pulse.
The I2C master initiates the data transfer by asserting a start condition which initiates a response from all slave
devices connected to the serial bus. Based on the 8-bit address byte sent by the master over the SDA line
(consisting of the 7-bit slave address (MSB first) and an R/W bit), the device whose address corresponds to the
transmitted address responds by sending an acknowledge bit. All other devices on the bus remain idle while the
selected device waits for data transfer with the master. The CDCM6208V1F slave address bytes are given in
below table.
After the data transfer has occurred, stop conditions are established. In write mode, the master asserts a stop
condition to end data transfer during the 10 thclock pulse following the acknowledge bit for the last data byte from
the slave. In read mode, the master receives the last data byte from the slave but does not pull SDA low during
the 9thclock pulse. This is known as a non-acknowledge bit. By receiving the non-acknowledge bit, the slave
knows the data transfer is finished and enters the idle mode. The master then takes the data line low during the
low period before the 10 thclock pulse, and high during the 10 thclock pulse to assert a stop condition.
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Programming (continued)
For "Register Write/Read" operations, the I2C master can individually access addressed registers, that are made
of two 8-bit data bytes.
Table 9. I2C Slave Address Byte
A6
A5
A4
A3
A2
AD1
AD0
R/W
1
0
1
0
1
0
0
1/0
1
0
1
0
1
0
1
1/0
1
0
1
0
1
1
0
1/0
1
0
1
0
1
1
1
1/0
Table 10. Generic Programming Sequence
S
Start Condition
Sr
Repeated Condition
R/W
1 = Read (Rd) from slave; 0 = Write (Wr) to slave
A
Acknowledge (ACK = 0 and NACK = 1)
P
Stop Condition
Master to Slave Transmission
Slave to Master Transmission
Figure 34. Register Write Programming Sequence
1
7
S
SLAVE
Address
1
Wr
1
8
A
Register
Address
1
8
A
Register
Address
1
8
A
Data
Byte
1
8
1
1
A
Data
Byte
A
P
Figure 35. Register Read Programming Sequence
1
7
S
SLAVE
Address
1
Wr
1
8
A
Register
Address
1
8
A
Register
Address
1
A
1
1
S
Slave
Address
1
Rd
1
8
A
Data
Byte
1
8
1
1
A
Data
Byte
A
P
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10.6 Register Maps
Y0
In SPI/I2C mode the device can be configured through twenty registers. Register 4 configures the input, Reg 0-3
the PLL and dividers, and Register 5 - 20 configures the 8 different outputs.
CDCM6208 Register programming
INT
DIV
REG 5
Y1
REG 6
REG 4
REG 4
PSB
M
I
REG 1
Charge Pump
and
Loop Filter
VCO
PSA
Y2
REG 4
R
INMUX
PRI
REG 3
SEC
INT
DIV
REG 0
REG 7
N
REG 8
PRI
SEC
Y4
REG 9,10,11
FRAC
DIV
OUTMUX
Y3
REG 2 / REG1
OUTMUX
PRI
SEC
Y5
REG 9
REG 12,13,14
FRAC
DIV
REG 12
Y6
FRAC
DIV
FRAC
DIV
Y7
REG 15,16,17
REG 18,19, 20
Figure 36. Device Register Map
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Register Maps (continued)
Table 11. Register 0
BIT
BIT NAME
15:10
RESERVED
These bits must be set to 0
LF_C3[2:0]
PLL Internal Loop Filter
(C3)
PLL Internal Loop Filter Capacitor (C3) Selection
000 → 35 pF
001→ 112.5 pF
010 → 177.5 pF
011 → 242.5 pF
100 → 310 pF
101 → 377.5 pF
110 → 445 pF
111 → 562.5 pF
PLL Internal Loop Filter
(R3)
PLL Internal Loop Filter Resistor (R3) Selection
000 → 10 Ω
001 → 30 Ω
010 → 60 Ω
011 → 100 Ω
100 → 530 Ω
101→ 1050 Ω
110 → 2080 Ω
111 → 4010 Ω
9:7
6:4
LF_R3[2:0]
3:1
PLL_ICP[2:0]
0
RESERVED
RELATED BLOCK
PLL Charge Pump
DESCRIPTION/FUNCTION
PLL Charge Pump Current Setting
000 → 500 µA
001 → 1.0 mA
010 → 1.5 mA
011 → 2.0 mA
100 → 2.5 mA
101 → 3.0 mA
110 → 3.5 mA
111→ 4.0 mA
This bit is tied to zero statically, and it is recommended to set to 0
when writing to register.
Table 12. Register 1
BIT
BIT NAME
15:2
PLL_REFDIV[13:0]
1:0
PLL_FBDIV1[9:8]
RELATED BLOCK
PLL Reference Divider
DESCRIPTION/FUNCTION
PLL Reference 14-b Divider Selection
(Divider value is register value +1)
PLL Feedback Divider 1 PLL Feedback 10-b Divider Selection, Bits 9:8
Table 13. Register 2
BIT
BIT NAME
RELATED BLOCK
DESCRIPTION/FUNCTION
15:8
PLL_FBDIV1[7:0]
PLL Feedback 10-b Divider Selection, Bits 7:0
PLL Feedback Divider 1
(Divider value is register value +1)
7:0
PLL_FBDIV0[7:0]
PLL Feedback Divider 0
PLL Feedback 8-b Divider Selection
(Divider value is register value +1)
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Table 14. Register 3
BIT
BIT NAME
15:13
RESERVED
RELATED BLOCK
DESCRIPTION/FUNCTION
12
ST1_SEL_REFCLK
11
ST1_LOR_EN
Loss-of-reference Enable on Status 1 pin:
0 → Disable"
1 → Enable (See Table 7 for full description)
10
ST1_PLLLOCK_EN
PLL Lock Indication Enable on Status 1 pin:
0 → Disable
1 → Enable (See Table 7 for full description)
These bits must be set to 0
Reference clock status enable on Status 1 pin:
0 → Disable
1 → Enable (See Table 7 for full description)
Device Status
Reference clock status enable on Status 0 pin:
0 → Disable
1 → Enable (See Table 7 for full description)
9
ST0_SEL_REFCLK
8
ST0_LOR_EN
Loss-of-reference Enable on Status 0 pin:
0 → Disable
1 → Enable (See Table 7 for full description)
7
ST0_PLLLOCK_EN
PLL Lock Indication Enable on Status 0 pin:"
0 → Disable
1 → Enable (See Table 7 for full description)
6
RSTN
Device Reset
Device Reset Selection:
0 → Device In Reset (retains register values)
1 → Normal Operation
5
SYNCN
Output Divider
Output Channel Dividers Synchronization Enable:
0 → Forces synchronization
1 → Exits synchronization
4
ENCAL
PLL/VCO
3:2
1:0
PLL/VCO Calibration Enable:
0 → Disable
1 → Enable
PS_B[1:0]
PLL Prescaler 1 Integer Divider Selection:
00 → Divide-by-4
01→ Divide-by-5
PLL Prescaler Divider B
10 → Divide-by-6
11 → RESERVED
used for Y2, Y3, Y6, and Y7
PS_A[1:0]
PLL Prescaler 0 Integer Divider Selection:
00 → Divide-by-4
01 → Divide-by-5
PLL Prescaler Divider A
10 → Divide-by-6
11 → RESERVED
used in PLL feedback, Y0, Y1, Y4, and Y5
Table 15. Register 4
BIT
15:14
13
12
44
BIT NAME
RELATED BLOCK
SMUX_PW[1:0]
SMUX_MODE_SEL
SMUX_REF_SEL
DESCRIPTION/FUNCTION
Smart MUX Pulse Width Selection. This bit controls the Smart MUX
delay and waveform reshaping.
00 → PLL Smart MUX Clock Delay and Reshape Disabled (default
in all pin modes)
01 → PLL Smart MUX Clock Delay Enable
10 → PLL Smart MUX Clock Reshape Enable
11 → PLL Smart MUX Clock Delay and Reshape Enable
Reference Input Smart
MUX
Smart MUX Mode Selection:
0 → Auto select
1 → Manual select
Note: in Auto select mode, both input buffers must be enabled. Set
R4.5 = 1 and R4.2 = 1
Smart MUX Selection for PLL Reference:
0 → Primary
1 → Secondary (only if REF_SEL pin is high)
This bit is ignored when smartmux is set to auto select (e.g. R4.13 =
0). See Table 7 for details.
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Table 15. Register 4 (continued)
BIT
11:8
7:6
BIT NAME
RELATED BLOCK
CLK_PRI_DIV[3:0]
Primary Input Divider
SEC_SELBUF[1:0]
Secondary Input
5
4:3
(1)
(2)
Secondary Input Buffer Type Selection:
00 → CML
01 → LVDS
10 → LVCMOS
11 → Crystal
Secondary input enable:
0 → Disable
1 → Enable
EN_SEC_CLK
PRI_SELBUF[1:0]
Primary Input
2
DESCRIPTION/FUNCTION
Primary Input (R) Divider Selection:
0000 → Divide by 1
1111 → Divide by 16
Primary Input Buffer Type Selection:
00 → CML
01 → LVDS
10 → LVCMOS
11 → LVCMOS
Primary input enable:
0 → Disable
1 → Enable
EN_PRI_CLK
1
SEC_SUPPLY
(1)
Secondary Input
0
PRI_SUPPLY
(2)
Primary Input
Supply voltage for secondary input:
0 → 1.8 V
1 → 2.5/3.3 V
Supply voltage for primary input:
0 → 1.8 V
1 → 2.5/3.3 V
It is ok to power up the device with a 2.5 V/3.3 V supply while this bit is set to 0. To ensure best device performance this registers
should be updated after power-up to reflect the true VDD_SEC supply voltage used.
It is ok to power up the device with a 2.5 V/3.3 V supply while this bit is set to 0. To ensure best device performance this registers
should be updated after power-up to reflect the true VDD_PRI supply voltage used.
Table 16. Register 5
BIT
BIT NAME
15
RESERVED
This bit must be set to 0
14
RESERVED
This bit must be set to 0
13
RESERVED
This bit must be set to 0
12
RESERVED
This bit must be set to 0
11
RESERVED
This bit must be set to 0
10
RESERVED
This bit must be set to 0
9
RESERVED
This bit must be set to 0
8:7
RELATED BLOCK
Output Channel 1 Type Selection:
00, 01 → LVDS
10 → CML
11 → PECL
SEL_DRVR_CH1[1:0]
Output Channel 1
6:5
EN _CH1[1:0]
4:3
SEL_DRVR_CH0[1:0]
EN_CH0[1:0]
Output channel 1 enable:
00 → Disable
01 → Enable
10 → Drive static 0
11 → Drive static 1
Output Channel 0 Type Selection:
00, 01 → LVDS
10 → CML
11 → PECL
Output Channel 0
2:1
DESCRIPTION/FUNCTION
Output channel 0 enable:
00 → Disable
01 → Enable
10 → Drive static 0
11 → Drive static 1
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Table 16. Register 5 (continued)
BIT
0
(1)
BIT NAME
SUPPLY_CH0_1
RELATED BLOCK
(1)
Output Channels 0
and 1
DESCRIPTION/FUNCTION
Output Channels 0 and 1 Supply Voltage Selection:
0 → 1.8 V
1 → 2.5/3.3 V
It is ok to power up the device with a 2.5 V/3.3 V supply while this bit is set to 0 and to update this bit thereafter.
Table 17. Register 6
BIT
BIT NAME
15
RESERVED
This bit must be set to 0
14
RESERVED
This bit must be set to 0
13
RESERVED
This bit must be set to 0
12
RESERVED
This bit must be set to 0
11
RESERVED
This bit must be set to 0
10
RESERVED
This bit must be set to 0
9
RESERVED
This bit must be set to 0
8
RESERVED
7:0
RELATED BLOCK
DESCRIPTION/FUNCTION
This bit must be set to 0
OUTDIV0_1[7:0]
Output Channels 0
and 1
Output channels 0 and 1 8-b output integer divider setting
(Divider value is register value +1)
Table 18. Register 7
BIT
BIT NAME
15
RESERVED
RELATED BLOCK
This bit must be set to 0
14
RESERVED
This bit must be set to 0
13
RESERVED
This bit must be set to 0
12
RESERVED
This bit must be set to 0
11
RESERVED
This bit must be set to 0
10
RESERVED
This bit must be set to 0
9
RESERVED
This bit must be set to 0
8:7
SEL_DRVR_CH3[1:0]
Output Channel 3 Type Selection:
00, 01 → LVDS
10 → CML
11 → PECL
Output Channel 3
6:5
4:3
EN_CH3[1:0]
0
SEL_DRVR_CH2[1:0]
(1)
46
EN_CH2[1:0]
SUPPLY_CH2_3
(1)
Output channel 3 enable:
00 → Disable
01 → Enable
10 → Drive static 0
11 → Drive static 1
Output Channel 2 Type Selection:
00, 01 → LVDS
10 → CML"
11 → PECL
Output Channel 2
2:1
DESCRIPTION/FUNCTION
Output Channels 2
and 3
Output channel 2 enable:
00 → Disable
01 → Enable
10 → Drive static 0
11 → Drive static 1
Output Channels 2 and 3 Supply Voltage Selection:
0 → 1.8 V
1 → 2.5/3.3 V
It is ok to power up the device with a 2.5 V/3.3 V supply while this bit is set to 0 and to update this bit thereafter.
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Table 19. Register 8
BIT
BIT NAME
15
RESERVED
RELATED BLOCK
This bit must be set to 0
14
RESERVED
This bit must be set to 0
13
RESERVED
This bit must be set to 0
12
RESERVED
This bit must be set to 0
11
RESERVED
This bit must be set to 0
10
RESERVED
This bit must be set to 0
9
RESERVED
This bit must be set to 0
8
RESERVED
This bit must be set to 0
7:0
OUTDIV2_3[7:0]
Output Channels 2
and 3
DESCRIPTION/FUNCTION
Output channels 2 and 3 8-b output integer divider setting
(Divider value is register value +1)
Table 20. Register 9
BIT
BIT NAME
15
RESERVED
14:13
OUTMUX_CH4[1:0]
Output MUX setting for output channel 4:
00 and 11 → PLL
01 → Primary input
10 → Secondary input
12:10
PRE_DIV_CH4[2:0]
Output channel 4 fractional divider's 3-b pre-divider setting (this predivider is bypassed if Q9.9 = 0)
000 → Divide by 2
001 → Divide by 3
111 → Divide by 1
All other combinations reserved
9
EN_FRACDIV_CH4
Output channel 4 fractional divider enable:
0 → Disable
1 → Enable
8
LVCMOS_SLEW_CH4
Output channel 4 LVCMOS output slew:
0 → Normal
1 → Slow
7
EN_LVCMOS_N_CH4
Output channel 4 negative-side LVCMOS enable:
0 → Disable
1 → Enable (Negative side can only be enabled if positive side is
enabled)
6
EN_LVCMOS_P_CH4
5
RESERVED
4:3
SEL_DRVR_CH4[2:0]
2:1
0
(1)
RELATED BLOCK
Output Channel 4
Output channel 4 positive-side LVCMOS enable:
0 → Disable
1 → Enable
This bit must be set to 0
Output channel 4 type selection:
00 or 01 → LVDS
10 → LVCMOS
11 → HCSL
Output channel 4 enable:
00 → Disable
01 → Enable
10 → Drive static 0
11 → Drive static 1
EN_CH4[1:0]
SUPPLY_CH4
DESCRIPTION/FUNCTION
This bit must be set to 0
Output channel 4 Supply Voltage Selection:
0 → 1.8 V
1 → 2.5/3.3 V
(1)
It is ok to power up the device with a 2.5 V / 3.3 V supply while this bit is set to 0 and to update this bit thereafter.
Table 21. Register 10
BIT
BIT NAME
RELATED BLOCK
DESCRIPTION/FUNCTION
15
RESERVED
This bit must be set to 0
14
RESERVED
This bit must be set to 0
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Table 21. Register 10 (continued)
BIT
BIT NAME
13
RESERVED
RELATED BLOCK
This bit must be set to 0
12
RESERVED
This bit must be set to 0
11:4
OUTDIV4[7:0]
3:0
FRACDIV4[19:16]
Output Channel 4
DESCRIPTION/FUNCTION
Output channel 4 8-b integer divider setting
(Divider value is register value +1)
Output channel 4 20-b fractional divider setting, bits 19 - 16
Table 22. Register 11
BIT
BIT NAME
RELATED BLOCK
15:0
FRACDIV4[15:0]
Output Channel 4
DESCRIPTION/FUNCTION
BIT
BIT NAME
RELATED BLOCK
15
RESERVED
14:13
OUTMUX_CH5[1:0]
Output MUX setting for output channel 5:
00 and 11 → PLL
01 → Primary input
10 → Secondary input
12:10
PRE_DIV_CH5[2:0]
Output channel 5 fractional divider's 3-b pre-divider setting (this predivider is bypassed if Q12.9 = 0)
000 → Divide by 2
001 → Divide by 3
111 → Divide by 1
All other combinations reserved
9
EN_FRACDIV_CH5
Output channel 5 fractional divider enable:
0 → Disable
1 → Enable
8
LVCMOS_SLEW_CH5
Output channel 5 LVCMOS output slew:
0 → Normal
1 → Slow
7
EN_LVCMOS_N_CH5
Output channel 5 negative-side LVCMOS enable:
0 → Disable
1 → Enable (Negative side can only be enabled if positive side is
enabled)
6
EN_LVCMOS_P_CH5
5
RESERVED
Output channel 4 20-b fractional divider setting, bits 15 - 0
Table 23. Register 12
4:3
2:1
0
(1)
This bit must be set to 0
Output Channel 5
Output channel 5 positive-side LVCMOS enable:
0 → Disable
1 → Enable
This bit must be set to 0
Output channel 5 type selection:
00 or 01 → LVDS
10 → LVCMOS
11 → HCSL
SEL_DRVR_CH5[2:0]
Output channel 5 enable:
00 → Disable
01 → Enable
10 → Drive static 0
11 → Drive static 1
EN_CH5[1:0]
SUPPLY_CH5
DESCRIPTION/FUNCTION
Output channel 5Supply Voltage Selection:
0 → 1.8 V
1 → 2.5/3.3 V
(1)
It is ok to power up the device with a 2.5 V/3.3 V supply while this bit is set to 0 and to update this bit thereafter.
Table 24. Register 13
48
BIT
BIT NAME
15
RESERVED
RELATED BLOCK
This bit must be set to 0
DESCRIPTION/FUNCTION
14
RESERVED
This bit must be set to 0
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Table 24. Register 13 (continued)
BIT
BIT NAME
13
RESERVED
RELATED BLOCK
This bit must be set to 0
12
RESERVED
This bit must be set to 0
11:4
OUTDIV5[7:0]
3:0
FRACDIV5[19:16]
Output Channel 5
DESCRIPTION/FUNCTION
Output channel 5 8-b integer divider setting
(Divider value is register value +1)
Output channel 5 20-b fractional divider setting, bits 19-16
Table 25. Register 14
BIT
BIT NAME
RELATED BLOCK
15:0
FRACDIV5[15:0]
Output Channel 5
DESCRIPTION/FUNCTION
BIT
BIT NAME
RELATED BLOCK
15
RESERVED
This bit must be set to 0
14
RESERVED
This bit must be set to 0
13
RESERVED
This bit must be set to 0
Output channel 5 20-b fractional divider setting, bits 15-0
Table 26. Register 15
12:10
PRE_DIV_CH6[2:0]
Output channel 6 fractional divider's 3-b pre-divider setting (this predivider is bypassed if Q15.9 = 0)
000 → Divide by 2
001 → Divide by 3
111 → Divide by 1
All other combinations reserved
9
EN_FRACDIV_CH6
Output channel 6 fractional divider enable:
0 → Disable
1 → Enable
8
LVCMOS_SLEW_CH6
Output channel 6 LVCMOS output slew:
0 → Normal
1 → Slow
7
EN_LVCMOS_N_CH6
Output channel 6 negative-side LVCMOS enable:
0 → Disable
1 → Enable (Negative side can only be enabled if positive side is
enabled)
6
EN_LVCMOS_P_CH6
5
RESERVED
4:3
SEL_DRVR_CH6[1:0]
Output Channel 6
2:1
0
(1)
DESCRIPTION/FUNCTION
This bit must be set to 0
Output channel 6 type selection:
00 or 01 → LVDS
10 → LVCMOS
11 → HCSL
Output channel 6 enable:
00 → Disable
01 → Enable
10 → Drive static 0
11 → Drive static 1
EN_CH6[1:0]
SUPPLY_CH6
Output channel 6 positive-side LVCMOS enable:
0 → Disable
1 → Enable
Output channel 6 Supply Voltage Selection:
0 → 1.8 V
1 → 2.5/3.3 V
(1)
It is ok to power up the device with a 2.5 V/3.3 V supply while this bit is set to 0 and to update this bit thereafter.
Table 27. Register 16
BIT
BIT NAME
RELATED BLOCK
DESCRIPTION/FUNCTION
15
RESERVED
This bit must be set to 0
14
RESERVED
This bit must be set to 0
13
RESERVED
This bit must be set to 0
12
RESERVED
This bit must be set to 0
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Table 27. Register 16 (continued)
BIT
BIT NAME
RELATED BLOCK
11:4
OUTDIV6[7:0]
3:0
FRACDIV6[19:16]
Output Channel 6
DESCRIPTION/FUNCTION
Output channel 6 8-b integer divider setting
(Divider value is register value +1)
Output channel 6 20-b fractional divider setting, bits 19-16
Table 28. Register 17
BIT
BIT NAME
RELATED BLOCK
15:0
FRACDIV6[15:0]
Output Channel 6
DESCRIPTION/FUNCTION
Output channel 6 20-b fractional divider setting, bits 15-0
Table 29. Register 18
BIT
BIT NAME
15
RESERVED
This bit must be set to 0
14
RESERVED
This bit must be set to 0
13
RESERVED
This bit must be set to 0
DESCRIPTION/FUNCTION
12:10
PRE_DIV_CH7[2:0]
Output channel 7 fractional divider's 3-b pre-divider setting (this predivider is bypassed if Q18.9 = 0)
000 → Divide by 2
001 → Divide by 3
111 → Divide by 1
All other combinations reserved
9
EN_FRACDIV_CH7
Output channel 7 fractional divider enable: 0 → Disable, 1 →
Enable
8
LVCMOS_SLEW_CH7
Output channel 7 LVCMOS output slew: 0 → Normal, 1 → Slow
7
EN_LVCMOS_N_CH7
Output channel 7 negative-side LVCMOS enable: 0 → Disable, 1 →
Enable (Negative side can only be enabled if positive side is
enabled)
6
EN_LVCMOS_P_CH7
5
RESERVED
4:3
SEL_DRVR_CH7[2:0]
Output channel 7 type selection:00 or 01 → LVDS, 10 → LVCMOS,
11 → HCSL
2:1
EN_CH7[1:0]
Output channel 7 enable: 00 → Disable, 01 → Enable, 10 → Drive
static low, 11 → Drive static high
0
(1)
RELATED BLOCK
SUPPLY_CH7
Output Channel 7
Output channel 7 positive-side LVCMOS enable: 0 → Disable, 1 →
Enable
This bit must be set to 0
Output channel 7 Supply Voltage Selection: 0 → 1.8 V, 1 → 2.5/3.3
V
(1)
It is ok to power up the device with a 2.5 V/3.3 V supply while this bit is set to 0 and to update this bit thereafter.
Table 30. Register 19
BIT
BIT NAME
15
RESERVED
RELATED BLOCK
This bit must be set to 0
14
RESERVED
This bit must be set to 0
13
RESERVED
This bit must be set to 0
12
RESERVED
This bit must be set to 0
11:4
OUTDIV7[7:0]
3:0
FRACDIV7[19:16]
Output Channel 7
DESCRIPTION/FUNCTION
Output channel 7 8-b integer divider setting
(Divider value is register value +1)
Output channel 7 20-b fractional divider setting, bits 19-16
Table 31. Register 20
50
BIT
BIT NAME
RELATED BLOCK
15:0
FRACDIV7[15:0]
Output Channel 7
DESCRIPTION/FUNCTION
Output channel 7 20-b fractional divider setting, bits 15-0
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Table 32. Register 21 (Read Only)
BIT
BIT NAME
15
RESERVED
This bit will read a 0
14
RESERVED
This bit will read a 0
13
RESERVED
This bit will read a 0
12
RESERVED
This bit will read a 0
11
RESERVED
This bit will read a 0
10
RESERVED
This bit will read a 0
9
RESERVED
This bit will read a 0
8
RESERVED
This bit will read a 0
7
RESERVED
This bit will read a 0
6
RESERVED
This bit will read a 0
5
RESERVED
This bit will read a 0
4
RESERVED
This bit will read a 0
3
RESERVED
This bit will read a 0
2
RELATED BLOCK
DESCRIPTION/FUNCTION
Indicates unlock status for PLL (digital):
0 → PLL locked
1 → PLL unlocked
Note: the external output signal on Status 0 or Status 1 uses a
reversed logic, and indicates "lock" with a VOH signal and unlock
with a VOL signaling level.
PLL_UNLOCK
Device Status
Monitoring
1
LOS_REF
Loss of reference input observed at input Smart MUX output in
observation window for PLL:
0 → Reference input present
1 → Loss of reference input
0
SEL_REF
Indicates Reference Selected for PLL:
0 → Primary
1 → Secondary
BIT
BIT NAME
15
RESERVED
Ignore
14
RESERVED
Ignore
13
RESERVED
Ignore
12
RESERVED
Ignore
11
RESERVED
Ignore
10
RESERVED
Ignore
9
RESERVED
Ignore
8
RESERVED
Ignore
7
RESERVED
Ignore
6
RESERVED
Ignore
5:3
VCO_VERSION
2:0
DIE_REVISION
Table 33. Register 40 (Read Only)
RELATED BLOCK
DESCRIPTION/FUNCTION
Indicates the device version (Read only):
000 → CDCM6208V1F
Device Information
Indicates the silicon die revision (Read only):
00X --> Engineering Prototypes
010 --> Production Material
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Table 34. Default Register Setting For SPI/I2C Modes
52
Register
CDCM6208V1F
0
0x01B9
1
0x0000
2
0x0018
3
0x08F4
4
0x20B7
5
0x01BA
6
0x0003
7
0x0002
8
0x0003
9
0x0000
10
0x0040
11
0x0000
12
0x0000
13
0x0040
14
0x0000
15
0x0000
16
0x0040
17
0x0000
18
0x0002
19
0x0040
20
0x7940
.
.
.
.
.
.
40
0x0001
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11 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
11.1 Application Information
The CDCM6208 is a highly integrated clock generator and jitter cleaner. The CDCM6208 derives its output
clocks from an on-chip oscillator which can be buffered through integer or fractional output dividers.
11.2 Typical Applications
DR
CDCM6208
Synthesizer
Mode
Packet
Accel
PCIe
TMS320TCI6616/18
DSP
AIF
ALT
CORE
SRIO
Base Band DSP
Clocking
Timing
Core
Packet
network
Server
Figure 37. Typical Application Circuit
FBADC
RXADC
SyncE
Eth
e
TXDAC
GPS receiver
t
rne
1pps
DPLL
Ethernet
IEEE1588
timing extract
CDCM6208
RF LO
APLL
1pps
RF LO
Pico Cell Clocking
Figure 38. Typical Application Circuit
11.2.1 Design Requirements
The most jitter sensitive application besides driving A-to-D converters are systems deploying a serial link using
Serializer and De-serializer implementation (for example, a 10 GigEthernet). Fully estimating the clock jitter
impact on the link budget requires an understanding of the transmit PLL bandwidth and the receiver CDR
bandwidth.
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Typical Applications (continued)
11.2.1.1 Device Block-level Description
The CDCM6208V1F includes an on-chip PLL with an on-chip VCO. The PLL blocks consist of a universal input
interface, a phase frequency detector (PFD), charge pump, partially integrated loop filter, and a feedback divider.
Completing the CDCM6208V1F device are the combination of integer and fractional output dividers, and
universal output buffers. The PLL is powered by on-chip low dropout (LDO), linear voltage regulators and the
regulated supply network is partitioned such that the sensitive analog supplies are running from separate LDOs
than the digital supplies which use their own LDO. The LDOs provide isolation of the PLL from any noise in the
external power supply rail with a PSNR of better than -50 dB at all frequencies. The regulator capacitor pin
REG_CAP should be connected to ground by a 10 µF capacitor with low ESR (e.g. below 1 Ω ESR) to ensure
stability.
11.2.1.2 Device Configuration Control
Figure 40 illustrates the relationships between device states, the control pins, device initialization and
configuration, and device operational modes. In pin mode, the state of the control pins determines the
configuration of the device for all device states. In programming mode, the device registers are initialized to their
default state and the host can update the configuration by writing to the device registers. A system may transition
a device from pin mode to host connected mode by changing the state of the SI_MODE pins and then triggering
a device reset (either via the RESETN pin or via setting the RESETN bit in the device registers). In reset, the
device disables the outputs so that unwanted sporadic activity associated with device initialization does not
appear on the device outputs.
54
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Typical Applications (continued)
11.2.1.3 Configuring the RESETN Pin
Figure 39 shows two typical applications examples of the RESETN pin.
DVDD
DVDD
50k
GPO
DVDD
50k
#44 (RESET)
50k
#44 (RESET)
#44 (PWR)
RPD
5k
Host
Controller
CDCM6208
CDCM6208
CDCM6208
if I/O power = 1.8V: RPD=0-Ohm
if I/O power=3.3V: RPD=open
(a) (SPI/I2C Host mode)
(b) (SPI/I2C Host Mode)
(c) (PIN Mode)
Figure 39. RESETN/PWR Pin Configurations
Figure 39 (a) SPI / I2C mode only: shows the RESETN pin connected to a digital device that controls device
reset. The resistor and capacitor combination ensure reset is held low even if the CDCM6208V1F is powered up
before the host controller output signal is valid.
Figure 39 (b) SPI / I2C mode only:shows a configuration in which the user wishes to introduce a delay between
the time that the system applies power to the device and the device exiting reset. If the user does not use a
capacitor, then the device effectively ignores the state of the RESETN pin.
Figure 39 (c) Pin mode only: shows a configuration useful if the device is used in Pin Mode. Here device pin
number 44 becomes the PWR input. An external pull down resistor can be used to pull this pin down. If the
resistor is not installed, the pin is internally pulled high.
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Typical Applications (continued)
Figure 40 shows how the different possible device configurations and when the VCO becomes calibrated and the
outputs turn on and off.
Power on
Reset
no
PDN =1?
(all outputs are disabled)
SI_MODE1
SI_MODE0
01
00
I2C Mode
(activate I2C IF)
10
no
RESETN =1?
Pin Mode
SPI Mode
(activate SPI IF)
latch PIN0 to PIN4, and
PWR
Enter Pin Mode specified by
the PINx and PWR
load device registers with defaults; registers
are customer programmable through serial IF
wait for selected reference input
signal (PRI/SEC) to become valid
no
Configure all device settings
wait for selected reference
input signal (PRI/SEC) to
become valid
Calibrate VCO
Calibrate VCO
no
Disable
all
outputs
Disable
all
outputs
RESETN =1?
no
SYNCN =1?
SYNCN =1?
Synchronize outputs
Enable outputs
Synchronize outputs
Enable all outputs
Normal device operation in
PIN mode
Normal device operation in
HOST mode
SYNCN=1?
SYNCN=1?
Disable
all
outputs
no
no
no
yes
yes
RESETN=1?
PDN=1?
PDN=1?
Disable
all
outputs
Figure 40. Device Power up and Configuration
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Typical Applications (continued)
11.2.1.4 Preventing False Output Frequencies in SPI/I2C Mode at Startup:
Some systems require a custom configuration and cannot tolerate any output to start up with a wrong frequency.
Holding RESET low at power-up until the device is fully configured keeps all outputs disabled. The device
calibrates automatically after RESET becomes released and starts out with the desired output frequency.
50k
GPO
DVDD
Release
RESETGPO
50k
RESET=low
RESET=high
CDCM6208
Step 1
Register
Space
outputs on
DVDD
SPI/I2C
SPI or I2C
Master
Register
Space
outputs off
SPI or I2C
Master
Configure
Registers
0 to 21
SPI/I2C
NOTE
The RESETN pin cannot be held low during I2C communication. Instead, use the SYNC
pin to disable the outputs during an I2C write operation, and toggle RESETN pin
afterwards. Alternatively, other options exist such as using the RESETN bit in the register
space to disable outputs until the write operation is complete.
CDCM6208
Step 2
Figure 41. Reset Pin Control During Register Loading
11.2.1.5 Power Down
When the PDN pin = 0, the device enters a complete power down mode with a current consumption of no more
than 1 mA from the entire device.
11.2.1.6 Device Power Up Timing:
Before the device outputs turn on after power up, the device goes through the following initialization routine:
Table 35. Initialization Routine
STEP
DURATION
COMMENTS
Step 1: Power up ramp
Depends on customer supply
ramp time
The POR monitor holds the device in power-down or reset until the
VDD supply voltage reaches 1.06 V (min) to 1.26 V (max)
Step 2: XO startup (if crystal is
used)
Depends on XTAL. Could be
several ms;
For NX3225GA 25 MHz typical
XTAL startup time measures 200
µs.
This step assumes RESETN = 1 and PDN = 1.The XTAL startup
time is the time it takes for the XTAL to oscillate with sufficient
amplitude. The CDCM6208V1F has a built-in amplitude detection
circuit, and holds the device in reset until the XTAL stage has
sufficient swing.
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Typical Applications (continued)
Table 35. Initialization Routine (continued)
STEP
DURATION
COMMENTS
Step 3: Ref Clock Counter
64k Reference clock cycles at
PFD input
This counter of 64 k clock cycles needs to expire before any further
power-up step is done inside the device. This counter ensures that
the input to the PFD from PRI or SEC input has stabilized in
frequency. The duration of this step can range from 640 µs (fPFD=
100 MHz) to 8 sec (8 kHz PFD).
Step 4: FBCLK counter
64k FBCLK cycles with CW=32;
The duration is similar to Step 3,
or can be more accurately
estimated as:
Approximately 64k x PS_A x
N/2.48 GHz
The Feedback counter delays the startup by another 64k PFD clock
cycles. This is so that all counters are well initialized and also ensure
additional timing margin for the reference clock to settle. This step
can range from 640 µs (fPFD= 100 MHz) to 8 sec (fPFD= 8kHz).
Step 5: VCO calibration
128k PFD reference clock cycles
This step calibrates the VCO to the exact frequency range, and
takes exactly 128k PFD clock cycles. The duration can therefore
range from 1280 µs (fPFD= 100 MHz) to 16 sec (f PFD= 8 KHz).
Step 6: PLL lock time
approximately 3 x LBW
The Outputs turn on immediately after calibration. A small frequency
error remains for the duration of approximately 3 x LBW (so in
synthesizer mode typically 10 µs). The initial output frequency will be
lower than the target output frequency, as the loop filter starts out
initially discharged.
Step 7: PLL Lock indicator high
approximately 2305 PFD clock
cycles
The PLL lock indicator if selected on output STATUS0 or STATUS1
will go high after approximately 2048 to 2560 PFD clock cycles to
indicate PLL is now locked.
Y4n
Device outputs held static low
( YxP=low, Yxn=high)
Y 4 ( HCSL)
Outputs tristated
Y4p
Step5
VCO CAL
Step2
XO startup
Step3
Ref Clk Cntr
Step4
FBCLK Cntr
Step6 : PLL lock time
From here
on Device
is locked
RESETN held low
1.8V
1.05V
Step1 : Pwr up
Figure 42. Powerup Time
58
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Figure 43. XTAL Startup Using NX3225GA 25 MHz (Step 2)
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Step 7
Time from PLL Lock
to LOCK signal asserting high on STATUS0 = 78
s
4=3.5%
140ns
250ns
Figure 44. PLL Lock Behavior (Step 6)
11.2.1.7 Input Mux and Smart Input Mux
The Smart Input MUX supports auto-switching and manual-switching using control pin (and through register).
The Smart Input MUX is designed such that glitches created during switching in both auto and manual modes
are suppressed at the MUX output.
Table 36. Input Mux Selection
SI_MODE1
PIN NO. 47
REGISTER 4 BIT
13SMUX_MODE_SE
L
REGISTER 4 BIT 12
SMUX_REF_SEL
REF_SEL
PIN NO. 6
0
X
X
0
0 (SPI/I2C mode)
1
1
1
1 (pin mode)
not available
1
SELECTED INPUT
Auto Select Priority is given to Primary
Reference input.
Primary input
Secondary input
input select through
SPI/I2C
0
Primary input
1
Secondary input
0
Primary or Auto (see Table 5)
1
Secondary or Auto (see Table 5)
input select through
external pin
Example 1:An application desired to auto-select the clock reference in SPI/I2C mode. During production testing
however, the system needs to force the device to use the primary followed by the secondary input. The settings
would be as follows:
1. Tie REF_SEL pin always high
2. For primary clock input testing, use R4[13:12] = 10
3. For secondary clock input testing, set R4[13:12] = 11.
4. For the auto-mux setting in the final product shipment, set R3[13:12]=01 or 00
Example 2: The application wants to select the clock input manually without programming SPI/I2C. In this case,
program R4[13:12] = 11, and select primary or secondary input by toggling REF_SEL low or high.
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SmartMux input frequency limitation: In the automatic mode, the frequencies of both inputs to the smart mux
(PRI_REF divided by R and SEC_REF) need to be similar; however, they can vary by up to 20%.
Switching behavior: The input clocks can have any phase. When switching happens between one input clock to
the other, the phase of the output clock slowly transitions to the phase of the newly selected input clock. There
will be no-phase jump at the output. The phase transition time to the new reference clock signal depends on the
PLL loop filter bandwidth. Auto-switch assigns higher priority to PRI_REF and lower priority to SEC_REF. The
timing diagram of an auto-switch at the input MUX is shown in Figure 45.
Figure 45. Smart Input MUX Auto-Switch Mode Timing Diagram
11.2.1.8 Universal INPUT Buffer (PRI_REF, SEC_REF)
The universal input buffers support multiple signaling formats (LVDS, CML or LVCMOS) and these require
external termination schemes. The secondary input buffer also supports crystal inputs and Table 28 provides the
characteristics of the crystal that can be used. Both inputs incorporate hysteresis.
11.2.1.9 VCO Calibration
The LC VCO is designed using high-Q monolithic inductors and has low phase noise characteristics. The VCO of
the CDCM6208V1F must be calibrated to ensure that the clock outputs deliver optimal phase noise performance.
Fundamentally, a VCO calibration establishes an optimal operating point within the tuning range of the VCO.
While transparent to the user, the CDCM6208V1F and the host system perform the following steps comprising a
VCO calibration sequence:
1. Normal Operation- When the CDCM6208V1F is in normal (operational) mode, the state of both the power
down pin (PDN) and reset pin (RESETN) is high.
2. Entering the reset state – If the user wishes to restore all device defaults and initiate a VCO calibration
sequence, then the host system must place the device in reset via the PDN pin, via the RESETN pin, or by
removing and restoring device power. Pulling either of these pins low places the device in the reset state.
Holding either pin low holds the device in reset.
3. Exiting the reset state – The device calibrates the VCO either by exiting the device reset state or through
the device reset command initiated via the host interface. Exiting the reset state occurs automatically after
power is applied and/or the system restores the state of the PDN or RESETN pins from the low to high state.
Exiting the reset state using this method causes the device defaults to be loaded/reloaded into the device
register bank. Invoking a device reset via the register bit does not restore device defaults; rather, the device
retains settings related to the current clock frequency plan. Using this method allows for a VCO calibration
for a frequency plan other than the default state (i.e. the device calibrates the VCO based on the settings
contained within the register bank at the time that the register bit is accessed). The nominal state of this bit is
low. Writing this bit to a high state and then returning it to the low state invokes a device reset without
restoring device defaults.
4. Device stabilization – After exiting the reset state as described in Step 3, the device monitors internal
voltages and starts a reset timer. Only after internal voltages are at the correct level and the reset time has
expired will the device initiate a VCO calibration. This ensures that the device power supplies and phase
locked loops have stabilized prior to calibrating the VCO.
5. VCO Calibration – The CDCM6208V1F calibrates the VCO. During the calibration routine, the device holds
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all outputs in reset so that the CDCM6208V1F generates no spurious clock signals.
11.2.1.10 Reference Divider (R)
The reference (R) divider is a continuous 4-b counter (1 – 16) that is present on the primary input before the
Smart Input MUX. It is operational in the frequency range of 8 kHz to 250 MHz. The output of the R divider sets
the input frequency for the Smart MUX, and the auto switch capability of the Smart MUX can then be employed
as long as the secondary input frequency is no more than ± 20% different from the output of the R divider.
11.2.1.11 Input Divider (M)
The input (M) divider is a continuous 14-b counter (1 – 16384) that is present after the Smart Input MUX. It is
operational in the frequency range of 8 kHz to 250 MHz. The output of the M divider sets the PFD frequency to
the PLL and should be in the range of 8 kHz to 100 MHz.
11.2.1.12 Feedback Divider (N)
The feedback (N) divider is made up of cascaded 8-b counter divider (1 – 256) followed by a 10-b counter divider
(1 – 1024) that are present on the feedback path of the PLL. It is operational in the frequency range of 8 kHz to
800 MHz. The output of the N divider sets the PFD frequency to the PLL and should be in the range of 8 kHz to
100 MHz. The frequency out of the first divider is required to be less than or equal to 200 MHz to ensure proper
operation.
11.2.1.13 Prescaler Dividers (PS_A, PS_B)
The prescaler (PS) dividers are fed by the output of the VCO and are distributed to the output dividers (PS_A to
the dividers for Outputs 0, 1, 4, and 5 and PS_B to the dividers for Outputs 2, 3, 6, and 7. PS_A also completes
the PLL as it also drives the input of the Feedback Divider (N).
11.2.1.14 Phase Frequency Detector (PFD)
The PFD takes inputs from the Smart Input MUX output and the feedback divider output and produces an output
that is dependent on the phase and frequency difference between the two inputs. The allowable range of
frequencies at the inputs of the PFD is from 8 kHz to 100 MHz.
11.2.1.15 Charge Pump (CP)
The charge pump is controlled by the PFD which dictates either to pump up or down in order to charge or
discharge the integrating section of the on-chip loop filter. The integrated and filtered charge pump current is then
converted to a voltage that drives the control voltage node of the internal VCO through the loop filter. The range
of the charge pump current is from 500 µA to 4 mA.
11.2.1.16 Programmable Loop Filter
The on-chip PLL supports a partially internal and partially external loop filter configuration for all PLL loop
bandwidths where the passive external components C1, C2, and R2 are connected to the ELF pin as shown in
Figure 46 to achieve PLL loop bandwidths from 400 kHz down to 10 Hz.
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R2
C2
C1
ELF
R3
C3
Figure 46. CDCM6208V1F PLL Loop Filter Topology
11.2.1.16.1 Loop Filter Component Selection
The loop filter setting and external resistor selection is important to set the PLL to best possible bandwidth and to
minimize jitter. A high bandwidth (≥ 100 kHz) provides best input signal tracking and is therefore desired with a
clean input reference (synthesizer mode). A low bandwidth (≤ 1 kHz) is desired if the input signal quality is
unknown (jitter cleaner mode). TI provides a software tool that makes it easy to select the right loop filter
components. C1, R2, and C2 are external loop filter components, connected to the ELF pin. The 3 rd pole of the
loop filter is device internal with R3 and C3 register selectable.
11.2.1.16.2 Device Output Signaling
LVDS-like: All outputs Y[7:0] support LVDS-like signaling. The actual output stage uses a CML structure and
drives a signal swing identical to LVDS (~350mV). The output slew rate is faster than standard LVDS for best
jitter performance. The LVDS-like outputs should be AC-coupled when interfacing to a LVDS receiver. See
reference schematic Figure 64 for an example. The supply voltage for outputs configured LVDS can be selected
freely between 1.8 V and 3.3 V.
LVPECL-like: Outputs Y[3:0] support LVPECL-like signaling. The actual output stage uses a CML structure but
drives the same signal amplitude and rise time as true emitter coupled logic output stages. The LVPECL-like
outputs should be AC-coupled, and contrary to standard PECL designs, no external termination resistor to VCC2V is used (fewer components for lowest BOM cost). See reference schematic Figure 64 for an example. The
supply voltage for outputs configured LVPECL-like is recommended to be 3.3 V, though even 1.8 V provides
nearly the same output swing and performance at much lower power consumption.
CML: Outputs Y[3:0] support standard CML signaling. The supply voltage for outputs configured CML can be
selected freely between 1.8 V and 3.3 V. A true CML receiver can be driven DC coupled. All other differential
receiver should connected using AC coupling. See reference schematic Figure 64 for a circuit example.
HCSL: Outputs Y[7:4] support HCSL signaling. The supply voltage for outputs configured HCSL can be selected
freely between 1.8 V and 3.3 V. HCSL is referenced to GND, and requires external 50 Ω termination to GND.
See reference schematic for an example.
CMOS: Outputs Y[7:4] support 1.8 V, 2.5 V, and 3.3 V CMOS signaling. A fast or reduced slew rate can be
selected through register programming. Each differential output port can drive one or two CMOS output signals.
Both signals are “in-phase”, meaning their phase offset is zero degrees, and not 180˚. The output swing is set by
providing the according supply voltage (for example, if VDD_Y4=2.5 V, the output swing on Y4 will be 2.5 V
CMOS). Outputs configured for CMOS should only be terminated with a series-resistor near the device output to
preserve the full signal swing. Terminating CMOS signals with a 50 Ω resistor to GND would reduce the output
signal swing significantly.
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11.2.1.16.3 Integer Output Divider (IO)
Each integer output divider is made up of a continuous 10-b counter. The output buffer itself contributes only little
to the total device output jitter due to a low output buffer phase noise floor. The typical output phase noise floor
at an output frequency of 122.88 MHz, 20 MHz offset from the carrier measures as follows: LVCMOS: -157.8
dBc/Hz, LVDS: -158 dBc/Hz, LVPECL: -158.25 dBc/Hz, HCSL: -160 dBc/Hz. Therefore, the overall contribution
of the output buffer to the total jitter is approximately 50 fs-rms (12 k - 20 MHz). An actual measurement of phase
noise floor with different output frequencies for one nominal until yielded the following:
Table 37. Integer Output Divider (IO)
fOUT
LVDS (Y0)
PECL (Y0)
CML (Y0)
HCSL (Y4)
CMOS 3p3V (Y7)
737.28 MHz
-154.0 dBc/Hz
-154.8 dBc/Hz
-154.4 dBc/Hz
-153.1 dBc/Hz
-150.9 dBc/Hz
368.64 MHz
-157.0 dBc/Hz
-155.8 dBc/Hz
-156.4 dBc/Hz
-153.9 dBc/Hz
-153.1 dBc/Hz
184.32 MHz
-157.3 dBc/Hz
-158.6 dBc/Hz
158.1 dBc/Hz
-154.7 dBc/Hz
-156.2 dBc/Hz
92.16 MHz
-161.2 dBc/Hz
-161.6 dBc/Hz
-161.4 dBc/Hz
-155.2 dBc/Hz
-159.4 dBc/Hz
46.08 MHz
-162.2 dBc/Hz
-165.0 dBc/Hz
-163.0 dBc/Hz
-154.0 dBc/Hz
-162.8 dBc/Hz
11.2.1.16.4 Fractional Output Divider (FOD)
The CDCM6208V1F incorporates a fractional output divider on Y[7:4], allowing these outputs to run at noninteger output divide ratios of the PLL frequencies. This feature is useful when systems require different,
unrelated frequencies. The fractional output divider architecture is shown in Figure 47.
Pre-Scaler PS_A or PS_B
VCO
2.39-2.55GHz
2.94-3.13GHz
÷ 4, 5 or 6
Reg 3.4:0
Pre-Scaler
output clock
398-800MHz
FracDiv Pre Divider
÷ 1, 2 or 3
Limit: 200-400MHz
Reg 9.12:10
Reg 12.12:10
Reg 15.12:10
Reg 18.12:10
Integer Divider
÷ 1 to 256
Reg 10.11:4
Reg 13.11:4
Reg 16.11:4
Reg 19.11:4
Fractional division
.xxx
Reg 10.3:0 + Reg 11
Reg 13.3:0 + Reg 14
Reg 16.3:0 + Reg 17
Reg 19.3:0 + Reg 20
Fractional Divider (simplified)
Figure 47. Fractional Output Divider Principle Architecture
(Simplified Graphic, not Showing Output Divider Bypass Options)
The fractional output divider requires an input frequency between 400 MHz and 800 MHz, and outputs any
frequency equal or less than 400 MHz (the minimum fractional output divider setting is 2). The fractional divider
block has a first stage integer pre-divider followed by a fractional sigma-delta output divider block that is deep
enough such as to generate any output frequency in the range of 0.78 MHz to 400 MHz from any input frequency
in the range of 400 MHz to 800 MHz with a worst case frequency accuracy of no more than ±1ppm. The
fractional values available are all possible 20-b representations of fractions within the following range:
• 1.0 ≤ ƒracDIV ≤ 1.9375
• 2.0 ≤ ƒracDIV ≤ 3.875
• 4.0 ≤ ƒracDIV ≤ 5.875
• x.0 ≤ ƒracDIV ≤ (x + 1) + 0.875 with x being all even numbers from x = 2, 4, 6, 8, 10, ...., 254
• 254.0 ≤ ƒracDIV ≤ 255.875
• 256.0 ≤ ƒracDIV ≤ 256.99999
The CDCM6208V1F user GUI comprehends the fractional divider limitations; therefore, using the GUI to
comprehend frequency planning is recommended.
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The fractional divider output jitter is a function of fractional divider input frequency and furthermore depends on
which bits are exercised within the fractional divider. Exercising only MSB or LSB bits provides better jitter than
exercising bits near the center of the fractional divider. Jitter data are provided in this document, and vary from
50 ps-pp to 200 ps-pp, when the device is operated as a frequency synthesizer with high PLL bandwidths
(approximately 100 kHz to 400 kHz). When the device is operated as a jitter cleaner with low PLL bandwidths (<
1 kHz), its additive total jitter increases by as much as 30 ps-pp. The fractional divider can be used in integer
mode. However, if only an integer divide ratio is needed, it is important to disable the corresponding fractional
divider enable bit, which engages the higher performing integer divider.
11.2.1.16.5 Output Synchronization
Both types of output dividers can be synchronized using the SYNCN signal. For the CDCM6208V1F, this signal
comes from the SYNCN pin or the soft SYNCN register bit R3.5. The most common way to execute the output
synchronization is to toggle the SYNCN pin. When SYNC is asserted (VSYNCN ≤ VIL), all outputs are disabled
(high-impedance) and the output dividers are reset. When SYNC is de-asserted (VSYNCN ≥ VIH), the device first
internally latches the signal, then retimes the signal with the pre-scaler, and finally turns all outputs on
simultaneously. The first rising edge of the outputs is therefore approximately 15 ns to 20 ns delayed from the
SYNC pin assertion. For one particular device configuration, the uncertainty of the delay is ±1 PS_A clock cycles.
For one particular device and one particular configuration, the delay uncertainty is one PS_A clock cycle.
The SYNC feature is particularly helpful in systems with multiple CDCM6208V1F. If SYNC is released
simultaneously for all devices, the total remaining output skew uncertainty is ±1 clock cycles for all devices
configured to identical pre-scaler settings. For devices with varying pre-scaler settings, the total part-to-part skew
uncertainty due to sync remains ±2 clock cycles.
Outputs Y0, Y1, Y4, and Y5 are aligned with the PS_A output while outputs Y2, Y3, Y6, and Y7 are aligned with
the PS_B output). All outputs Y[7:0] turn on simultaneously, if PS_B and PS_A are set to identical divide values
(PS_A=PS_B).
PS_A
1
2
3
4
5
6
7
8
9
10
11
12
One pre-scaler clock cycle
uncertainty, of when the
output turns on for one
device in one particular
configuration
SYNCN
Outputs tristates
Y0
Possibility (A)
Y0
Outputs turned on
Possibility (B)
Figure 48. SYNCN to Output Delay Uncertainty
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11.2.1.16.6 Output MUX on Y4 and Y5
The CDCM6208V1F device outputs Y4 and Y5 can either be used as independent fractional outputs or allow
bypassing of the PLL in order to output the primary or secondary input signal directly.
11.2.1.16.7 Staggered CLK Output Powerup for Power Sequencing of a DSP
DSPs are sensitive to any kind of voltage swing on unpowered input rails. To protect the DSP from long-term
reliability problems, it is recommended to avoid any clock signal to the DSP until the DSP power rail is also
powered up. This can be achieved in two ways using the CDCM6208V1F:
1. Digital control: Initiating a configuration of all registers so that all outputs are disabled, and then turning on
outputs one by one through serial interface after each DSP rail becomes powered up accordingly.
2. Output Power supply domain control: An even easier scheme might be to connect the clock output power
supply VDD_Yx to the corresponding DSP input clock supply domain. In this case, the CDCM6208V1F
output will remain disabled until the DSP rails ramps up as well. Figure 49 shows the turn-on behavior.
Figure 49. Sequencing the Output Turn-on Through Sequencing the Output Supplies. Output Y2 Powers
Up While Output Y0 is Already Running.
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11.2.2 Detailed Design Procedure
11.2.2.1 Jitter Considerations in SERDES Systems
The most jitter sensitive application besides driving A-to-D converters are systems deploying a serial link using
Serializer and De-serializer implementation (for example, 10 GigEthernet). Fully estimating the clock jitter impact
on the link budget requires an understanding of the transmit PLL bandwidth and the receiver CDR bandwidth. As
can be seen in Figure 50, the bandwidth of TX and RX is the frequency range in which clock jitter adds without
any attenuation to the jitter budget of the link. Outside of these frequencies, the SERDES link will attenuate clock
jitter with a 20 dB/dec or even steeper roll-off.
Parallel out
De-Serializer
Parallel in
Serializer
serial data with
embedded clock
TX PLL
RX PLL
/ de
dB
/de
c
RX REF
CLOCK
c
20
dB
1-HRXPLL(f)
20
TX REF
CLOCK
HTXPLL(f)
CDR
flow=BWRX PLL
HTransfer(f) = HTXPLL * ( 1 - HRXPLL)
/de
dB
20
dB
/de
c
20
HTransfer(f)
fhigh=BWTX PLL
c
flow
fhigh
fhigh=20MHz for 10GbE
flow=1.875MHz for 10GbE
Figure 50. Serial Link Jitter Budget Explanation
Example: SERDES link with KeyStone™ I DSP
The SERDES TX PLL of the TI KeyStone™ I DSP family (see SPRABI2) for the SRIO interface, has a 13 MHz
PLL bandwidth (Low Pass Characteristic, see Figure 50). The CDCM6208V2, pin-mode 27, was characterized in
this example over Process, Voltage and Temperature (PVT) with a low pass filter of 13 MHz to simulate the TX
PLL. The attenuation is higher or equal to 20 dB/dec; therefore, the characterization used 20 dB/dec as worst
case.
Table 38 shows the maximum Total Jitter (1) over PVT with and without Low Pass Filter.
Table 38. Maximum Total Jitter Over PVT With and Without Low Pass Filter
(1)
OUTPUT
FREQUENCY
[MHz]
MAX TJ [ps]
DSP SPEC
MAX TJ [ps]
without LOW PASS FILTER
MAX TJ [ps]
with 13 MHz LOW PASS
FILTER
Y0
122.88
56
9.43
8.19
Y2
30.72
56
9.60
7.36
Y3
30.72
56
9.47
7.42
Input signal: 250fs RMS (Integration Range 12kHz to 5MHz)
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Table 38. Maximum Total Jitter Over PVT With and Without Low Pass Filter (continued)
OUTPUT
FREQUENCY
[MHz]
MAX TJ [ps]
DSP SPEC
MAX TJ [ps]
without LOW PASS FILTER
MAX TJ [ps]
with 13 MHz LOW PASS
FILTER
Y4
156.25
(6 bit fraction)
56
57.66
17.48
Y5
156.25
(20 bit fraction)
56
76.87
32.32
Y6
100.00
56
86.30
33.86
Y7
66.667
300
81.71
35.77
Figure 51 shows the maximum Total Jitter with, without Low Pass Filter characteristic and the maximum TI
KeyStone™ I specification.
Figure 51. Maximum Jitter Over PVT
NOTE
Due to the damping characteristic of the DSP SERDES PLLs, the actual TJ data can be
worse.
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11.2.2.2 Jitter Considerations in ADC and DAC Systems
A/D and D/A converters are sensitive to clock jitter in two ways: They are sensitive to phase noise in a particular
frequency band, and also have maximum spur level requirements to achieve maximum noise floor sensitivity.
The following test results were achieved connecting the CDCM6208V1F to ADC and DACs:
Figure 52. IF = 60 MHz Fclk = 122.88 MHz Baseline (Lab Clk Generator) ADC: ADS62P48-49
Figure 53. IF = 60 MHz Fclk = 122.88 MHz CDCM6208V1F driving ADC
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Observation: up to an IF = 100 MHz, The ADC performance when driven by the CDCM6208V1F (Figure 53) is
similar to when the ADC is driven by an expensive lab signal generator with additional passive source filtering
(Figure 52).
Conclusion Therefore, the CDCM6208V1F is usable for applications up to 100 MHz IF. For IF above 100 MHz,
the SNR starts degrading in our experiments. Measurements were conducted with ADC connected to Y0 and
other outputs running at different integer frequencies.
Important note on crosstalk: it is highly recommended that both pre-dividers are configured identically, as
otherwise SFDR and SNR suffer due to crosstalk between the two pre-divider frequencies.
245.76MHz DAC
driven from ³LGHDOVRXUFH´
(Wenzel oscillator buffered by HP8133A)
245.76MHz DAC
driven from CDCM6208
(no performance degradation observed)
* RBW 30 kHz
* RBW 30 kHz
* VBW 300 kHz
* VBW 300 kHz
Ref -14.1 dBm
* Att
5 dB
Ref -14.1 dBm
* SWT 1 s
5 dB
* SWT 1 s
-20
-20
-30
-30
A
A
-40
-40
1 RM *
* Att
1 RM *
-50
-50
CLRWR
CLRWR
-60
-60
-70
-70
-80
-80
NOR
NOR
-90
-90
-100
-100
-110
-110
Center
245.76 MHz
2.55 MHz/
Tx Channel
Bandwidth
Adjacent Channel
Bandwidth
Spacing
Alternate Channel
Bandwidth
Spacing
Span 25.5 MHz PRN
3.84 MHz
5 MHz
3.84 MHz
10 MHz
Power
Lower
Upper
Lower
Upper
245.76 MHz
2.55 MHz/
Tx Channel
W-CDMA 3GPP FWD
3.84 MHz
Center
-9.39 dBm
-72.81 dB
-72.40 dB
-77.79 dB
-78.31 dB
Bandwidth
Adjacent Channel
Bandwidth
Spacing
Alternate Channel
Bandwidth
Spacing
Span 25.5 MHz PRN
W-CDMA 3GPP FWD
3.84 MHz
3.84 MHz
5 MHz
3.84 MHz
10 MHz
Power
-9.40 dBm
Lower
Upper
-73.12 dB
-73.06 dB
Lower
Upper
-79.22 dB
-79.19 dB
Figure 54. DAC Driven by Lab Source and CDCM6208V1F in Comparison (Performance Identical)
Observation/Conclusion: The DAC performance was not degraded at all by the CDCM6208V1F compared to
driving the DAC with a perfect lab source. Therefore, the CDCM6208V1F provides sufficient low noise to drive a
245.76 MHz DAC.
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11.2.3 Application Performance Plots
11.2.3.1 Typical Device Jitter
Figure 55. Typical Device Output Phase Noise and Jitter
for 25 MHz
Figure 56. Typical Device Output Phase Noise and Jitter
for 312.5 MHz
0
156.25MHz output using 60Hz Loop
Bandwidth; Clock source is ok to be noisy,
as CDCM6208 filters the jitter out of the
noisy source; RJ=1.2ps-rms (12k-20MHz)
-20
Noise (dB/Hz)
-40
-60
156.25 MHZ
with 60 Hz BW
-80
156.25 MHZ
closed loop
-100
-120
156.25MHz output using 300kHz
bandwidth; Clock source needs to
be clean (e.g. XTAL source)
RJ=265fs-rms
-140
-160
1
10
100
1k
10k
100k
1M
10M 100M
Frequency (Hz)
Figure 57. Phase Noise Plot for Jitter Cleaning Mode (blue) and Synthesizer Mode (green)
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12 Power Supply Recommendations
12.1 Power Rail Sequencing, Power Supply Ramp Rate, and Mixing Supply Domains
Mixing Supplies: The CDCM6208V1F incorporates a very flexible power supply architecture. Each building
block has its own power supply domain, and can be driven independently with 1.8 V, 2.5 V, or 3.3 V . This is
especially of advantage to minimize total system cost by deploying multiple low-cost LDOs instead of one, moreexpensive LDO. This also allows mixed IO supply voltages (e.g. one CMOS output with 1.8 V, another with 3.3
V) or interfacing to a SPI/I2C controller with 3.3 V supply while other blocks are driven from a lower supply
voltage to minimize power consumption. The CDCM6208V1F current consumption is practically independent of
the supply voltage, and therefore a lower supply voltage consumes lower device power. Also note that outputs
Y3:0 if used for PECL swing will provide higher output swing if the according output domains are connected to
2.5 V or 3.3 V.
Power-on Reset: The CDCM6208V1F integrates a built-in POR circuit, that holds the device in powerdown until
all input, digital, and PLL supplies have reached at least 1.06 V (min) to 1.24 V (max). After this power-on
release, device internal counters start (see previous section on device power up timing) followed by device
calibration. While the device digital circuit resets properly at this supply voltage level, the device is not ready to
calibrate at such a low voltage. Therefore, for slow power up ramps, the counters expire before the supply
voltage reaches the minimum voltage of 1.71 V. Hence for slow power-supply ramp rates, it is necessary to delay
calibration further using the PDN input.
Slow power-up supply ramp: No particular power supply sequence is required for the CDCM6208V1F.
However, it is necessary to ensure that device calibration occurs AFTER the DVDD supply as well as the
VDD_PLL1, VDD_PLL2, VDD_PRI, and VDD_SEC supply are all operational, and the voltage on each supply is
higher than 1.45. This is best realized by delaying the PDN low-to-high transition. The PDN input incorporates a
50 kΩ resistor to DVDD. Assuming the DVDD supply ramp has a fixed time relationship to the slowest of all PLL
and input power supplies, a capacitor from PDN to GND can delay the PDN input signal sufficiently to toggle
PDN low-to-high AFTER all other supplies are stable. However, if the DVDD supply ramps much sooner than the
PLL or input supplies, additional means are necessary to prevent PDN from toggling too early. A premature
toggling of PDN would possibly result in failed PLL calibration, which can only be corrected by re-calibrating the
PLL by either toggling PDN or RESET high-low-high.
VDVDD
PDN
1.8V ,
2.5V , or
3.3V
1.3V
50k
0V
VDD_PLL 1, VDD_ PLL2, VDD_PRI,
VDD_SEC all must rise before PDN toggles high
VDVDD
t? 0
CPDN
VDVDD
CDCM6208
VIH( min)
VPDN
0V
Figure 58. PDN Delay When Using Slow Ramping Power Supplies (Supply Ramp > 50 ms)
12.1.1 Fast Power-up Supply Ramp
If the supply ramp time for DVDD, VDD_PLL1, VDD_PLL2, VDD_PRI, and VDD_SEC are faster than 50 ms from
0 V to 1.8 V, no special provisions are necessary on PDN; the PDN pin can be left floating. Even an external
capacitor to GND can be omitted in this circumstance, as the device delays calibration sufficiently by internal
means.
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Power Rail Sequencing, Power Supply Ramp Rate, and Mixing Supply Domains (continued)
12.1.2 Delaying VDD_Yx_Yy to Protect DSP IOs
DSPs and other highly integrated processors sometimes do not permit any clock signal to be present until the
DSP power supply for the corresponding IO is also present. The CDCM6208V1F allows to either sequence
output clock signals by writing to the corresponding output enable bit through SPI/I2C, or alternatively it is
possible to connect the DSP IO supply and the CDCM6208V1F output supply together, in which case the
CDCM6208V1F output will not turn on until the DSP supply is also valid. This second implementation avoids
SPI/I2C programming.
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13 Layout
13.1 Layout Guidelines
Employing the thermally enhanced printed circuit board layout shown in Figure 59 insures good thermal
performance of the solution. Observing good thermal layout practices enables the thermal pad on the backside of
the QFN-48 package to provide a good thermal path between the die contained within the package and the
ambient air. This thermal pad also serves as the ground connection the device; therefore, a low inductance
connection to the ground plane is essential.
13.2 Layout Example
Figure 59 shows a layout optimized for good thermal performance and a good power supply connection as well.
The 7×7 filled via pattern facilitates both considerations.
Figure 59. Recommended PCB layout of CDCM6208
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Layout Example (continued)
Figure 60 shows two conceptual layouts detailing recommended placement of power supply bypass capacitors. If
the capacitors are mounted on the back side, 0402 components can be employed; however, soldering to the
Thermal Dissipation Pad can be difficult. For component side mounting, use 0201 body size capacitors to
facilitate signal routing. Keep the connections between the bypass capacitors and the power supply on the
device as short as possible. Ground the other side of the capacitor using a low impedance connection to the
ground plane.
Figure 60. PCB Conceptual Layouts
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13.2.1 Reference Schematic
5
4
STATUS1_PIN0
REG_CAP
3
SDI_SDA_PIN1
SDO_AD0_PIN2
SCS_AD1_PIN3
2
1
SCL_PIN4
C82
Place 10uF close to
device pin to minimize
series resistance
10uF/6.3V
General Power supply related note:
Place all 0.1uF bypass caps as close as possible to device pins.
DNI
DNI
DNI
DNI
DNI
DNI
DNI
DNI
DNI
BLM15HD102SN1D
1 L1
2
DNI
C298
D
DVDD
PWR_MONITOR
DVDD
DVDD
DVDD
C283
VDD_PLL
C282
C280
D
VDD_PLL_A
DVDD
0.1uF
100pF
0.1uF
1uF
10uF
C288
C279
VDD_OUT01
RESET_PWR
C295
0.1uF
VDD_PLL
VDD_PLL_A
REG_CAP
ELF
SYNCN
PDN
RESET_PWR
C289
C284
0.1uF
1uF
C276
0.1uF
1uF
VDD_OUT4
C
C
37
VDD_PLL2
VDD_PLL1
38
39
VDD_VCO
40
ELF
PDN
REG_CAP
41
43
42
45
44
STATUS1/PIN0
STATUS0
SI_MODE1
RESETN/PWR
46
48
47
DVDD
SYNCN
VDD2_Y2_Y3
VDD_Y4
Y4_P
Y4_N
36
DSP_CLK7N
35
34
C291
VDD_OUT7
33
0.1uF
32
0.1uF
30
C300
0.1uF
1uF
B
VDD_OUT7
DSP_CLK5N
C301
0.1uF
C303
C302
DSP_CLK5P
0.1uF
27
0.1uF
1uF
VDD_OUT4
26
0.1uF
25
0.1uF
DSP_CLK4N
VDD_PRI_IN
DSP_CLK4P
C304
C305
0.1uF
1uF
VDD_SEC_IN
DVDD
0.1uF
C307
C293
C308
0.1uF
1uF
Rev
01
Title
Date:
3
December, 2011
2
A
1uF
CDCM6208 Reference Schematic
4
1uF
VDD_OUT5
0.1uF
VDD_OUT23
DSP_CLK3N
DSP_CLK3P
DSP_CLK2N
DSP_CLK2P
VDD_OUT23
VDD_OUT01
DSP_CLK1P
DSP_CLK1N
DSP_CLK0N
DSP_CLK0P
C299
0.1uF
C274
VDD_OUT01
C286
0.1uF
C292
VDD_OUT6
A
5
1uF
VDD_OUT6
DSP_CLK6P
31
C287
0.1uF
DSP_CLK6N
28
0.1uF
VDD_OUT5
0.1uF
DSP_CLK7P
29
C277
0.1uF
24
0.1uF
Y3_P
23
Y3_N
22
0.1uF
Y2_N
21
0.1uF
VDD1_Y2_Y3
Y2_P
20
SEC_REFN
0.1uF
SEC_REFP
13
SEC_REFN
VDD_SEC_REF
Y5_N
VDD2_Y0_Y1
12
PRI_REFN
19
11
SEC_REFP
Y5_P
18
10
VDD_SEC_IN
VDD_Y5
U1
PRI_REFP
Y1_P
9
PRI_REFN
VDD_PRI_REF
Y1_N
8
PRI_REFP
VDD_Y6
CDCM6208
17
VDD_PRI_IN
REF_SEL
0.1uF
7
Y0_N
REF_SEL
Y6_P
16
6
VDD_Y7
SCL/PIN4
15
5
SCL_PIN4
Y7_P
Y6_N
0.1uF
SCS_AD1_PIN3
C285
0.1uF
Y7_N
SCS/AD1/PIN3
0.1uF
4
Y0_P
SDO_AD0_PIN2
SDO/AD0/PIN2
14
3
SDI/SDA/PIN1
0.1uF
2
SDI_SDA_PIN1
SI_MODE0
VDD1_Y0_Y1
1
SI_MODE0
POWER_PAD
49
C290
B
C275
0.1uF
VDD_OUT23
STATUS1_PIN0
STATUS0
SI_MODE1
0.1uF
DVDD
Device Reset can connect to
power monitor or left unconnected;
pin has internal 150k pullup
C281
Sheet
1
of
3
1
Figure 61. Schematic Page 1
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5
4
3
2
1
PRIMARY REFERENCE INPUT
LOOP FILTER
C_PRI_P
CLKIN_PRIP
PRI_REFP
1uF
49.9
D
C2
R2
R_PRI_PUP
ELF
VDD_PRI_IN
D
R83
C296
C1
49.9
1uF
R_PRI_PDN
R84
C_PRI_N
CLKIN_PRIN
PRI_REFN
1uF
Loop Filter
Examples:
The following input biasing is recommended:
C
AC coupled differential signals with VDD_PRI/SEC=2.5/3.3V:
select Reg4[7:6]=01 and/or Reg4[4:3]=01 (LVDS),
target VBIAS=1.2V, therefore
set R_PRI_PUP=5.5k, RPRI_PDN=3.14k
DC coupled LVDS signals with VDD_PRI/SEC=2.5/3.3V:
select Reg4[7:6]=01 and/or Reg4[4:3]=01 (LVDS),
R_PRI_PUP=5.5k, RPRI_PDN=3.14k
replace C_PRI_P=C_PRI_N=0Ö
DC coupled 3.3V CMOS signals:
Connect VDD_SEC_IN=3.3V,
select Reg4[7:6]=10 and/or Reg4[4:3]=10 (CMOS),
R83,R84,R85, & R86=DNI, replace C_PRI_P=C_PRI_N=0Ö
for VDD_PRI/SEC=1.8V:
CDCM6208V2:
With C1=470pF, R2=560Ö, C2=100nF and
Internal components R3=100Ö, C3=242.5pF,
fPFD=30.72MHz, and ICP=2.5mA:
Loop bandwidth ~ (300kHz)
target VBIAS=0.9V, therefore
set R_PRI_PUP=5.5k, RPRI_PDN=5.5k
for VDD_PRI/SEC=1.8V:
R_PRI_PUP=5.5k, RPRI_PDN=3.14k
25MHz
4
1
GND0
3
1
GND1
3
CDCM6208V2:
With C1=5éF, R2=100Ö, C2=100éF and
Internal components R3=4.01kÖ, C3=662.5pF,
fPFD=80kHz, and ICP=500éA:
Loop bandwidth ~ (100Hz)
2
NX3225GA
Use of Crystal on secondary reference input (VDD_SEC_,1YROWDJHLVGRQ¬WFDUH):
select Reg4[7:6]=11 (XTAL),
set R87=DNI, R89=DNI, R72=0Ö, R73=0Ö
C
Jitter cleaner mode (low loop bandwidth):
CDCM6208V1:
With C1=4.7éF, R2=145Ö, C2=47éF and
Internal components R3=4.01kÖ, C3=662.5pF,
fPFD=40kHz, and ICP=500éA:
Loop bandwidth ~ (40Hz)
Y1
for 1.8V CMOS signals:
Connect VDD_SEC_IN=1.8V:
DC coupled CML only (VDD_PRI/6(&YROWDJHLVGRQ¬WFDUH):
select Reg4[7:6]=00 and/or Reg4[4:3]=00 (CML),
set R_PRI_PUP=0Ö, RPRI_PDN=DNI,
Replace CPRI_P=0Ö, C_PRI_N=0Ö
B
Synthesizer mode (high loop bandwidth)
CDCM6208V1:
With C1=100pF, R2=500Ö, C2=22nF and
Internal components R3=100Ö, C3=242.5pF,
fPFD=25MHz, and ICP=2.5mA:
Loop bandwidth ~ (300kHz)
B
C27
4pF
C28
4pF
SECONDARY REFERENCE INPUT
R72
R73
DNI
DNI
C29
0.0
CLKIN_SECP
SEC_REFP
R87
1uF
49.9
R_SEC_PUP
VDD_SEC_IN
R85
C297
49.9
A
R_SEC_PDN
1uF
A
R86
C30
0.0
CLKIN_SECN
SEC_REFN
R89
01
CDCM6208 Reference Schematic
Date:
5
Rev
Title
1uF
4
3
December, 2011
2
Sheet
of
2
3
1
Figure 62. Schematic Page 2
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5
4
3
2
1
3.3V Power Supply
2
3p3V
R40
30.9k
1
DNI
R3p3
DNI
VDD_OUT6
2
0
2
2p5V
DNI
2
3p3V
DNI
1p8V
3
R41
10k
4
OUT2
FB
GND
EN
TPS7A8001
NR
IN2
IN1
5
C34
6
7
D
10uF/6.3V
C38
0.01uF
8
2p5V
9
0
R2p5
1p8V
OUT1
1
R1p8
VDD_PLL
2
1
2
GND_PAD
C37
510pF
D
+5V
U6
C39
10uF/6.3V
3p3V
MANY VIAS with Heat Sink
VDD_OUT01
2
0
2
DNI
2
DNI
C
0
VDD_OUT7
0
2
2p5V
DNI
2
3p3V
1p8V
2
DNI
VDD_PRI_IN
1p8V
2p5V
3p3V
2.5V Power Supply
2p5V
2
0
2p5V
DNI
C50
750pF
2p5V
R55
21k
+5V
1
2
2
3p3V
DNI
3p3V
3
2
DNI
1
2
2
DNI
2
DNI
VDD_OUT5
2
0
2
B
DNI
2
DNI
1p8V
VDD_SEC_IN
DNI
2
3p3V
2p5V
3p3V
0
2
2p5V
1p8V
2
DNI
DVDD
R54
10k
1p8V
4
GND
2
0
2
DNI
2
DNI
EN
TPS7A8001
9
0
FB
1
2
OUT2
2p5V
NR
IN2
IN1
5
C35
6
7
10uF/6.3V
C48
0.01uF
8
U7
C49
10uF/6.3V
MANY VIAS with Heat Sink
3p3V
1p8V
B
2p5V
1.8V Power Supply
3p3V
VDD_OUT4, 5, 6, and VDD_OUT7 supply setting
If SPI or I2C is used, set DVDD to the same
reflect the CMOS signal output swing
supply voltage (e.g. 1.8V, 2.5V, or 3.3V)
1p8V
2
VDD_OUT4
OUT1
GND_PAD
DNI
2
C53
1300pF
R58
12.5k
+5V
1
1
2
3
2
Every supply can individually be connected to either 1.8V, 2.5V, or 3.3V. It is also possible to
run all IO from one single supply at 1.8V, 2.5V, or 3.3V.
OUT2
FB
GND
EN
TPS7A8001
9
4
1
R56
10k
OUT1
GND_PAD
2
C
1p8V
2
VDD_OUT23
2
1p8V
NR
IN2
IN1
5
C36
6
7
10uF/6.3V
C51
0.01uF
8
U8
C52
10uF/6.3V
MANY VIAS with Heat Sink
A
A
Rev
Title
01
CDCM6208 Reference Schematic
Date:
5
4
3
2
December, 2011
Sheet
1
3
of
3
Figure 63. Schematic Page 3
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5
4
3
HCSL connection example (DC coupled)
2
1
LVDS or LVPECL connection example (AC coupled)
RS(P)
D
Y4-7_HCSL_P
0
TX-line 50Ö
PCIe_PHY_P
TX-line 50Ö
PCIe_PHY_N
TX-line 50Ö
Y0-7 LVDS_P
Diff_in_P
RS(N)
Y4-7_HCSL_N
0
49.9
DSP with receiver input
termination and selfbiasing
1uF
TX-line 50Ö
Y0-7 LVDS_N
49.9
D
Diff_in_N
1uF
PICe phy
Outputs 4 to 7 have option for HCSL, LVCMOS, LPCML
For HCSL, install 50 ohm termination resistors and adjust
series resistor between 0 and 33 ohms to improve ringing.
C
LVDS or LVPECL connection example (AC coupled)
TX-line 50Ö
Y0-7 LVDS_P
Diff_in_P
DSP without receiver
input termination and
self-biasing
1uF
B
TX-line 50Ö
Y0-7 LVDS_N
B
Diff_in_N
1uF
49.9
49.9
Vbias
100n
A
A
Title
Rev
CDCM6208 Reference Schematic (Extra: output termination)
Date:
5
4
3
December, 2011
2
Sheet
extra
01
of
1
Figure 64. Schematic Page 4
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14 Device and Documentation Support
14.1 Trademarks
KeyStone is a trademark of Texas Instruments.
I2C is a trademark of NXP B.V. Corporation.
All other trademarks are the property of their respective owners.
14.2 Documentation Support
14.2.1 Related Documentation
IC Package Thermal Metrics application report, SPRA953.
Hardware Design Guide for KeyStone Devices SPRABI2 for the SRIO interface.
14.3 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
14.4 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
15 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
(3)
Device Marking
(4/5)
(6)
CDCM6208V1FRGZR
ACTIVE
VQFN
RGZ
48
2500
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
CM6208V1F
CDCM6208V1FRGZT
ACTIVE
VQFN
RGZ
48
250
RoHS & Green
NIPDAU
Level-3-260C-168 HR
-40 to 85
CM6208V1F
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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