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CDCM7005
SCAS793G – JUNE 2005 – REVISED AUGUST 2017
CDCM7005 3.3-V High Performance Clock Synchronizer and Jitter Cleaner
1 Features
3 Description
•
The CDCM7005 is a high-performance, low phase
noise and low skew clock synchronizer that
synchronizes a VCXO (voltage controlled crystal
oscillator) or VCO (voltage controlled oscillator)
frequency to one of the two reference clocks. The
programmable pre-divider M and the feedbackdividers N and P give a high flexibility to the
frequency ratio of the reference clock to VC(X)O
1
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
High Performance LVPECL and LVCMOS PLL
Clock Synchronizer
Two Reference Clock Inputs (Primary and
Secondary Clock) for Redundancy Support With
Manual or Automatic Selection
Accepts LVCMOS Input Frequencies up to 200
MHz
VCXO_IN Clock is Synchronized to One of the
Two Reference Clocks
VCXO_IN Frequencies Up to 2.2 GHz (LVPECL)
Outputs Can Be a Combination of LVPECL and
LVCMOS (Up to Five Differential LVPECL Outputs
or up to 10 LVCMOS Outputs)
Output Frequency is Selectable by ×1, /2, /3, /4,
/6, /8, /16 on Each Output Individually
Efficient Jitter Cleaning From Low PLL Loop
Bandwidth
Low Phase Noise PLL Core
Programmable Phase Offset (PRI_REF and
SEC_REF to Outputs)
Wide Charge Pump Current Range From
200 μA to 3 mA
Dedicated Charge Pump Supply (VCC_CP) for
Wide Tuning Voltage Range VCOs
Presets Charge Pump to VCC_CP/2 for Fast
Center-Frequency Setting of VC(X)O
Analog and Digital PLL Lock Indication
Provides VBB Bias Voltage Output for SingleEnded Input Signals (VCXO_IN)
Frequency Hold-Over Mode Improves Fail-Safe
Operation
Power-up Control Forces LVPECL Outputs to 3State at VCC < 1.5 V
SPI Controllable Device Setting
3.3-V Power Supply
Packaged in 64-Pin BGA (0.8 mm Pitch – ZVA) or
48-Pin QFN (RGZ)
Industrial Temperature Range –40°C to 85°C
VC(X)O_IN clock operates
the selection of external
components, the PLL loop
factor can be adjust to
requirements.
up to 2.2 GHz. Through
VC(X)O and loop filter
bandwidth and damping
meet different system
The CDCM7005 can lock to one of two reference
clock inputs (PRI_REF and SEC_REF), supports
frequency hold-over mode and fast-frequency-locking
for fail-safe and increased system redundancy. The
outputs of the CDCM7005 are user definable and can
be any combination of up to five LVPECL outputs or
up to 10 LVCMOS outputs. The built in
synchronization latches ensure that all outputs are
synchronized for low output skew.
Device Information(1)
PART NUMBER
CDCM7005
PACKAGE
BODY SIZE (NOM)
VQFN (48)
7.00 mm × 7.00 mm
BGA (64)
8.00 mm × 8.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Typical Application Schematic
DAC
PRIREF
YnA
VCXOIN
YnB
CDCM7005
VCXOIN
CPOUT
OSC
VCXO
LF
2 Applications
•
•
•
•
Wireless Infrastructure
SONET
Data Communication
Test Equipment
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
CDCM7005
SCAS793G – JUNE 2005 – REVISED AUGUST 2017
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Description (continued).........................................
Pin Configuration and Functions .........................
Specifications.........................................................
7.1
7.2
7.3
7.4
7.5
7.6
7.7
8
9
1
1
1
2
4
4
7
Absolute Maximum Ratings ...................................... 7
ESD Ratings.............................................................. 7
Recommended Operating Conditions....................... 7
Thermal Information .................................................. 8
Electrical Characteristics........................................... 8
Timing Requirements .............................................. 10
Typical Characteristics ............................................ 11
Parameter Measurement Information ................ 12
Detailed Description ............................................ 15
9.1 Overview ................................................................. 15
9.2 Functional Block Diagram ....................................... 16
9.3 Feature Description................................................. 16
9.4 Device Functional Modes........................................ 24
9.5 Programming........................................................... 25
10 Application and Implementation........................ 34
10.1 Application Information.......................................... 34
10.2 Typical Application ............................................... 37
11 Power Supply Recommendations ..................... 40
12 Layout................................................................... 40
12.1 Layout Guidelines ................................................. 40
12.2 Layout Example .................................................... 41
13 Device and Documentation Support ................. 43
13.1
13.2
13.3
13.4
13.5
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
43
43
43
43
43
14 Mechanical, Packaging, and Orderable
Information ........................................................... 43
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision F (July 2015) to Revision G
Page
•
Removed duplicate row: PRI_SEC_CLK................................................................................................................................ 5
•
Changed text from: "STATUS_REF or" to: "STATUS_REF or PRI_SEC_CLK". ................................................................... 6
Changes from Revision E (February 2013) to Revision F
•
Page
Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional
Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device
and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .............................. 1
Changes from Revision D (August 2009) to Revision E
Page
•
Changed PLL_LOCK pin description, replaced cycle-slip text. .............................................................................................. 5
•
Changed the Frequency Hold-Over Mode section ............................................................................................................... 22
•
Changed text From: Cycle-Slip To: Frequency Offset in Figure 21 ..................................................................................... 23
•
Changed Note 1 of table Word 3.......................................................................................................................................... 29
•
Changed table Word 3, Cycle Slip (Bit 6) To: Frequency Offset.......................................................................................... 29
•
Changed table Lock-Detect Window (Word 3) - Clip slip To: Frequency offset, and Note 2 ............................................... 32
Changes from Revision C (December 2007) to Revision D
Page
•
Added text to the CTRL_CLK pin - Unused or floating inputs must be tied to proper logic level. A 20kΩ or larger
pull−up resistor to VCC is recommended. ............................................................................................................................. 4
•
Added text to the CTRL_DATA pin - Unused or floating inputs must be tied to proper logic level. A 20kΩ or larger
pull−up resistor to VCC is recommended. ............................................................................................................................. 4
•
Added text to the CTRL_LE pin - Unused or floating inputs must be tied to proper logic level. A 20kΩ or larger
pull−up resistor to VCC is recommended. ............................................................................................................................. 4
•
Added text to the PD pin - It is recommended to ramp up the PD with the same time as VCC and AVCC or later. The
2
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ramp up rate of the PD should not be faster than the ramp up rate of VCC and AVCC. .......................................................... 5
•
Changed VCC pin text From: 3.3-V supply. There is no internal connection between VCC and AVCC. It is
recommended that AVCC use its own supply filter. To: 3.3-V supply. VCC and AVCC should always have the same
supply voltage. It is recommended that AVCC use its own supply filter. ................................................................................. 6
•
Added text to the SPI CONTROL INTERFACE section - Unused or floating inputs must be tied to proper logic level.
A 20kΩ or larger pull−up resistor to VCC is recommended. ............................................................................................... 25
•
Added text to the SPI CONTROL INTERFACE section - It is recommended to program Word 0, Word 1, Word 2
and Word 3 right after power up and PD becomes HIGH. ................................................................................................... 25
•
Changed From: RES To: GTME........................................................................................................................................... 29
•
Changed From: RES To: PFDFC ......................................................................................................................................... 29
Changes from Revision B (October 2005) to Revision C
Page
•
Changed N2, From: 1 To: 0.................................................................................................................................................. 30
•
Changed N3, From: 1 To: 0.................................................................................................................................................. 30
•
Changed N3, From: 1 To: 0.................................................................................................................................................. 30
•
Changed N2, From: 1 To: 0.................................................................................................................................................. 30
Changes from Revision A (June 2005) to Revision B
•
Page
Added minor updates. ............................................................................................................................................................ 1
Changes from Original (June 2005) to Revision A
•
Page
Changed data sheet from Product Preview to Production data. ............................................................................................ 1
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SCAS793G – JUNE 2005 – REVISED AUGUST 2017
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5 Description (continued)
All device settings, like outputs signaling, divider value, and input selection are programmable by SPI (3-wire
serial peripheral interface). SPI allows individually control of the device settings.
The device operates in 3.3-V environment and is characterized for operation from –40°C to 85°C.
6 Pin Configuration and Functions
CTRL_DATA
PLL_LOCK
CTRL_CLK
ZVA Package
64-Pin BGA
Top View
AVCC
AVCC
CTRL_LE
AVCC
CP_OUT
NC
VCC_CP
PRI_REF
SEC_REF
REF_SEL
RGZ Package
48-Pin VQFN
Top View
1
36 35 34 33 32 31 30 29 28 27 26 25
24
37
GND
2
3
4
5
6
7
8
CTRL_
DATA PLL_LOCK
A
PRI_REF REF_SEL VCC_CP CP_OUT CTRL_LE CTRL_CLK
B
SEC_REF
GND
GND
GND
GND
GND
GND
C
VBB
GND
AVCC
AVCC
AVCC
AVCC
AVCC
GND
AVCC
38
23
AVCC
39
22
STATUS_REF or
PRI_SEC_CLK
STATUS_VCXO or
I_REF_CP
VBB
40
21
VCC
VCC
41
20
VCC
STATUS_
19
VCC
VCXO
or
18
VCC
Thermal Pad
must be
soldered to GND
D
43
VCC
44
17
Y4B
VCC
45
16
Y4A
Y0A
46
15
VCC
Y0B
47
14
VCC
48
1
RESET or
HOLD
VCC
GND
GND
GND
GND
GND
VCC
Y3A
13
10 11 12
E
VCXO_IN
GND
VCC
VCC
VCC
VCC
VCC
VCC
F
Y0A
GND
GND
GND
GND
GND
VCC
Y4B
G
Y0B
VCC
VCC
VCC
VCC
VCC
VCC
Y4A
H
PD
Y1A
Y1B
Y2A
Y2B
Y3A
Y3B
RESET
or
HOLD
Y3B
9
VCC
8
VCXO_IN
I_REF_CP
VCC
7
Y2A
6
Y2B
VCC
5
VCC
Y1A
4
Y1B
VCC
PD
42
VCXO_IN
3
REF or
PRI_SEC_
CLK
VCXO_IN
2
STATUS_
P0023-01
P0022-01
Pin Functions
PIN
I/O
DESCRIPTION
NAME
BGA
QFN
AVCC
C3, C4,
C5, C6,
C7
27, 30,
32, 38,
39
Analog
Power
CP_OUT
A4
31
O
Charge pump output
CTRL_CLK
A6
28
I
LVCMOS input, serial control clock input for SPI, with hysteresis. Unused or
floating inputs must be tied to proper logic level. A 20kΩ or larger pull−up resistor
to VCC is recommended.
CTRL_DATA
A7
26
I
LVCMOS input, serial control data input for SPI, with hysteresis. Unused or
floating inputs must be tied to proper logic level. A 20kΩ or larger pull−up resistor
to VCC is recommended.
CTRL_LE
A5
29
I
LVCMOS input, control latch enable for serial programmable Interface (SPI), with
hysteresis. Unused or floating inputs must be tied to proper logic level. A 20kΩ or
larger pull−up resistor to VCC is recommended.
B2, B3,
B4, B5,
B6, B7,
B8, C2,
D2, D3,
D4, D5,
D6, E2,
F2, F3,
F4, F5,
F6
Thermal
pad and
pin 24
Ground
GND
4
3.3-V analog power supply. There is no internal connection between AVCC and
VCC. It is recommended that AVCC use its own supply filter.
Ground
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Pin Functions (continued)
PIN
NAME
HOLD
BGA
H8
QFN
14
I/O
I
DESCRIPTION
This LVCMOS input can be programmed (SPI) to act as HOLD or RESET. RESET
is the default function. This pin is low active and can be activated external or via
the corresponding bit in the SPI register. In case of RESET, the charge pump (CP)
is switched to 3-state and all counters (N, M, P) are reset to zero (the initial divider
settings are maintained in SPI registers). The LVPECL outputs are static low and
high respectively and the LVCMOS outputs are all low or high if inverted. RESET
is not edge triggered and should have a pulse duration of at least 5 ns.
In case of HOLD, the CP is switched in to 3-state mode only. After HOLD is
released and with the next valid reference clock cycle the charge pump is
switched back in to normal operation (CP stays in 3-state as long as no reference
clock is valid). During HOLD, the P divider and all outputs Yx are at normal
operation. This mode allows an external control of the frequency hold-over mode.
The input has an internal 150-kΩ pullup resistor.
This LVCMOS output can be programmed (SPI) to provide either the
STATUS_VCXO information or serve as current path for the charge pump (CP).
STATUS_VCXO is the default setting.
I_REF_CP
D8
22
O
In case of STATUS_VCXO, the LVCMOS output provides the status of the VCXO
input (frequencies above 2 MHz are interpreted as valid clock; active high).
In case of I_REF_CP, it provides the current path for the external reference
resistor (12 kΩ ±1%) to support an accurate charge pump current, optional. Do not
use any capacitor across this resistor to prevent noise coupling via this node. If
the internal 12 kΩ is selected (default setting), this pin can be left open.
PD
H1
1
I
LVCMOS input, asynchronous power down (PD) signal. This pin is low active and
can be activated external or by the corresponding bit in the SPI register (in case of
logic high, the SPI setting is valid). Switches the device into power-down mode.
Resets M- and N-Divider, 3-states charge pump, STATUS_REF, or
PRI_SEC_CLK pin, STATUS_VCXO or I_REF_CP pin, PLL_LOCK pin, VBB pin
and all Yx outputs. Sets the SPI register to default value; has internal 150-kΩ
pullup resistor. It is recommended to ramp up the PD with the same time as VCC
and AVCC or later. The ramp up rate of the PD should not be faster than the ramp
up rate of VCC and AVCC.
LVCMOS output for PLL_LOCK information. This pin is set high if the PLL is in
lock (see feature description). This output can be programmed to be digital lock
detect or analog lock detect (see feature description).
PLL_LOCK
A8
25
I/O
The PLL is locked (set high), if the rising edge either of PRI_REF or SEC_REF
clock and VCXO_IN clock at the phase frequency detector (PFD) are inside the
lock detect window for a predetermined number of successive clock cycles.
The PLL is out-of-lock (set low), if the rising edge of either the PRI_REF or
SEC_REF) clock and VCXO_IN clock at the PFD are outside the lock detect
window or if a certain frequency offset between reference frequency and feedback
frequency (VCXO) is detected.
Both, the lock detect window and the number of successive clock cycles are user
definable (via SPI).
PRI_REF
REF_SEL
A1
A2
36
35
I
LVCMOS input for the primary reference clock, with an internal 150-kΩ pullup
resistor and input hysteresis.
I
LVCMOS reference clock selection input. In the manual mode the REF_SEL
signal selects one of the two input clocks:
REF_SEL [1]: PRI_REF is selected;
REF_SEL [0]: SEC_REF is selected;
The input has an internal 150-kΩ pullup resistor.
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Pin Functions (continued)
PIN
NAME
BGA
RESET
H8
QFN
14
I/O
I
DESCRIPTION
This LVCMOS input can be programmed (SPI) to act as HOLD or RESET. RESET
is the default function. This pin is low active and can be activated external or via
the corresponding bit in the SPI register. In case of RESET, the charge pump (CP)
is switched to 3-state and all counters (N, M, P) are reset to zero (the initial divider
settings are maintained in SPI registers). The LVPECL outputs are static low and
high respectively and the LVCMOS outputs are all low or high if inverted. RESET
is not edge triggered and should have a pulse duration of at least 5 ns.
In case of HOLD, the CP is switched in to 3-state mode only. After HOLD is
released and with the next valid reference clock cycle the charge pump is
switched back in to normal operation (CP stays in 3-state as long as no reference
clock is valid). During HOLD, the P divider and all outputs Yx are at normal
operation. This mode allows an external control of the frequency hold-over mode.
The input has an internal 150-kΩ pullup resistor.
SEC_REF
B1
37
I
LVCMOS input for the secondary reference clock, with an internal 150-kΩ pullup
resistor and input hysteresis.
This output can be programmed (SPI) to provide either the STATUS_REF or
PRI_SEC_CLK information. This pin is set high if one of the STATUS conditions is
valid. STATUS_REF is the default setting.
STATUS_REF or
PRI_SEC_CLK
C8
23
O
In case of STATUS_REF, the LVCMOS output provides the Status of the
Reference Clock. If a reference clock with a frequency above 2 MHz is provided to
PRI_REF or SEC_REF STATUS_REF will be set high.
In case of PRI_SEC_CLK, the LVCMOS output indicates whether the primary
clock [high] or the secondary clock [low] is selected.
This LVCMOS output can be programmed (SPI) to provide either the
STATUS_VCXO information or serve as current path for the charge pump (CP).
STATUS_VCXO is the default setting.
STATUS_VCXO
D8
22
O
In case of STATUS_VCXO, the LVCMOS output provides the status of the VCXO
input (frequencies above 2 MHz are interpreted as valid clock; active high).
In case of I_REF_CP, it provides the current path for the external reference
resistor (12 kΩ ±1%) to support an accurate charge pump current, optional. Do not
use any capacitor across this resistor to prevent noise coupling via this node. If
the internal 12 kΩ is selected (default setting), this pin can be left open.
Bias voltage output to be used to bias unused complementary input VCXO_IN for
single ended signals. The output of VBB is VCC – 1.3 V. The output current is
limited to about 1.5 mA.
VBB
C1
40
O
VCC
D7, E3,
E4, E5,
E6, E7,
E8, F7,
G2, G3,
G4, G5,
G6, G7
2, 5, 6,
9, 10,
13, 15,
18, 19,
20, 21,
41, 44,
45; 48
Power
3.3-V supply. VCC and AVCC should always have the same supply voltage. It is
recommended that AVCC use its own supply filter.
VCC_CP
A3
33
Power
This is the charge pump power supply pin used to have the same supply as the
external VCO. It can be set from 2.3 V to 3.6 V.
VCXO_IN
E1
43
I
VCXO LVPECL input
I
Complementary VCXO LVPECL input
O
The outputs of the CDCM7005 are user definable and can be any combination of
up to five LVPECL outputs or up to 10 LVCMOS outputs. The outputs are
selectable via SPI (Word 1, Bit 2-6). The power-up setting is all outputs are
LVPECL.
VCXO_IN
D1
42
Y0A:Y0B
Y1A:Y1B
Y2A:Y2B
Y3A:Y3B
Y4A:Y4B
F1, G1,
H2, H3,
H4, H5,
H6, H7,
G8, F8
46, 47,
3, 4,
7, 8,
11,12,
16, 17
6
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
VCC, AVCC, Supply voltage
VCC_CP
MIN
MAX
UNIT
–0.5
4.6
V
–0.5
VCC + 0.5
V
–0.5
VCC + 0.5
V
±50
mA
(2)
(3)
VI
Input voltage
VO
Output voltage
IOUT
Output current for LVPECL/LVCMOS outputs
(0 < VO < VCC)
IIN
Input current (VI < 0, VI > VCC)
±20
mA
TJ
Maximum junction temperature
125
°C
Tstg
Storage temperature
150
°C
(1)
(2)
(3)
(3)
–65
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability.
All supply voltages have to be supplied at the same time.
The input and output negative voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
7.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±2500
Charged-device model (CDM), per JEDEC specification JESD22C101 (2)
±1500
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
VCC, AVCC
VCC_CP
Supply voltage
MIN
NOM
3
3.3
2.3
(1)
MAX
3.6
VCC
V
VIL
Low-level input voltage LVCMOS, see
VIH
High-level input voltage LVCMOS, see
IOH
High-level output current LVCMOS (includes all status pins)
–8
mA
IOL
Low-level output current LVCMOS (includes all status pins)
8
mA
VI
Input voltage range LVCMOS
(1)
Input amplitude LVPECL (VVCXO_IN – V VCXO_IN )
VIC
Common-mode input voltage LVPECL
TA
Operating free-air temperature
(2)
0.7 VCC
0
VINPP
(1)
0.3 VCC
UNIT
(2)
V
V
3.6
V
0.5
1.3
V
1
VCC–0.3
V
–40
85
°C
VIL and VIH are required to maintain ac specifications; the actual device function tolerates a smaller input level of 1V, if an ac-coupling to
VCC/2 is provided.
VINPP minimum and maximum is required to maintain ac specifications; the actual device function tolerates at a minimum VINPP
of 150 mV.
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7.4 Thermal Information
CDCM7005
THERMAL METRIC
RGZ
AIRFLOW
(lfm)
(1)
ZVA
AIRFLOW
(m/s)
RGZ
(VQFN)
ZVA
(BGA)
48 PINS
64 PINS
0
0
29.9
53.9
150
1
24.7
49.8
250
2
23.2
48.5
500
–
UNIT
RθJA
Junction-to-ambient thermal resistance
21.5
–
RθJC(top)
Junction-to-case (top) thermal resistance
22.4
28.3
°C/W
RθJB
Junction-to-board thermal resistance
14.2
38.6
°C/W
Junction-to-top characterization parameter
ψJT
ψJB
Junction-to-board characterization parameter
RθJC(bot)
Junction-to-case (bottom) thermal resistance
(1)
0
0
0.2
0.7
150
1
0.2
0.7
250
2
0.2
0.8
500
–
0.3
–
–
–
°C/W
°C/W
°C/W
°C/W
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
7.5 Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
TYP (1)
MAX
UNIT
fVCXO = 245.76 MHz,
fREF_IN = 30.72 MHz,
PFD = 240 kHz, ICP = 2 mA, all outputs are LVPECL
and Div-by-8 (load, see Figure 13)
210
260
mA
fVCXO = 245.76 MHz,
fREF_IN = 30.72 MHz,
PFD = 240 kHz, ICP = 2 mA, All outputs are
LVCMOS and Div-by-8 (load, 10 pF)
120
150
mA
fIN = 0 MHz, VCC = 3.6 V, AVCC = 3.6 V,
VCC_CP = 3.6 V,
VI = 0 V or VCC
100
300
µA
±40
µA
±100
µA
PARAMETER
TEST CONDITIONS
MIN
OVERALL
ICC_LVPECL
Supply current (ICC over frequency see
Figure 1 through Figure 4)
ICC_LVCMOS
ICCPD
Power-down current
IOZ
High-impedance state output current for Yx
outputs
VI_REF_CP
Voltage on I_REF_CP (external current path
12 kΩ to GND at pin D8 (BGA), pin 22 (QFN)
for accurate charge pump current)
VBB
Output reference voltage
VCC = 3 V – 3.6 V; IBB = –0.2 mA
CO
Output capacitance for Yx
VCC = 3.3 V, VO = 0 V or VCC
Input capacitance at PRI_REF and
SEC_REF
VI = 0 V or VCC, VI = 0 V or VCC
Input capacitance at CTRL_LE,
CTRL_CLOCK, CTRL_DATA
VI = 0 V or VCC
CI
VO = 0 V or VCC – 0.8 V
VO = 0 V or VCC
1.21
V
VCC–1.3
V
2
pF
2.7
pF
2
LVCMOS
fclk
Output frequency, see
Figure 7
VIK
II
(1)
(2)
(3)
8
(2) (3)
,
, Figure 6, and
Load = 5 pF to GND, 1 kΩ to VCC, 1 kΩ to GND
250
MHz
LVCMOS input clamp voltage
VCC = 3 V, II = –18 mA
–1.2
V
LVCMOS input current for CTRL_LE,
CTRL_CLK, CTRL_DATA
VI = 0 V or VCC, VCC = 3.6 V
±5
µA
All typical values are at VCC = 3.3 V, temperature = 25°C.
fclk can be up to 400 MHz in the typical operating mode (25°C / 3.3-V VCC). The total power consumption limit of 700 mW for the BGA
package can be violated if several LVCMOS outputs switch at high frequency (see Figure 3 and Figure 4).
Operating the LVCMOS or LVPECL output above the maximum frequency will not cause a malfunction to the device, but the output
signal swing may no longer meet the output specification.
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Electrical Characteristics (continued)
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
IIH
LVCMOS input current for PD, RESET,
HOLD, REF_SEL, PRI_REF, SEC_REF,
(see (4))
VI = VCC, VCC = 3.6 V
IIL
LVCMOS input current for PD, RESET,
HOLD, REF_SEL, PRI_REF, SEC_REF,
(see (4))
VI = 0 V, VCC = 3.6 V
VOH
High-level output voltage for LVCMOS
outputs
VCC = min to max,
IOH = –100 μA
VCC = 3 V, IOH = –6 mA
VCC = 3 V, IOH = –12 mA
Low-level output voltage for LVCMOS
outputs
VOL
MIN
TYP (1)
–15
MAX
UNIT
5
µA
–35
µA
VCC–0.1
V
2.4
2
VCC = min to max,
IOL = 100 μA
0.1
VCC = 3 V, IOL = 6 mA
0.5
VCC = 3 V, IOL = 12 mA
0.8
V
IOH
High-level output current
VCC = 3.3 V, VO = 1.65 V
–30
mA
IOL
Low-level output current
VCC = 3.3 V, VO = 1.65 V
33
mA
VREF_IN = VCC/2, Y = VCC/2,
see Figure 11, Load = 10 pF
1.8
ns
(5)
tpho
Phase offset (REF_IN to Y output)
tsk(p)
LVCMOS pulse skew, see Figure 10
Crosspoint to VCC/2 load, see Figure 12
tpd(LH)
tpd(HL)
Propagation delay from VCXO_IN to Yx,
see Figure 10
Crosspoint to VCC/2,
Load = 10 pF, see Figure 12 (PLL bypass mode)
tsk(o)
LVCMOS single-ended output skew, see
and Figure 10
Duty cycle
LVCMOS
VCC/2 to VCC/2
Output rise/fall slew rate
20% to 80% of swing (load
see Figure 12)
tslew-rate
(6)
2
2.5
150
ps
3
ns
All outputs have the same divider ratio
55
Outputs have different divider ratios
70
49%
2.4
ps
51%
3.5
V/ns
LVPECL
fclk
Output frequency, see
II
LVPECL input current
(3)
and Figure 5
Load, see Figure 13
0
VI = 0 V or VCC
1500
MHz
±20
µA
V
V
VOH
LVPECL high-level output voltage
Load, See Figure 13
VCC–1.18
VCC–0.8
1
VOL
LVPECL low-level output voltage
Load, See Figure 13
VCC–2
VCC–1.5
5
|VOD|
Differential output voltage
See Figure 9 and load, see Figure 13
tpho
Phase offset (REF_IN to Y output) (6)
VREF_IN = VCC/2 to cross point of Y, see Figure 11
tpd(LH)
tpd(HL)
Propagation delay time, VCXO_IN to Yx,
see Figure 10
Cross point-to-cross point, load
see Figure 13
tsk(p)
LVPECL pulse skew, see Figure 10
tsk(o)
LVPECL output skew (6)
tr / tf
Rise and fall time
CI
Input capacitance at VCXO_IN, VCXO_IN
500
mV
100
ps
640
ps
Cross point-to-cross point, load
see Figure 13
10
ps
Load see Figure 13, all outputs have the same
divider ratio
20
Load see Figure 13, outputs have
different divider ratios
50
20% to 80% of VOUTPP, see Figure 9
–200
340
490
ps
120
170
220
1.5
ps
pF
LVCMOS-TO-LVPECL
tsk(P_C)
Output skew between LVCMOS and
LVPECL outputs, see (7) and Figure 10
Cross point to VCC/2; load,
see Figure 12 and Figure 13
1.7
2
2.4
ns
PLL ANALOG LOCK
IOH
High-level output current
VCC = 3.6 V, VO = 1.8 V
–110
µA
IOL
Low-level output current
VCC = 3.6 V, VO = 1.8 V
110
µA
(4)
(5)
(6)
(7)
These inputs have an internal 150-kΩ pullup resistor.
This is valid only for the same frequency of REF_IN clock and Y output clock. It can be adjusted by the SPI controller (reference delay M
and VCXO delay N).
The tsk(o) specification is only valid for equal loading of all outputs.
The phase of LVCMOS is lagging in reference to the phase of LVPECL.
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Electrical Characteristics (continued)
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
IOZH LOCK
High-impedance state output current for PLL
VO = 3.6 V (PD is set low)
LOCK output (8)
IOZL
High-impedance state output current for PLL
VO = 0 V (PD is set low)
LOCK output (8)
LOCK
MIN
TYP (1)
MAX
45
65
µA
±5
µA
UNIT
VIT+
Positive input threshold voltage
VCC = min to max
VCC×0.55
V
VIT–
Negative input threshold voltage
VCC = min to max
VCC×0.35
V
PHASE DETECTOR
fCPmax
Maximum charge pump frequency
Default PFD pulse width delay
100
MHz
±3
mA
10
nA
CHARGE PUMP
ICP
Charge pump sink/source current range
ICP3St
Charge pump 3-state current
ICPA
(9)
VCP = 0.5 VCC_CP
±0.2
0.5 V < VCP < VCC_CP – 0.5 V
VCP = 0.5 VCC_CP, internal reference resistor, SPI
default settings
ICP absolute accuracy
VCP = 0.5 VCC_CP, external reference resistor 12 kΩ
(1%) at I_REF_CP, SPI default settings
ICPM
Sink/source current matching
0.5 V < VCP < VCC_CP – 0.5 V, SPI default settings
IVCPM
ICP vs VCP matching
0.5 V < VCP < VCC_CP – 0.5 V
(8)
(9)
10%
5%
2.5%
5%
Lock output has an 80-kΩ pulldown resistor.
Defined by SPI settings.
7.6 Timing Requirements
over recommended ranges of supply voltage, load and operating free air temperature
MIN
NOM
MAX
UNIT
0
200
MHz
40%
60%
0
2200
PRI_REF/SEC_REF_IN REQUIREMENTS
fREF_IN
LVCMOS primary or secondary reference clock frequency (1)
(2)
tr/ tf
Rise and fall time of PRI_REF or SEC_REF signals from 20% to 80% of VCC
dutyREF
Duty cycle of PRI_REF or SEC_REF at VCC/2
4
ns
VCXO_IN, VCXO_IN REQUIREMENTS
fVCXO_IN
VCXO clock frequency (3)
tr/ tf
Rise and fall time 20% to 80% of VINPP at 80 MHz to 800 MHz (4)
dutyVCXO
Duty cycle of VCXO clock
MHz
3
40%
ns
60%
SPI/CONTROL REQUIREMENTS (see Figure 23)
fCTRL_CLK
CTRL_CLK frequency
tsu1
CTRL_DATA to CTRL_CLK setup time
10
20
MHz
ns
th2
CTRL_DATA to CTRL_CLK hold time
10
ns
t3
CTRL_CLK high duration
25
ns
t4
CTRL_CLK low duration
25
ns
tsu5
CTRL_LE to CTRL_CLK setup time
10
ns
tsu6
CTRL_CLK to CTRL_LE setup time
10
ns
t7
CTRL_LE pulse width
20
tr/ tf
Rise and fall time of CTRL_DATA CTRL_CLK, CTRL_LE from 20% to 80% of VCC
ns
4
ns
4
ns
PD, RESET, HOLD, REF_SEL REQUIREMENTS
tr / tf
(1)
(2)
(3)
(4)
10
Rise and fall time of the PD, RESET, HOLD, REF_SEL signal from 20% to 80% of VCC
At Reference Clock less than 2 MHz, the device stays in normal operation mode but the frequency detection circuitry resets the
STATUS_REF signal to low. In this case, the status of the STATUS_REF is no longer relevant.
fREF_IN can be up to 250 MHz in typical operating mode (25°C / 3.3-V VCC).
If the Feedback Clock (derives from VCXO input) is less than 2 MHz, the device stays in normal operation mode but the frequency
detection circuitry resets the STATUS_VCXO signal and PLL_LOCK signal to low. Both status signals are no longer relevant. This
effects the HOLD-over function as well, as the PLL_LOCK signal is no longer valid!
Use a square wave for lower frequencies (< 80 MHz).
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7.7 Typical Characteristics
750
250
PDEV − Device Power Consumption − mW
All Output Pairs Active (4 div-by-8 / 1 div-by-3)
230
D For div-by-3/6
ICC − Supply Current − mA
210
190
All Output Pairs Active (div-by-8)
170
All Output Pairs Active (div-by-1)
150
VCC = 3.3 V
TA = 25°C
D for div-by-2/4/8/16
130
One Output Pair Active (div-by-8)
110
90
No Output Active
D For 1 Output Pair
70
VCC = 3.3 V
TA = 25°C
650
All Output Pairs Active (4 div-by-8 / 1 div-by-3)
550
All Output Pairs Active (div-by-8)
450
All Output Pairs Active (div-by-1)
One Output Pair Active (div-by-8)
350
250
150
No Output Active
50
50
50
250
450
650
850
1050
1250
1450
1650
1850
50
2050
250
450
650
850
1050
1250
1450
1650
1850
2050
VCXO_IN Input Frequency − MHz
VCXO_IN Input Frequency − MHz
G002
G001
If div-by-2/4/8/16 is activated for one or more outputs, 'Δ for div-by2/4/8/16' has to be added to ICC of div-by-1. If div-by-3 or div-by-6 is
activated, 'Δ for div-by-2/4/8/16' and 'Δ for div-by3/6' has to be added
to ICC of div-by-1.
Figure 1. LVPECL Supply Current vs Number of Active
Outputs
Figure 2. LVPECL Device Power Consumption vs Number of
Active Outputs
900
800
700
600
for div−by−3/6
150
500
400
all outputs active div−by−1 one output pair active div−by−1
100
300
200
for 1 output pair
for 1 output
50
100
one output active div−by−1
VCC = 3.3 V
TA = 25°C
Load = 10 pF
700
200
600
for div−by−3/6
500
150
all outputs active div−by−1
400
one output pair active div−by−1
100
300
for 1 output
50
no output active
100
800
for 1 output pair
150
200
no output active
0
300
250
200
100
one output active div−by−1
0
50
all outputs active div−by−3
PDEV − Device Power
Consumption − mW
Icc − Supply Current − mA
200
250
all outputs active div−by−3
PDEV − Power Device Consumption
− mW
Icc − Supply Current − mA
Vcc = 3.3V
TA = 25C
load = 5 pF
0
40
60
80
100
120
140
Output Frequency − MHz
160
180
200
220
240
260
280
0
300
Output Frequency − MHz
It is not recommended to exceed power dissipation of 700 mW for the It is not recommended to exceed power dissipation of 700 mW for the
BGA package at TA 85°C.
BGA package at TA 85°C.
Figure 3. LVCMOS Supply Current and Device Power
Figure 4. LVCMOS Supply Current and Device Power
Consumption vs Number of Active Outputs (Load = 5 pF)
Consumption vs Number of Active Outputs (Load = 10 pF)
3.6
VCC = 3.3 V
TA = 25°C
Termination = 50 to VCC − 2 V
0.85
0.80
0.75
0.70
0.65
0.60
VCC = 3.6 V
3.4
3.2
LVCMOS Output Swing − V
VOD − Differential Output Voltage − V
0.90
3.0
2.8
2.6
VCC = 3.3 V
2.4
VCC = 3 V
2.2
2.0
1.8
0.55
TA = 25°C
Load = 5 pF (See Figure 12)
1.6
1.4
0.50
50
250
450
650
850
1050
1250
1450
1650
50
1850
100
150
200
250
300
350
400
450
500
f − Frequency − MHz
fOut − Output Frequency − MHz
G006
G005
Figure 5. Differential LVPECL Output Voltage vs Output
Frequency
Figure 6. LVCMOS Output Swing vs Frequency
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Typical Characteristics (continued)
3.6
4.0
3.4
VCC = 3.6 V
VBB − Output Reference Voltage − V
LVCMOS Output Swing − V
3.0
2.8
2.6
2.4
VCC = 3.3 V
2.2
VCC = 3 V
2.0
1.8
TA = 25°C
Load = 10 pF (See Figure 12)
1.6
VCC = 3.3 V
TA = 25°C
3.5
3.2
3.0
2.5
2.0
1.5
1.0
0.5
0.0
1.4
50
100
150
200
250
300
350
400
450
−5
500
0
5
10
15
20
25
30
35
I − Load − mA
f − Frequency − MHz
G008
G007
Figure 7. LVCMOS Output Swing vs Frequency
Figure 8. Output Reference Voltage (VBB) vs Load
8 Parameter Measurement Information
Yx
VOH
VOD
Yx
VOL
80%
20%
0V
tr
VOUTpp
tf
T0058-01
Figure 9. LVPECL Differential Output Voltage and Rise/Fall Time
12
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Parameter Measurement Information (continued)
LVPECL
VCXO_IN
/VCXO_IN
tpd(LH) / tpd(HL); tsk(p) = | tpd(HL) − tpd(LH) |
YxA
LVPECL
YxB
YxA
LVPECL
YxB
tsk(o)LVPECL
YxA
LVPECL
YxB
YxA
LVCMOS
tsk p_c
LVCMOS
VCXO_IN
/VCXO_IN
tpd(LH); tsk(p) = | tpd(HL) − tpd(LH) |
YxA/B
LVCMOS
tsk(o)LVCMOS
YxA/B
LVCMOS
A.
Output skew, tsk(o), is calculated as the greater of:
The difference between the fastest and the slowest tpd(LH)n (n = 0...4)
The difference between the fastest and the slowest tpd(HL)n (n = 0...4)
B.
Pluse skew, tsk(p), is calculated as the magnitude of the absolute time difference between the high-to-low (tpd(HL)) and
the low-to-high (tpd(LH)) propagation delays when a single switching input causes one or more outputs to switch,
tsk(p) = |tpd(HL) – tpd(LH) |. Pulse skew is sometimes refered to as pulse width distortion or duty cycle skew.
Figure 10. Output Skew
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Parameter Measurement Information (continued)
VIH
50% VCC
VIL
REF_IN
tpho LVPECL
VOH
YxB
LVPECL
VOL
YxA
tpho LVCMOS
VOH
LVCMOS
VOL
T0060-01
Figure 11. Phase Offset
CDCM7005
1kW
Y3
LVCMOS
1kW
10pF
S0079-01
Figure 12. LVCMOS Output Loading During Device Test
VCC
ZO = 50W
Yx
CDCM7005
Driver
LVPECL
Receiver
ZO = 50W
Yx
50W
50W
VEE
VT = VCC – 2V
S0078-01
Figure 13. LVPECL Output Loading During Device Test
14
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9 Detailed Description
9.1 Overview
The CDCM7005 is a high-performance, low phase noise and low skew clock synchronizer that synchronizes a
VCXO or VCO frequency to one of the two reference clocks. VC(X)O_IN clock operates up to 2.2 GHz. Through
the selection of external VC(X)O and loop filter components, the PLL loop bandwidth and damping factor can be
adjust to meet different system requirements.
The CDCM7005 can lock to one of two reference clock inputs (PRI_REF and SEC_REF), supports frequency
hold-over mode and fast-frequency-locking for fail-safe and increased system redundancy. The outputs of the
CDCM7005 are user definable and can be any combination of up to five LVPECL outputs or up to 10 LVCMOS
outputs. The LVCMOS outputs are arranged in pairs (Y0A:Y0B, Y1A:Y1B, …), so that each pair has the same
frequency. But each output can be separately inverted and disabled. The built in synchronization latches ensure
that all outputs are synchronized for low output skew.
CDCM7005 is programmable through SPI (3-wire serial peripheral interface). SPI allows individually control of
the device settings.
The device operates in 3.3-V environment and is characterized for operation from –40°C to 85°C.
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9.2 Functional Block Diagram
VCC
AVCC
VCC_CP
Selected REF Signal
REF_SEL
Manual &
Automatic
CLK Select
STATUS_REF/
PRI_SEC_CLK
STATUS_VCXO/
I_REF_CP
freq. Detect
> 2 Mhz
PLL_LOCK
freq. Detect
> 2 Mhz
LVCMOS
SEC_REF
R EF_M UX
PRI_REF
Reference
Clock
Feedback
Clock
Progr. Delay
M
Progr. Divider
Progr. Delay
N
Progr. Divider
LOCK
HOLD
PFD
Charge
Pump
10
M 2
N 2
Current
Reference
SPI LOGIC
CTRL_LE
CP_OUT
12
CTRL_DATA
CTRL_CLK
PECL
to
LVCMOS
LV
CMOS
FB_MUX
Y0_MUX
Y0A
PD
RESET or
HOLD
LV
PECL
Y0B
LV
CMOS
LV
CMOS
Y1_MUX
Y1A
÷1
LV
PECL
Y1B
÷2
LV
CMOS
÷3
LV
CMOS
÷4
VCXO_IN
PECL
INPUT
Y2A
Y2_MUX
VCXO_IN
÷6
LV
PECL
Y2B
/8
÷8
LV
CMOS
÷ 16
LV
CMOS
90o 90o
Y3A
Y3_MUX
÷4
÷8
P16-Div
LV
PECL
P Divider
Y3B
LV
CMOS
LV
CMOS
Bias Generator
VCC – 1.3V
Y4A
Y4_MUX
VBB
LV
PECL
Y4B
LV
CMOS
GND
B0057-01
9.3 Feature Description
9.3.1 Automatic/Manual Reference Clock Switching
The CDCM7005 supports two reference clock inputs, the primary clock input, PRI_REF, and the secondary clock
input, SEC_REF. The clocks can be selected manually or automatically. The respective mode is selected by the
dedicated SPI register bit (Word 0, Bit 30).
In the manual mode, the external REF_SEL signal selects one of the two input clocks:
REF_SEL [1] -> primary clock is selected
REF_SEL [0] -> secondary clock is selected
In the automatic mode, the primary clock is selected by default even if both clocks are available. In case the
primary clock is not available or fails, then the input switches to the secondary clock as long until the primary
clock is back. Figure 14 shows the automatic clock selection.
16
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Feature Description (continued)
1
PRI_REF
SEC_REF
1
2
3
4
2
Internal
Reference Clock
STATUS_REF
PRI_SEC_CLK
Secondary Clock
Primary Clock
Primary Clock
T0062-01
NOTE: PRI_REF is the preferred clock input.
Figure 14. Behavior of STATUS_REF and PRI_SEC_CLK
In the automatic mode, the frequencies of both clock signals have to be similar, but may differ by up to 20%. The
phase of the clock signal can be any.
The clock input circuitry is design to suppress glitches during switching between the primary and secondary clock
in the manual and automatic mode. This avoids an undefined switching of the following circuitries.
The phase of the output clock slowly follows the new input phase. There will be no phase-jump at the output.
How quick the phase adjustment is done depends on the selected loop parameter, i.e., at a loop bandwidth of
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