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CDCM9102
SCAS922A – FEBRUARY 2012 – REVISED APRIL 2016
CDCM9102 Low-Noise Two-Channel 100-MHz Clock Generator
1 Features
3 Description
•
The CDCM9102 is a low-jitter clock generator
designed
to
provide
reference
clocks
for
communications standards such as PCI Express™.
The device supports up to PCIE gen3 and is easy to
configure and use. The CDCM9102 provides two
100-MHz differential clock ports. The output types
supported for these ports include LVPECL, LVDS, or
a pair of LVCMOS buffers. HCSL signaling is
supported using an AC-coupled network. The user
configures the output buffer type desired by strapping
device pins. Additionally, a single-ended 25-MHz
clock output port is provided. Uses for this port
include general-purpose clocking, clocking Ethernet
PHYs, or providing a reference clock for additional
clock generators. All clocks generated are derived
from a single external 25-MHz crystal.
1
•
•
•
•
•
•
•
•
Integrated Low-Noise Clock Generator Including
PLL, VCO, and Loop Filter
Two Low-Noise 100-MHz Clocks (LVPECL,
LVDS, or pair of LVCMOS)
– Support for HCSL Signaling Levels
(AC-Coupled)
– Typical Period Jitter: 21 ps pk-pk
– Typical Random Jitter: 510 fs RMS
– Output Type Set by Pins
Bonus Single-Ended 25-MHz Output
Integrated Crystal Oscillator Input Accepts
25-MHz Crystal
Output Enable Pin Shuts Off Device and Outputs
5-mm × 5-mm 32-Pin VQFN Package
ESD Protection Exceeds 2000 V HBM, 500 V
CDM
Industrial Temperature Range (–40°C to 85°C)
3.3-V Power Supply
Device Information(1)
PART NUMBER
CDCM9102
PACKAGE
VQFN (32)
BODY SIZE (NOM)
5.00 mm × 5.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
2 Applications
•
•
Reference Clock Generation for PCI Express
Gen 1, Gen 2, and Gen 3
General-Purpose Clocking
Simplified Schematic
VDD
OUT1P
OUT1N
HCSL input ITTP
HCSL output
OUT2P
OUT2N
OTTP
471 Ÿ
471 Ÿ
100MHz LVPECL
IN1P
25MHz
CDCM9102
CDCUN1208LP
VDD
OUT3P
OUT3N
Up to 8x
OUT4P
OUT4N
100MHz
HCSL
outputs
IN1N
150 Ÿ
150 Ÿ 56 Ÿ
56 Ÿ
OUT8P
OUT8N
Copyright © 2016, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
CDCM9102
SCAS922A – FEBRUARY 2012 – REVISED APRIL 2016
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Device Comparison Table.....................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
3
5
7.1
7.2
7.3
7.4
7.5
7.6
7.7
5
5
5
5
6
7
7
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Timing Requirements ................................................
Typical Characteristics ..............................................
8
Parameter Measurement Information .................. 8
9
Detailed Description ............................................ 10
8.1 Test Configurations ................................................... 8
9.1 Overview ................................................................. 10
9.2 Functional Block Diagrams ..................................... 10
9.3 Feature Description................................................. 10
9.4 Device Functional Modes ....................................... 10
9.5 Programming........................................................... 12
10 Application and Implementation........................ 13
10.1 Application Information.......................................... 13
10.2 Typical Application ................................................ 16
11 Power Supply Recommendations ..................... 19
11.1 Thermal Management ........................................... 19
11.2 Power Supply Filtering .......................................... 19
12 Layout................................................................... 20
12.1 Layout Guidelines ................................................. 20
12.2 Layout Example .................................................... 20
13 Device and Documentation Support ................. 21
13.1
13.2
13.3
13.4
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
21
21
21
21
14 Mechanical, Packaging, and Orderable
Information ........................................................... 21
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Original (February 2012) to Revision A
Page
•
Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section .................................................................................................. 1
•
Added text to Description: The device supports up to PCIE gen3 and is .............................................................................. 1
•
Changed part number to 1134 25M0000000 ....................................................................................................................... 11
•
Changed part number to FP2500002 ................................................................................................................................... 11
•
Added text and Figure 16 to PCI Express Applications ....................................................................................................... 15
2
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SCAS922A – FEBRUARY 2012 – REVISED APRIL 2016
5 Device Comparison Table
PACKAGED DEVICES
FEATURES
TA
CDCM9102RHBT
32-pin VQFN (RHB) package, small tape and reel
–40°C to 85°C
CDCM9102RHBR
32-pin VQFN (RHB) package, tape and reel
6 Pin Configuration and Functions
NC
OSCOUT
GND
XIN
VDD6
REGCAP1
VDD5
REGCAP2
24
23
22
21
20
19
18
17
RHB Package
32-Pin VQFN
(Top View)
NC
25
16
VDD4
NC
26
15
NC
NC
27
14
GND
NC
28
13
NC
GND
8
VDD3
NC
9
7
32
OE
NC
6
OS1
OUT0P
10
5
31
OUT0N
NC
4
OS0
VDD1
11
3
30
OUT1P
NC
2
RESET
OUT1N
12
1
29
VDD2
NC
Pin Functions
PIN
NAME
NO.
TYPE (1)
DESCRIPTION
POWER SUPPLIES
GND
Thermal pad, 14, 22
G
Power supply ground and thermal relief
REGCAP1
19
P
Capacitor for internal regulator, connect 10-μF Y5V capacitor to GND
REGCAP2
17
P
Capacitor for internal regulator, connect 10-μF Y5V capacitor to GND
VDD1
4
P
Power Supply, OUT0 clock port
VDD2
1
P
Power Supply, OUT1 clock port
VDD3
9
P
Power supply, low-noise clock generator
VDD4
16
P
Power supply, low-noise clock generator
VDD5
18
P
Power supply, low-noise clock generator
VDD6
20
P
Power supply, crystal oscillator input
(1)
G = Ground, I = Input, O = Output, P = Power
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Pin Functions (continued)
PIN
NAME
NO.
TYPE (1)
DESCRIPTION
DEVICE CONFIGURATION AND CONTROL
NC
8, 13, 15, 24–32
—
No connection permitted
OE
7
O
Output enable/shutdown control input (see Table 2)
OS1
10
O
Output format select control inputs (see Table 3)
OS0
11
O
Output format select control inputs (see Table 3)
RESET
12
I
Device reset input (active-low) (see Table 4) (2)
21
I
Parallel resonant crystal input (25 MHz)
OSCOUT
23
O
Oscillator output port (25 MHz)
OUT0N
5
O
Output 0 – negative terminal (100 MHz)
OUT0P
6
O
Output 0 – positive terminal (100 MHz)
OUT1N
2
O
Output 1 – negative terminal (100 MHz)
OUT1P
3
O
Output 1 – positive terminal (100 MHz)
CRYSTAL OSCILLATOR
XIN
DEVICE OUTPUTS
(2)
4
For proper device startup, it is recommended that a capacitor be installed from pin 12 to GND. See Start-Up Time Estimation for more
details.
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
MAX
UNIT
20
mA
50
mA
4.6
V
IIN
Input current
IOUT
Output current
VDDx
Supply voltage (2)
–0.5
VIN
Input voltage (3)
–0.5
VDDx + 0.5
V
–0.5
VDDx + 0.5
V
85
°C
150
°C
(3)
VOUT
Output voltage
TA
Operating temperature
Tstg
Storage temperature
(1)
(2)
(3)
–65
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Supply voltages must be applied simultaneously.
The input and output negative voltage ratings may be exceeded if the input and output clamp–current ratings are observed
7.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001
Electrostatic discharge
(1)
UNIT
±2000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
V
±500
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
VDDX
DC power-supply voltage
TA
Ambient temperature
MIN
NOM
MAX
3
3.3
3.6
V
85
°C
–40
UNIT
7.4 Thermal Information
CDCM9102
THERMAL METRIC (1) (2)
RHB (VQFN)
UNIT
32 PINS
RθJA
Junction-to-ambient thermal resistance
33.1
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
25.7
°C/W
RθJB
Junction-to-board thermal resistance
0.3
°C/W
ψJT
Junction-to-top characterization parameter
7.1
°C/W
ψJB
Junction-to-board characterization parameter
2
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
6.12
°C/W
(1)
(2)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
4 × 4 Vias on Pad.
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7.5 Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
PARAMETER
LVCMOS INPUTS
TEST CONDITIONS
MIN
TYP
MAX
UNIT
(1)
VIH
Input high voltage
VIL
Input low voltage
0.6 × VDD
IIH
Input high current
VDD = 3.6 V, VIL = 0 V
IIL
Input low current
VDD = 3 V, VIH = 3.6 V
CIN
Input capacitance
RPU
Input pullup resistor
V
8
0.4 × VDD
V
200
µA
–200
µA
10
pF
150
kΩ
25
MHz
CRYSTAL CHARACTERISTICS (XIN) (2)
fXTAL
Crystal input frequency
ESR
Effective series resistance of
crystal
CIN
On-chip load capacitance
XTALDL
Maximum drive level - XTAL
CSHUNT
Maximum shunt capacitance
Fundamental mode
50
8
VOH
Output high voltage
VOL
Output low voltage
|VOD|
Differential output voltage
tR and tF
Output rise and fall time
ODC
Output duty cycle
tSKEW
Skew between outputs
Differential output voltage
ΔVOD
VOD magnitude change
VOS
Common-mode voltage
ΔVOS
VOS magnitude change
tR and tF
Output rise and fall time
ODC
Output duty cycle
tSKEW
Skew between outputs
pF
1
mW
7
pF
VDD – 1.18
VDD – 0.73
V
VDD – 2
VDD – 1.55
V
0.6
1.23
V
175
ps
(3)
20% to 80%
45%
55%
20
CLOCK OUTPUT BUFFER (OUTPUT MODE = LVDS)
|VOD|
10
0.1
CLOCK OUTPUT BUFFER (OUTPUT MODE = LVPECL)
Ω
ps
(4)
0.247
0.454
50
1.125
20% to 80%
45%
1.375
V
mV
V
50
mV
255
ps
55%
30
ps
CLOCK OUTPUT BUFFER (OUTPUT MODE = LVCMOS) (5)
VOH
Output high voltage
VCC = 3 V to 3.6 V, IOH = –100 µA
VOL
Output low voltage
VCC = 3 V to 3.6 V, IOH = 100 µA
tSLEW
Output rise/fall slew rate
20% to 80%
ODC
Output duty cycle
tSKEW
Skew between outputs
(1)
(2)
(3)
(4)
(5)
6
VDD – 0.5
V
0.3
2.4
45%
V
V/ns
55%
50
ps
LVCMOS inputs at TA = –40°C to 85°C
Crystal characteristics for external 25 MHz crystal with VDD = 3.3 V, TA = –40°C to 85°C
Clock output buffer with output mode = LVPECL at VDD1, VDD2 = 3.3 V; TA = –40°C to 85°C
Clock output buffer with output mode = LVDS at VDD1, VDD2 = 3.3 V; TA = –40°C to 85°C
Clock output buffer with output mode = LVCMOS at VDD1, VDD2 = 3.3 V; TA = –40°C to 85°C
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7.6 Timing Requirements
fOUT = 100 MHz, VDD = 3.3 V, TA = 25°C, and jitter integration bandwidth between 10 kHz and 20 MHz (unless otherwise
noted)
MIN
TYP
MAX
UNIT
LVCMOS OUTPUT MODE
Random jitter
507
fs RMS
Period jitter
24.5
ps pk-pk
Random jitter
510
fs RMS
Period jitter
20.7
ps pk-pk
Random jitter
533
fs RMS
Period jitter
26.5
ps pk-pk
LVPECL OUTPUT MODE
LVDS OUTPUT MODE
7.7 Typical Characteristics
Figure 1. CDCM9102 Typical Phase Noise Performance (LVPECL Mode)
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8 Parameter Measurement Information
8.1 Test Configurations
LVCMOS
5 pF
Figure 2. LVCMOS Output Test Load
Phase Noise Analyzer
RF
50 W
LVCMOS
50 W
Figure 3. LVCMOS AC Configuration for Device Test
Oscilloscope
CH1
CH2
50 W
LVPECL
50 W
50 W (2)
VDD - 2 V
Figure 4. LVPECL DC Configuration for Device Test
Phase Noise Analyzer
RF
50 W
LVPECL
150 W (2)
50 W
Figure 5. LVPECL AC Configuration for Device Test
8
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Test Configurations (continued)
Oscilloscope
CH1
CH2
50 W
LVDS
100 W
50 W
Figure 6. LVDS DC Configuration for Device Test
Phase Noise Analyzer
RF
50 W
50 W
LVDS
50 W
50 W
Figure 7. LVDS AC Configuration for Device Test
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9 Detailed Description
9.1 Overview
The CDCM9102 is a high-performance PLL that generates 2 copies of commonly-used reference clocks with less
than 1-ps RMS jitter from a low-cost crystal.
9.2 Functional Block Diagrams
REGCAP1
REGCAP2
Vreg
Vreg
OE
OSCOUT
OUT1P
XO
Low
Noise
Clock
Generator
OUT1N
OUT0P
OUT0N
CDCM9102
RESET
OS1 OS0
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9.3 Feature Description
The CDCM9102 includes an on-chip PLL with an on-chip VCO. The PLL blocks consist of a crystal input
interface, a phase frequency detector (PFD), a charge pump, an on-chip loop filter, and prescaler and feedback
dividers. Completing the CDCM9102 device are the output divider and universal output buffer. The PLL and
output divider are pre-programmed to generate 2 copies of 100 MHz in LVCMOS, LVPECL or LVDS format.
The PLL is powered by on-chip, low-dropout (LDO) linear voltage regulators. The regulated supply network is
partitioned such that the sensitive analog supplies are powered from separate LDOs rather than the digital
supplies which use a separate LDO regulator. These LDOs provide isolation for the PLL from any noise in the
external power-supply rail. The REG_CAP1 and REG_CAP2 pins should each be connected to ground by 10-μF
capacitors to ensure stability.
9.4 Device Functional Modes
9.4.1 Crystal Input (XIN) Interface
The CDCM9102 implements a Colpitts oscillator; therefore, one side of the crystal connects to the XIN pin and
the other crystal terminal connects to ground. The device requires the use of a fundamental-mode crystal, and
the oscillator operates in parallel resonance mode. The correct load capacitance is necessary to ensure that the
circuit oscillates properly. The load capacitance comprises all capacitances in the oscillator feedback loop (the
capacitances seen between the terminals of the crystal in the circuit). It is important to account for all sources of
capacitance when calculating the correct value for the external discrete load capacitance shown in Figure 8.
XIN
(Pin 21)
XO
25 MHz
CL
CSTRAY
CPARASITIC
CIN
Figure 8. Configuration of Circuit for CDCM9102 XIN Oscillator
10
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Device Functional Modes (continued)
The CDCM9102 has been characterized with 10-pF parallel-resonant crystals. The input stage of the crystal
oscillator in the CDCM9102 is designed to oscillate at the correct frequency for all parallel-resonant crystals with
low-pull capability and rated with a load capacitance that is equal to the sum of the on-chip load capacitance at
the XIN pin (CIN = 10 pF maximum), crystal stray capacitance, and board parasitic capacitance between the
crystal and XIN pin. To minimize stray and parasitic capacitances, minimize the trace distance routed from the
crystal to the XIN pin and avoid other active traces and active circuitry in the area of the crystal oscillator circuit.
Table 1 lists crystal types that have been evaluated with the CDCM9102.
Table 1. CDCM9102 Crystal Recommendations
MANUFACTURER
PART NUMBER
Vectron
VXC1-1134 25M0000000
Fox
218-3
Saronix
FP2500002
A mismatch of the load capacitance results in a frequency error according to Equation 1.
C
C
Δf
S
S
=
f
2 C +C
2 C +C
Lr
La
O
O
(
) (
)
where
•
•
•
•
•
•
Δƒ is the frequency error required by the application.
f is the fundamental frequency of the crystal.
CS is the motional capacitance of the crystal. This is a parameter in the data sheet of the crystal.
C0 is the shunt capacitance of the crystal. This is a parameter in the data sheet of the crystal.
CLr is the rated load capacitance of the crystal. This is a parameter in the data sheet of the crystal.
CLa is the actual load capacitance implemented on the PCB (CIN + stray capacitance + parasitic capacitance +
CL).
(1)
The difference between the rated load capacitance (from the crystal datasheet) and the actual load capacitance
(CLa = CIN + CL + CSTRAY + CPARASITIC) should be minimized. A crystal with a low pullability rating (low CS) is
ideal.
Design Example:
Desired frequency tolerance Δf ≤ ±80 ppm
Crystal Vendor Parameters:
Intrinsic Frequency Tolerance = ±30 ppm
C0 = 7 pF (shunt capacitance)
CS = 10 fF (motional capacitance)
CLr = 12 pF (load capacitance)
Substituting these parameters into Equation 1 yields a maximum value of CLa = 17 pF to achieve the desired Δf
(±50 ppm). Recall that CLa = CIN + CL + CSTRAY + CPARASITIC = 8 pF + (CL + CSTRAY + CPARASITIC). Ideally, the load
presented to this crystal should be 12 pF; therefore, the sum of (CL + CSTRAY + CPARASITIC) must be less than 9
pF. Stray and parasitic capacitance must be controlled. This is because the Colpitts oscillator is particularly
sensitive to capacitance in parallel with the crystal; therefore, good layout practice is essential. TI recommends
that the designer extract the stray and parasitic capacitance from the printed-circuit board design tool and adjust
CL accordingly to achieve CLr = CLa. In common scenarios, the external load capacitor is often unnecessary;
however, TI recommends that pads be implemented to accommodate an external load capacitor so that the ppm
error can be minimized.
9.4.2 Interfacing between LVPECL and HCSL (PCI Express)
Certain PCI Express applications require HCSL signaling. Because the common-mode voltage for LVPECL and
HCSL are different, applications requiring HCSL signaling must use AC-coupling as shown in Figure 9. The
150-Ω resistors ensure proper biasing of the CDCM9102 LVPECL output stage. The 471-Ω and 56-Ω resistor
network biases the HCSL receiver input stage.
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VDDHCSL
471 W (2)
HCSL
LVPECL
56 W (2)
150 W (2)
CIN = 8 pF (typical), 10 pF (maximum); see Electrical Characteristics.
Figure 9. Interfacing Between LVPECL and HCSL
9.5 Programming
Table 2 and Table 3 list the pin controls and pin configurations of the CDCM9102 output. Table 4 lists the device
reset.
9.5.1 Device Configuration
Table 2. CDCM9102 Pin Control of Output Enable
OE (Pin 7)
MODE
DEVICE CORE
OUTPUT
0
Power down
Power down
Hi-Z
1
Normal
Active
Active
Table 3. CDCM9102 Pin Configuration of Output Type
CONTROL PINS
OUTPUT MODE
OS1 (Pin 10)
OS0 (Pin 11)
0
0
0
1
LVDS, OSCOUT = OFF
1
0
LVPECL, OSCOUT = OFF
1
1
LVPECL, OSCOUT = ON
LVCMOS, OSCOUT = OFF
Table 4. CDCM9102 Device Reset
12
RESET (Pin 12)
OPERATING MODE
DEVICE OUTPUTS
0
Device reset
Hi-Z
0→1
Clock generator calibration
Hi-Z
1
Normal
Active
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10 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
10.1 Application Information
10.1.1 Start-Up Time Estimation
The CDCM9102 contains a low-noise clock generator that calibrates to an optimal operating point at device
power up. To ensure proper device operation, the oscillator must be stable before the low-noise clock generator
calibration procedure. Quartz-based oscillators can take up to 2 ms to stabilize; therefore, TI recommends that
the application ensure that the RESET pin is de-asserted at least 5 ms after the power supply has finished
ramping. This can be accomplished by controlling the RESET pin directly, or by applying a 47-nF capacitor to
ground on the RESET pin (this provides a delay because the RESET pin includes a 150-kΩ pullup resistor.
The CDCM9102 start-up time can be estimated based on parameters defined in Table 5 and graphically shown
in Figure 10.
Table 5. CDCM9102 Start-Up Time Dependencies
PARAMETER
DEFINITION
DESCRIPTION
FORMULA OR METHOD OF DETERMINATION
1
tREF
Reference clock period
The reciprocal of the applied reference
frequency in seconds
tpul
Power-up time (low limit)
Power-supply rise time to low limit of poweron-reset trip point
Time required for power supply to ramp to 2.27 V
tpuh
Power-up time (high limit)
Power supply rise time to high limit of poweron-reset trip point
Time required for power supply to ramp to 2.64 V
trsu
Reference start-up time
After POR releases, the Colpitts oscillator is
enabled. This start-up time is required for the
oscillator to generate the requisite signal
levels for the delay block to be clocked by the
reference input.
500 μs best case and 800 μs worst case (for a crystal
input)
tdelay
Delay time
Internal delay time generated from the
reference clock. This delay provides time for
the reference oscillator to stabilize.
tdelay = 16,384 × tREF = 655 µs
tVCO_CAL
VCO calibration time
VCO calibration time generated from the
reference clock. This process selects the
operating point for the VCO based on the PLL
settings.
tVCO_CAL = 550 × tREF = 22 µs
tPLL_LOCK
PLL lock time
Time requried for PLL to lock within ±10 ppm
of fREF
The PLL settles in 12.5 μs
t REF =
fREF
= 0.04 μs
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Power Up
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Reference
Start-Up
Delay
VCO Calibration
PLL Lock
trsu
tdelay
tVCO_CAL
tPLL_LOCK
2.64
2.27
tpd
Time - (S)
tpuh
Figure 10. CDCM9102 Start-Up Time Dependencies
The CDCM9102 start-up time limits, tMAX and tMIN, can now be calculated with Equation 2 and Equation 3.
tMAX = tpuh + trsu + tdelay + tVCO_CAL + tPLL_LOCK
tMIN = tpul + trsu + tdelay + tVCO_CAL + tPLL_LOCK
(2)
(3)
10.1.2 Output Termination
The CDCM9102 is a 3.3-V clock driver which has the following options for the output type: LVPECL, LVDS, and
LVCMOS.
10.1.3 LVPECL Termination
The CDCM9102 is an open emitter for LVPECL outputs. Therefore, proper biasing and termination is required to
ensure correct operation of the device and to optimize signal integrity. The proper termination for LVPECL is
50 Ω to (Vcc-2) V but this DC voltage is not readily available on a board. Thus a Thevenin’s equivalent circuit is
worked out for the LVPECL termination in both direct-coupled (DC) and AC-coupled cases, as shown in
Figure 11 and Figure 12. TI recommends placing all resistive components close to either the driver end or the
receiver end. If the supply voltages of the driver and receiver are different, AC coupling is required.
VDDOUT
130 W (2)
LVPECL
LVPECL
82 W (2)
Figure 11. LVPECL Output Termination (DC-Coupled)
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Vb
50 W (2)
LVPECL
150 W (2)
Figure 12. LVPECL Output Termination (AC-Coupled)
10.1.4 LVDS Termination
The proper LVDS termination for signal integrity over two 50-Ω lines is 100 Ω between the outputs on the
receiver end. Either a direct-coupled (dc) termination or ac-coupled termination can be used for LVDS outputs,
as shown in Figure 13 and Figure 14. TI recommends placing all resistive components close to either the driver
end or the receiver end. If the supply voltages of the driver and receiver are different, AC coupling is required.
100 W
LVDS
LVDS
Figure 13. LVDS Output Termination (DC Coupled)
100 W
LVDS
Figure 14. LVDS Output Termination (AC Coupling)
10.1.5 LVCMOS Termination
Series termination is a common method to maintain the signal integrity for LVCMOS drivers, if connected to a
receiver with a high-impedance input. For series termination, a series resistor, Rs, is placed close to the driver,
as shown in Figure 15. The sum of the driver impedance and Rs should be close to the transmission-line
impedance, which is usually 50 Ω. Because the LVCMOS driver in the CDCM9102 has an impedance of 30 Ω, TI
recommends Rs be 22 Ω to maintain proper signal integrity.
LVCMOS
LVCMOS
22 W
Figure 15. LVCMOS Output Termination
10.1.6 PCI Express Applications
Texas Instruments offers a complete clock solution for PCI Express applications. The CDCUN1208LP can be
used to fan out reference clock generated by the CDCM9102 as shown in Figure 16.
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VDD
OUT1P
OUT1N
HCSL input
HCSL output
ITTP
OUT2P
OUT2N
OTTP
VDD
471Q
100MHz LVPECL
IN1P
25MHz
CDCM9102
IN1N
150Q
150Q
56Q
56Q
CDCUN1208LP
471Q
OUT3P
OUT3N
Up to 8x
OUT4P
OUT4N
100MHz
HCSL
outputs
OUT8P
OUT8N
Figure 16. Clock Solution for PCIE Express Applications
10.2 Typical Application
25 MHz
XO
25 MHz
Low
Noise
Clock
Generator
PCLe
100 MHz
PCLe
100 MHz
CDCM9102
Copyright © 2016, Texas Instruments Incorporated
Figure 17. CDCM9102 Typical Application Example
10.2.1 Design Requirements
Consider a typical wired communications application, like a top-of-rack switch, which needs to clock PCI Express
Gen 2 or 3 PHYs. For such asynchronous systems, the reference input can be a crystal. In such systems, the
clocks are expected to be available upon power up without the need for any device-level programming. An
example of clock input and output requirements is shown below:
• Clock Input:
– 25-MHz crystal
• Clock Outputs:
– 2× 100 MHz clock for PCI Express Gen 3 (8 GT/s), LVPECL
See Detailed Design Procedure for how to generate the required output frequencies for this application using the
CDCM9102.
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Typical Application (continued)
10.2.2 Detailed Design Procedure
Design of all aspects of the CDCM61004 is quite involved and software support is available to assist in part
selection and phase noise simulation. This design procedure will give a quick outline of the process.
1. Device Selection
– The first step is to calculate the VCO frequency given the required output frequency. The device must be
able to produce the VCO frequency that can be divided down to the required output frequency.
– The WEBENCH Clock Architect Tool from TI will aid in the selection of the right device that meets the
customer's output frequencies and format requirements.
2. Device Configuration
– The WEBENCH Clock Architect Tool attempts to maximize the phase detector frequency, use smallest
dividers, and maximizes PLL bandwidth.
10.2.2.1 Device Selection
Use the WEBENCH Clock Architect Tool. Enter the required frequencies and formats into the tool. To use this
device, find a solution using the CDCM9102.
10.2.2.1.1 Calculation Using LCM
In this example, the valid VCO frequency for CDCM9102 is 1.8 GHz.
10.2.2.2 Device Configuration
For this example, when using the WEBENCH Clock Architect Tool, the reference would have been manually
entered as 25 MHz according to input frequency requirements. Enter the desired output frequencies and click on
Generate Solutions. Select CDCM9102 from the solution list.
From the simulation page of the WEBENCH Clock Architect Tool, it can be seen that to maximize phase detector
frequencies, the N divider is set to 24 and prescaler divider is set to 3. This results in a VCO frequency of
1.8 GHz. The output divider is set to 6. At this point the design meets all input and output frequency
requirements and simulate performance on the clock outputs. Figure 18 shows the typical phase noise plot of the
100 MHz LVPECL output.
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Typical Application (continued)
10.2.3 Application Curve
Figure 18. Typical Phase Noise Plot of 100 MHz LVPECL Output
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11 Power Supply Recommendations
TA = –40°C to 85°C, VDDx = 3.3 V, OE = 1, values represent cumulative current/power on all VDDx pins.
Table 6. Device Current Consumption
BLOCK
CONDITION
Entire device,
core current
LVPECL
Output Buffers
LVDS
LVCMOS
CURRENT (mA)
DEVICE POWER (mW)
85
280
28
42.4
20
66
V × ƒout × (CL + 20 × 10–12) × 103
V2 × ƒout × (CL + 20 × 10–12) × 103
EXTERNAL
RESISTOR
POWER (mW)
50
11.1 Thermal Management
To ensure optimal performance and reliability, good thermal design practices are important when using the
CDCM9102. Die temperature should be limited to a maximum of 125°C. That is, as an estimate, TA (ambient
temperature) plus device power consumption times RθJA should not exceed 125°C.
The device package has an exposed pad that provides the primary heat removal path as well as an electrical
grounding to the printed circuit board (PCB). To maximize the removal of heat from the package, a thermal
landing pattern including multiple vias to a ground plane must be incorporated on the PCB within the footprint of
the package. The exposed pad must be soldered down to ensure adequate heat conduction out of the package.
A recommended land and via pattern is shown in Figure 19.
5.0 mm,min
0.33 mm, typ
2.1 mm, typ
Figure 19. Recommended PCB Layout for CDCM9102
11.2 Power Supply Filtering
PLL-based frequency synthesizers are very sensitive to noise on the power supply, which can dramatically
increase the jitter of the PLL. This is especially true for analog-based PLLs. Thus, it is essential to reduce noise
from the system power supply, especially when jitter/phase noise is very critical to applications. A PLL has
attenuated jitter due to power supply noise at frequencies beyond the PLL bandwidth due to attenuation by the
loop response.
Filter capacitors are used to eliminate the low-frequency noise from the power supply, where the bypass
capacitors provide the very low-impedance path for high-frequency noise and guard the power supply system
against induced fluctuations. The bypass capacitors also provide a source of instantaneous current as required
by the device output stages. Therefore, bypass capacitors must have low ESR. To properly use the bypass
capacitors, they must be placed very close to the power supply pins and must be laid out with short loops to
minimize inductance.
Figure 20 shows a general recommendation for decoupling the power supply. The CDCXM9102 power supplies
fall into one of two categories: analog supplies (VDD3, VDD4, and VDD5), and input/output supplies (VDD1,
VDD2, and VDD6). Short the analog supplies together to form the analog supply node; likewise, short the
input/output supplies together to form the I/O supply node. Isolate the analog node from the PCB power supply
and I/O node by inserting a ferrite bead. This helps isolate the high-frequency switching noises generated by the
clock drivers and I/O from the sensitive analog supply node. Choosing an appropriate ferrite bead with low dc
resistance is important, as it is imperative to maintain a voltage at the power-supply pin of the CDCM9102 that is
over the minimum voltage needed for its proper operation.
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Power Supply Filtering (continued)
PCB
Supply
Analog Node
I/O Node
Ferrite Bead
0.1 µF
(´3)
10 µF
10 µF
0.1 µF
(´3)
Figure 20. CDCM9102 Power Supply Decoupling – Power Pin Bypass Concept
12 Layout
12.1 Layout Guidelines
The CDCM9102 is a high-performance device; therefore, pay careful attention to device configuration and
printed-circuit board layout with respect to power consumption. Observing good thermal layout practices enables
the thermal pad on the backside of the 32-pin VQFN package to provide a good thermal path between the die
contained within the package and the ambient air. This thermal pad also serves as the ground connection the
device; therefore, a low inductance connection to the ground plane is essential.
12.2 Layout Example
Figure 21 shows a general recommendation of PCB layout with the CDCM9102 that ensures good system-level
thermal reliability.
Back Side
Component Side
QFN-32
Solder Mask
Thermal Slug
(package bottom)
Internal
Ground
Plane
Internal
Power
Plane
Thermal
Dissipation
Pad (back side)
Thermal Vias
No Solder Mask
Figure 21. Recommended PCB Layout
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13 Device and Documentation Support
13.1 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
13.2 Trademarks
E2E is a trademark of Texas Instruments.
PCI Express is a trademark of PCI-SIG.
All other trademarks are the property of their respective owners.
13.3 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
13.4 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
14 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
CDCM9102RHBR
ACTIVE
VQFN
RHB
32
3000
RoHS & Green
NIPDAUAG
Level-2-260C-1 YEAR
-40 to 85
CDCM
9102
CDCM9102RHBT
ACTIVE
VQFN
RHB
32
250
RoHS & Green
NIPDAUAG
Level-2-260C-1 YEAR
-40 to 85
CDCM
9102
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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