CDCS503TPWRQ1

CDCS503-Q1 www.ti.com SCAS924B – MARCH 2012 – REVISED JUNE 2012 Clock Buffer/Clock Multiplier With Optional SSC Check for Samples: CDCS503-Q1 FEATURES 1 • • • • • • Qualified for Automotive Applications AEC-Q100 Test Guidance With the Following Results: – Device Temperature Grade 2 – -40°C to 105°C Ambient Operating Temperature Range – Device HBM ESD Classification Level H2 – Device CDM ESD Classification Level C3B Part of a Family of Easy to Use Clock Generator Devices With Optional Spread Spectrum Clocking (SSC) Clock Multiplier With Selectable Output Frequency and Selectable SSC SSC Controllable Through Two External Pins – ±0%, ±0.5%, ±1%, ±2% Center Spread Frequency Multiplication Selectable Between x1 or x4 With One External Control Pin VDD IN SSC_SEL 0 SSC_SEL 1 FS LVCMOS • • • • Output Disable Through Control Pin Single 3.3 V Device Power Supply Wide Temperature Range –40°C to 105°C Low Space Consumption 8-Pin TSSOP Package APPLICATIONS • Automotive Applications Requiring EMI Reduction Through SSC and/or Clock Multiplication IN SSC_SEL 0 SSC_SEL 1 GND 1 2 3 4 CDCS503-Q1 8 7 6 5 VDD OE OUT FS GND x1 or x4 / SSC LV CMOS OUT Control Logic OE Figure 1. BLOCK DIAGRAM 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2012, Texas Instruments Incorporated CDCS503-Q1 SCAS924B – MARCH 2012 – REVISED JUNE 2012 www.ti.com DESCRIPTION The CDCS503-Q1 device is a spread spectrum capable, LVCMOS input clock buffer with selectable frequency multiplication. It shares major functionality with the CDCS502 but uses a LVCMOS input stage instead of the crystal input stage of the CDCS502, and the CDCS503-Q1 has an output enable pin. The device accepts a 3.3-V LVCMOS signal at the input. The input signal is processed by a phased-locked loop (PLL), whose output frequency is either equal to the input frequency or multiplied by the factor of four. The PLL is also able to spread the clock signal by ±0%, ±0.5%, ±1% or ±2% centered around the output clock frequency with a triangular modulation. By this, the device can generate output frequencies between 8 MHz and 108 MHz with or without SSC. A separate control pin can be used to enable or disable the output. The CDCS503-Q1 device operates in a 3.3-V environment. It is characterized for operation from –40°C to 105°C, and available in an 8-pin TSSOP package. Table 1. FUNCTION TABLE 2 OE FS SSC_SEL 0 SSC_SEL 1 SSC AMOUNT fOUT/fIN 0 x x x x x fOUT at fin = 27 MHz 3-state 1 0 0 0 ±0.00% 1 27 MHz 1 0 0 1 ±0.50% 1 27 MHz 1 0 1 0 ±1.00% 1 27 MHz 1 0 1 1 ±2.00% 1 27 MHz 1 1 0 0 ±0.00% 4 108 MHz 1 1 0 1 ±0.50% 4 108 MHz 1 1 1 0 ±1.00% 4 108 MHz 1 1 1 1 ±2.00% 4 108 MHz Copyright © 2012, Texas Instruments Incorporated CDCS503-Q1 www.ti.com SCAS924B – MARCH 2012 – REVISED JUNE 2012 This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. DEVICE INFORMATION PACKAGE IN SSC_SEL 0 SSC_SEL 1 GND 1 2 3 4 CDCS503-Q1 8 7 6 5 VDD OE OUT FS PIN FUNCTIONS SIGNAL PIN TYPE DESCRIPTION IN 1 I LVCMOS clock input OUT 6 O LVCMOS clock output SSC_SEL 0, 1 2, 3 I Spread selection pins, internal pullup OE 7 I Output enable, internal pullup FS 5 I Frequency multiplication selection, internal pullup VDD 8 Power 3.3-V power supply GND 4 Ground Ground ORDERING INFORMATION TA PACKAGE –40°C to 105°C TSSOP ORDERABLE PART NUMBER TOP-SIDE MARKING CDCS503TPWRQ1 CS503Q 2000 PACKAGE THERMAL RESISTANCE FOR TSSOP (PW) PACKAGE over operating free-air temperature range (unless otherwise noted) (1) THERMAL AIRFLOW (CFM) PW 8-PIN TSSOP RθJA RθJC (1) 0 150 250 500 High K 149 142 138 132 Low K 230 185 170 150 High K 65 Low K 69 UNIT °C/W °C/W The package thermal impedance is calculated in accordance with JESD 51 and JEDEC2S2P (high-k board). THERMAL INFORMATION THERMAL METRIC (1) CDCS503TPWRQ1 PW (8 PINS) θJA Junction-to-ambient thermal resistance θJCtop Junction-to-case (top) thermal resistance 64.9 θJB Junction-to-board thermal resistance 108.7 ψJT Junction-to-top characterization parameter ψJB Junction-to-board characterization parameter 107 θJCbot Junction-to-case (bottom) thermal resistance n/a (1) UNIT 179.9 9 °C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): CDCS503-Q1 3 CDCS503-Q1 SCAS924B – MARCH 2012 – REVISED JUNE 2012 www.ti.com ABSOLUTE MAXIMUM RATINGS (1) over operating free-air temperature range (unless otherwise noted) VALUE UNIT VDD Supply voltage range –0.5 to 4.6 V VIN Input voltage range –0.5 to 4.6 V Vout Output voltage range –0.5 to 4.6 V IIN Input current (VI < 0, VI > VDD) 20 mA Iout Continuous output current 50 mA TST Storage temperature range –65 to 150 °C TJ Maximum junction temperature 125 °C ESD Rating Human-body model (HBM) AEC-Q100 classification level H2 1.5 kV Charged-device model (CDM) AEC-Q100 classification level C3B 750 V (1) 4 Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): CDCS503-Q1 CDCS503-Q1 www.ti.com SCAS924B – MARCH 2012 – REVISED JUNE 2012 RECOMMENDED OPERATING CONDITIONS MIN VDD Supply voltage fIN Input frequency VIL Low-level input voltage LVCMOS VIH High-level input voltage LVCMOS VI Input voltage threshold LVCMOS CL Output load test LVCMOS IOH/IOL Output current TA Operating free-air temperature NOM MAX 3 3.6 FS = 0 8 32 FS = 1 8 27 UNIT V MHz 0.3 VDD V 0.7 VDD V 0.5 VDD –40 V 15 pF ±12 mA 105 °C MAX UNIT DEVICE CHARACTERISTICS over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS fout = 70 MHz; FS = 1, SSC = 2% 22 Device supply current fOUT Output frequency IIH LVCMOS input current VI = VDD; VDD = 3.6 V IIL LVCMOS input current VI = 0 V; VDD = 3.6 V LVCMOS high-level output voltage VOL LVCMOS low-level output voltage mA FS = 0 8 32 FS = 1 32 108 IOH = - 0.1 mA 2.9 IOH = - 8 mA 2.4 IOH = - 12 mA 2.2 μA –10 μA V 0.1 IOL = 8 mA 0.5 IOL = 12 mA 0.8 High-impedance-state output current OE = Low tJIT(C-C) Cycle to cycle jitter (1) fout = 108 MHz; FS = 1, SSC = 1%, 10000 Cycles tr/tf Rise and fall time (1) 20%–80% Odc Output duty cycle (2) fMOD Modulation frequency MHz 10 IOL = 0.1 mA IOZ (1) (2) TYP 19 IDD VOH MIN fout = 20 MHz; FS = 0, no SSC –2 2 110 μA ps 0.75 45% V ns 55% 30 kHz Measured with Test Load, see Figure 3. Not production tested. Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): CDCS503-Q1 5 CDCS503-Q1 SCAS924B – MARCH 2012 – REVISED JUNE 2012 www.ti.com 40 35 IDD - Input Current - mA 30 x4 Mode 25 20 x1 Mode 15 10 5 0 0 5 10 15 20 25 fi - Input Frequency - MHz 30 35 Figure 2. IDD vs Input Frequency, VCC = 3.3 V, SSC = 2%, Output Loaded With Test Load APPLICATION INFORMATION SSC MODULATION The exact implementation of the SSC modulation plays a vital role for the EMI reduction. The CDCS503-Q1 device uses a triangular modulation scheme implemented in a way that the modulation frequency depends on the VCO frequency of the internal PLL and the spread amount is independent from the VCO frequency. The modulation frequency can be calculated by using one of the below formulas chosen by frequency multiplication mode. FS = 0: fmod = fIN / 708 FS = 1: fmod = fIN / 620 PARAMETER MEASUREMENT INFORMATION VDD CDCS503-Q1 1 kW LVCMOS 1 kW 10 pF Figure 3. Test Load 6 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): CDCS503-Q1 CDCS503-Q1 www.ti.com SCAS924B – MARCH 2012 – REVISED JUNE 2012 PARAMETER MEASUREMENT INFORMATION (continued) CDCS503-Q1 LVCMOS LVCMOS Typical Driver Series Termination ~ 18 W Impedance ~ 32 W ZL = 50 W Figure 4. Load for 50-Ω Board Environment Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): CDCS503-Q1 7 CDCS503-Q1 SCAS924B – MARCH 2012 – REVISED JUNE 2012 www.ti.com REVISION HISTORY Changes from Revision A (June 2012) to Revision B • 8 Page Changed AEC Q100 Qualified to AEC Q100 Test Guidance in FAD. .................................................................................. 1 Submit Documentation Feedback Copyright © 2012, Texas Instruments Incorporated Product Folder Link(s): CDCS503-Q1 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) CDCS503TPWRQ1 ACTIVE TSSOP PW 8 2000 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 105 CS503Q (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of