CDCU877ANMKR

CDCU877,, CDCU877A 1.8-V PHASE LOCK LOOP CLOCK DRIVER www.ti.com SCAS688D – JUNE 2005 – REVISED JULY 2007 FEATURES • • • • • • • • 1.8-V Phase Lock Loop Clock Driver for Double Data Rate (DDR II) Applications Spread Spectrum Clock Compatible Operating Frequency: 10 MHz to 400 MHz Low Current Consumption: VDDQ ±50 mA IOK Output clamp current VO < 0 or VO > VDDQ ±50 mA IO Continuous output current VO = 0 to VDDQ Continuous current through each VDDQ or GND Tstg (1) (2) (3) Storage temperature range –65 V ±50 mA ±100 mA 150 °C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed. This value is limited to 2.5 V maximum. Recommended Operating Conditions VCC Output supply voltage, VDDQ Supply Voltage, AVDD MIN NOM MAX 1.7 1.8 1.9 (1) VDDQ UNIT V V VIL Low-level input voltage (2) OE, OS VIH High-level input voltage (2) CK, CK IOH High-level output current (see Figure 2) -9 mA IOL Low-level output current (see Figure 2) 9 mA VIX Input differential-pair cross voltage VI Input voltage level (2) VID Input differential voltage (see Figure 9 ) TA Operating free-air temperature (1) (2) 0.35 x VDDQ 0.65 x VDDQ V V (VDDQ/2) - 0.15 (VDDQ/2) + 0.15 V -0.3 VDDQ + 0.3 V DC 0.3 VDDQ + 0.4 V AC 0.6 VDDQ + 0.4 V -40 85 °C The PLL is turned off and bypassed for test purposes when AVDD is grounded. During this test mode, VDDQ remains within the recommended operating conditions and no timing parameters are specified. VID is the magnitude of the difference between the input level on CK and the input level on CK, see Figure 9 for definition. The CK and CK, VIH and VIL limits define the dc low and high levels for the logic detect state. Submit Documentation Feedback 5 CDCU877,, CDCU877A 1.8-V PHASE LOCK LOOP CLOCK DRIVER www.ti.com SCAS688D – JUNE 2005 – REVISED JULY 2007 Electrical Characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VIK Input VOH High-level output voltage VOL Low-level output voltage IO(DL) Low-level output current, dissabled VOD Differential output voltage (1) II = 18 mA (1) (2) UNIT -1.2 V VDDQ – 0.2 V 1.1 0.1 IOL = 9 mA 1.7 VO(DL) = 100 mV, OE = L 1.7 100 1.7 0.5 μA V ±250 OE, OS, FBIN, FBIN 1.9 ±10 CK and CK = L 1.9 500 CK and CK = 270 MHz. All outputs are open (not connected to a PCB) 1.9 135 All outputs are loaded with 2 pF and 120-Ω termination resistor 1.9 CK, CK FBIN, FBIN CK, CK FBIN, FBIN VI = VDD or GND VI = VDD or GND V 0.6 1.9 Supply current, dynamic (IDDQ + IADD) (see Note (2) for CPD calculation) Change in input current MAX CK, CK Supply current, static (IDDQ + IADD) CI(Δ) 1.7 IOL = 100 μA IDD(LD) Input capacitance 1.7 to 1.9 IOH = –9 mA Input current CI MIN TYP (1) 1.7 IOH = –100 μA II IDD AVDD , VDDQ μA μA mA 235 1.8 2 3 1.8 2 3 1.8 0.25 1.8 0.25 pF VOD is the magnitude of the difference between the true and complimentary outputs. See Figure 9 for a definition. Total IDD = IDDQ + IADD = fCK × CPD × VDDQ, solving for CPD = (IDDQ + IADD)/(fCK × VDDQ) where fCK is the input frequency, VDDQ is the power supply, and CPD is the power dissipation capacitance. Timing Requirements over recommended operating free-air temperature range (unless otherwise noted) (1) PARAMETER fCK Duty cycle, input clock tL Stabiliztion time (3) (4) 6 Clock frequency (application) (1) (3) tDC (1) (2) TEST CONDITIONS Clock frequency (operating) (1) (2) AVDD, VDD = 1.8 V ±0.1 V (4) MIN MAX UNIT 10 400 MHz 160 340 MHz 40% 60% 12 μs The PLL must be able to handle spread spectrum induced skew. Operating clock frequency indicates a range over which the PLL must be able to lock, but in which it is not required to meet the other timing parameters (used for low speed system debug). Application clock frequency indicates a range over which the PLL must meet all timing parameters. Stabilization time is the time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal after power up. During normal operation, the stabilization time is also the time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal when CK and CK go to a logic low state, enter the power-down mode and later return to active operation. CK and CK may be left floating after they have been driven low for one complete clock cycle. Submit Documentation Feedback CDCU877,, CDCU877A 1.8-V PHASE LOCK LOOP CLOCK DRIVER www.ti.com SCAS688D – JUNE 2005 – REVISED JULY 2007 Switching Characteristics over recommended operating free-air temperature range (unless otherwise noted) (see PARAMETER TEST CONDITIONS (1) ) AVDD, VDD = 1.8 V ± 0.1 V MIN TYP MAX UNIT ten Enable time, OE to any Y/Y See Figure 11 8 ns tdis Disable time, OE to any Y/Y See Figure 11 8 ns Cycle-to-cycle period jitter (2) 160 MHz to 190 MHz, see Figure 4 Cycle-to-cycle period jitter (2) 160 MHz to 340 MHz, see Figure 4 t(ω) Static phase offset time (3) t(ω)dyn Dynamic phase offset time tsk(o) Output clock skew See Figure 6 tjit(cc+) tjit(cc-) tjit(cc+) tjit(cc-) tjit(per) VOX 40 0 -40 0 30 0 -30 See Figure 5 -50 50 ps See Figure 10 -15 15 ps 35 ps 160 MHz to 190 MHz, see Figure 7 -30 30 190 MHz to 340 MHz, see Figure 7 -20 20 160 MHz to 190 MHz, see Figure 8 -115 115 190 MHz to 250 MHz, see Figure 8 -70 70 250 MHz to 300 MHz, see Figure 8 -40 40 300 MHz to 340 MHz, see Figure 8 -60 60 Slew rate, OE See Figure 3 and Figure 9 0.5 Input clock slew rate See Figure 3 and Figure 9 1 2.5 4 Output clock slew rate (5) (6) (no load) See Figure 3 and Figure 9 1.5 2.5 3 Period jitter (4) (2) tjit(hper) Half-period jitter (4) (2) SR 0 Output differential-pair cross voltage CDCU877, See Figure 2 (VDDQ/2) 0.1 (VDDQ/2) + 0.1 CDCU877A (8), See Figure 2 (0 - 85°C) (VDDQ/2) 0.1 (VDDQ/2) + 0.1 (7) SSC modulation frequency SSC clock input frequency deviation PLL loop bandwidth (1) (2) (3) (4) (5) (6) (7) (8) 30 33 0% -0.5% 2 ps ps ps ps V/ns V kHz MHz There are two different terminations that are used with the following tests. The load/board in Figure 2 is used to measure the input and output differential-pair cross voltage only. The load/board in Figure 3 is used to measure all other tests. For consistency, equal length cables must be used. This parameter is specifieded by design and characterization. Phase static offset time does not include jitter. Period jitter, half-period jitter specifications are separate specifications that must be met independently of each other. The output slew rate is determined from the IBIS model with a 120-Ω load only. To eliminate the impact of input slew rates on static phase offset, the input skew rates of reference clock input CK and CK and feedback clock inputs FBIN and FBIN are recommended to be nearly equal. The 2.5-V/ns skew rates are shown as a recommended target. Compliance with these typical values is not mandatory if it can adequately shown that alternative characteristics meet the requirements of the registered DDR2 DIMM application. Output differential-pair cross voltage specified at the DRAM clock input or the test load. VOX of CDCU877A is on average 30 mV lower than that of CDCU877 for the same application. Submit Documentation Feedback 7 CDCU877,, CDCU877A 1.8-V PHASE LOCK LOOP CLOCK DRIVER www.ti.com SCAS688D – JUNE 2005 – REVISED JULY 2007 PARAMETER MEASUREMENT INFORMATION VDD CU877 SCOPE GND C = 10 pF Z = 60 W L = 2.97” C = 1 pF Z = 120 W R = 1 MW VTT Z = 60 W L = 2.97” C = 1 pF R = 1 MW C = 10 pF VTT GND Note: VTT = GND Figure 2. Output Load Test Circuit 1 VDD/2 CU877 SCOPE −VDD/2 C = 10 pF Z = 60 W Z = 50 W L = 2.97” R = 10 W Z = 60 W R = 50 W VTT Z = 50 W L = 2.97” R = 10 W R = 50 W C = 10 pF −VDD/2 VTT Note: VTT = GND −VDD/2 Figure 3. Output Load Test Circuit 2 Yx, FBOUT Yx, FBOUT tcycle n tcycle n+1 tjit(cc) = tcycle n − tcycle n+1 Figure 4. Cycle-To-Cycle Period Jitter 8 Submit Documentation Feedback CDCU877,, CDCU877A 1.8-V PHASE LOCK LOOP CLOCK DRIVER www.ti.com SCAS688D – JUNE 2005 – REVISED JULY 2007 PARAMETER MEASUREMENT INFORMATION (continued) tjn tjn+1 Figure 5. Static Phase Offset n=N å1 tj = tjn N (N is the large number of samples) (N > 1000 samples) (1) Figure 6. Output Skew Figure 7. Period Jitter t jit(per) = tcycle n - 1 fO (fO average input frequency measured at CK/CK Submit Documentation Feedback (2) 9 CDCU877,, CDCU877A 1.8-V PHASE LOCK LOOP CLOCK DRIVER www.ti.com SCAS688D – JUNE 2005 – REVISED JULY 2007 PARAMETER MEASUREMENT INFORMATION (continued) Figure 8. Half-Period Jitter t jit(hper) = thalf period n - 1 2 x fO n = any half cycle (fO average input frequency measured at CK/CK (3) 80% 80% VID, VOD Clock Inputs and Outputs, OE 20% 20% tr(i), tr(o) tf(i), tf(o) Figure 9. Input and Output Slew Rates slrr(i/o) = V80% - V20% tr(i/o) slrf(i/o) = V80% - V20% t f(i/o) (4) tj tj tjdyn tjdyn tjdyn Figure 10. Dynamic Phase Offset 10 Submit Documentation Feedback tjdyn CDCU877,, CDCU877A 1.8-V PHASE LOCK LOOP CLOCK DRIVER www.ti.com SCAS688D – JUNE 2005 – REVISED JULY 2007 PARAMETER MEASUREMENT INFORMATION (continued) Figure 11. Time Delay Between OE and Clock Output (Y, Y) RECOMMENDED AVDD FILTERING Bead 0603 CARD VIA AV DD V DDQ 1W 4.7 mF 1206 0.1 mF 0603 2200 pF 0603 PLL GND AGND CARD VIA A. Place the 2200-pF capacitor close to the PLL. B. Use a wide trace for the PLL analog power and ground. Connect PLL and capacitors to AGND trace and connect trace to one GND via (farthest from the PLL). C. Recommended bead: Fair-Rite PN 2506036017Y0 or equilvalent (0.8 Ω dc maximum, 600 Ω at 100 MHz). Figure 12. Recommended AVDD Filtering Submit Documentation Feedback 11 PACKAGE OPTION ADDENDUM www.ti.com 26-May-2021 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) CDCU877ANMKR ACTIVE NFBGA NMK 52 1000 RoHS & Green SNAGCU Level-3-260C-168 HR -40 to 85 CDCU877A CDCU877ANMKT ACTIVE NFBGA NMK 52 250 RoHS & Green SNAGCU Level-3-260C-168 HR -40 to 85 CDCU877A CDCU877ARHAR ACTIVE VQFN RHA 40 2500 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 CDCU877A CDCU877ARHARG4 ACTIVE VQFN RHA 40 2500 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 CDCU877A CDCU877ARHAT ACTIVE VQFN RHA 40 250 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 CDCU877A CDCU877RHAR ACTIVE VQFN RHA 40 2500 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 CDCU877 CDCU877RHARG4 ACTIVE VQFN RHA 40 2500 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 CDCU877 CDCU877RHAT ACTIVE VQFN RHA 40 250 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 CDCU877 CDCU877RHATG4 ACTIVE VQFN RHA 40 250 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 CDCU877 CDCU877RTBR ACTIVE VQFN RHA 40 2500 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 CDCU877 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of