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CDCUN1208LP
SCAS928D – MAY 2012 – REVISED APRIL 2019
CDCUN1208LP 400-MHz Low Power 2:8 Fan-Out Buffer With
Universal Inputs and Outputs
1 Features
3 Description
•
•
The CDCUN1208LP is a 2:8 fan-out buffer featuring a
wide operating supply range, two universal
differential/single-ended inputs, and universal outputs
(HCSL, LVDS, or LVCMOS) with edge-rate control.
The clock buffer supports PCIe Gen1, Gen2 and
Gen3. One of the device inputs includes a divider that
provides divide values of /1, /2, /4, or /8. The
CDCUN1208LP is offered in a 32-pin QFN package,
reducing the solution footprint. The device is flexible
and easy to use. The state of certain pins determines
device configuration at power up. Alternately, the
CDCUN1208LP provides a SPI/I2C port with which a
host processor controls device settings. The
CDCUN1208LP delivers excellent additive jitter
performance, and low power consumption. The
output section includes four dedicated supply pins
enabling the operation of output ports from different
power supply domains. This provides the ability to
clock devices switching at different LVCMOS levels
without the need for external logic level translation
circuitry.
1
•
•
•
•
•
•
•
Supports PCIe Gen1, Gen2, Gen3
Configuration Options (Through Pins or SPI/I2C):
– Input Type (HCSL, LVDS, LVCMOS)
– Output Type (HCSL, LVDS, LVCMOS)
– Signal Edge Rate (Slow, Medium, Fast)
– Clock Input Divide Value (/1, /2, /4, /8) – IN2
Only
Low-Power Consumption and Power Management
Features, Including 1.8-V Operation and Output
Enable Control
Integrated Voltage Regulators to Improve PSNR
Excellent Additive Jitter Performance
– 200 fs RMS (10 kHz to 20 MHz), LVDS at
100 MHz
– 160 fs RMS (10 kHz to 20 MHz), HCSL at
100 MHz
Maximum Operating Frequency:
– Differential Mode: up to 400 MHz
– LVCMOS Mode: up to 250 MHz
ESD Protection Exceeds 2-kV HBM, 500-V CDM
Industrial Temperature Range (–40°C to 85°C)
Wide Supply Range (1.8 V, 2.5 V, or 3.3 V)
Device Information(1)
PART NUMBER
CDCUN1208LP
Communications and Computing Systems
Factory Automation and Control
Medical Imaging
Pro Audio, Video and Signage
Motor Drives
BODY SIZE (NOM)
5.00 mm × 5.00 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
2 Applications
•
•
•
•
•
PACKAGE
VQFN (32)
Pin Configuration Overview
VDD
IN2
AUTO
NC
INSEL
IN1
VDD
HCSL
VDD
OTTP
LVCMOS
NC
HCSL
LVCMOS
NC
LVDS
ITTP
LVDS
OUT1P
IN1P
OUT1N
INMUX
IN1N
IN2P
IN2N
OUT2P
OUT2N
/1,/2,/4,/8
~
~
~ ~
~
~
VDD
NC
/1
/4
OUT8P
DIVIDE
OUT8N
/2
OE
VDD
MODE (PINS)
Medium
CDCUN1208LP
ERC
Fast
NC
Slow
Copyright © 2017, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
CDCUN1208LP
SCAS928D – MAY 2012 – REVISED APRIL 2019
www.ti.com
Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
4
6
6.1
6.2
6.3
6.4
6.5
Absolute Maximum Ratings ...................................... 6
ESD Ratings.............................................................. 6
Recommended Operating Conditions....................... 6
Thermal Information .................................................. 7
Digital Input Electrical Characteristics – OE (SCL),
INSEL, ITTP, OTTP, Divide (SDA/MOSI),
ERC(ADDR/CS), Mode .............................................. 7
6.6 Universal Input (IN1, IN2) Characteristics ............... 8
6.7 Clock Output Buffer Characteristics (Output Mode =
LVDS)......................................................................... 9
6.8 Clock Output Buffer Characteristics (Output Mode =
HCSL) ...................................................................... 10
6.9 Clock Output Buffer Electrical Characteristics (Output
Mode = LVCMOS).................................................... 11
6.10 Clock Output Buffer Electrical Characteristics
(Output Mode = LVCMOS) (Continued)................... 12
6.11 Clock Output Buffer Electrical Characteristics
(Output Mode = LVCMOS) (Continued)................... 13
6.12 Typical Characteristics .......................................... 16
7
Parameter Measurement Information ................ 18
7.1 Test Configurations ................................................. 18
8
Detailed Description ............................................ 22
8.1
8.2
8.3
8.4
8.5
8.6
9
Overview .................................................................
Functional Block Diagrams .....................................
Feature Description.................................................
Device Functional Modes........................................
Programming...........................................................
Register Maps .........................................................
22
22
23
28
30
37
Application and Implementation ........................ 39
9.1 Application Information............................................ 39
9.2 Typical Application .................................................. 39
9.3 Systems Examples.................................................. 41
10 Power Supply Recommendations ..................... 42
10.1 CDCUN1208LP Power Consumption ................... 42
10.2 Device Power Supply Connections and
Sequencing .............................................................. 42
10.3 Device Inputs (IN1, IN2)........................................ 43
11 Layout................................................................... 44
11.1 Layout Guidelines ................................................. 44
11.2 Layout Example .................................................... 44
12 Device and Documentation Support ................. 45
12.1
12.2
12.3
12.4
12.5
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
45
45
45
45
45
13 Mechanical, Packaging, and Orderable
Information ........................................................... 45
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision C (March 2017) to Revision D
Page
•
Changed applications list........................................................................................................................................................ 1
•
Added type descriptions to the Pin Functions table ............................................................................................................... 4
•
Changed input voltage maximum from: VDDx + 0.5 to: VDD + 0.5 in the Absolute Maximum Ratings table......................... 6
•
Added the junction temperature range to the Absolute Maximum Ratings table ................................................................... 6
•
Changed the output current unit from mA °C to mA and moved the °C unit to the storage temperature parameter in
the Absolute Maximum Ratings table ..................................................................................................................................... 6
•
Added note on VDD and VDDOx supply voltages ...................................................................................................................... 6
•
Added text "Pull ADDR to GND for I2C communication" to the CDCUN1208LP Host Configuration Pins table................. 29
•
Changed SPI Message Format graphic to correct SCS timing. ........................................................................................... 30
•
Changed CDCUN1208LP Device Addressing - SPI Mode graphic to correct SCS timing. ................................................. 30
•
Changed SPI Timing Diagram graphic to correct SDI.......................................................................................................... 31
•
Changed t3 in SPI Timing Specifications table to "SDI to SCL hold time" ........................................................................... 32
•
Changed t8 in SPI Timing Specifications table to "SCL falling edge to SCS release time" ................................................. 32
•
Changed I2C address to 7b'0101000 in CDCUN1208LP I2C Message - Addressing graphic ............................................. 34
•
Changed description to reflect that the I2C address is 7b'0101000 in CDCUN1208LP Device Addressing (I2C
Address) section ................................................................................................................................................................... 34
•
Added content to the Application Information section ......................................................................................................... 39
2
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Changes from Revision B (July 2013) to Revision C
Page
•
Changed Added Device Information Table, ESD Ratings tableApplication and Implementation; Power Supply
Recommendations; Layout; Device and Documentation Support; Mechanical, Packaging, and Ordering Information . ...... 1
•
Added ΔV/ΔT2 to the Recommended Operating Conditions table. ........................................................................................ 6
•
Added text "note that CDCUN1208LP supports only single-device" to the first paragraph of SPI Communication. ........... 30
•
Added text "At no time should the clock be toggled while SCS is high. CDCUN1208LP should always be used in
single-slave SPI configuration." to Writing to the CDCUN1208LP. ...................................................................................... 31
•
Added text "At no time should the clock be toggled while SCS is high. CDCUN1208LP should always be used in
single-slave SPI configuration." to Reading From the CDCUN1208LP. .............................................................................. 31
Changes from Revision A (January 2013) to Revision B
Page
•
Added slew rate note to Recommended Operating Conditions. ............................................................................................ 6
•
Changed VIOPEN1.8 from 0.9 V to 0.75 V in Digital Input Electrical Characteristics – OE (SCL), INSEL, ITTP, OTTP,
DIVIDE (SDA/MOSI), ERC(ADDR/CS), Mode. ...................................................................................................................... 7
•
Changed Fast to Medium and Medium to Fast in Figure 28................................................................................................ 24
Changes from Original (May 2012) to Revision A
Page
•
Added Feature:160 fs RMS (10kHz-20MHz), HCSL at 100MHz............................................................................................ 1
•
Added Features: Support PCIE gen1, gen2, gen3................................................................................................................. 1
•
Added text to the Description: "The clock buffer supports PCIE gen1, gen2 and gen3." ...................................................... 1
•
Added text to the Clock Output Buffer Characteristics table: "Supporting PCIe gen1, gen2, gen3."................................... 10
•
Changed Table 4 From: DISABLED To: DISABLED in Tri_State ........................................................................................ 25
•
Changed Table 11 From: Disabled To: Disabled in Tri_State for OUTx_PD. ..................................................................... 37
•
Added text and Figure 41 to the PCI Express Applications section. ................................................................................... 39
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CDCUN1208LP
SCAS928D – MAY 2012 – REVISED APRIL 2019
www.ti.com
5 Pin Configuration and Functions
RHB Package
VQFN 32-Pin
Top View
OUT6N
OUT6P
VDDO3
OUT5N
OUT5P
OTTP
OUT4N
OUT4P
24
23
22
21
20
19
18
17
OUT7P
25
16
OUT3N
OUT7N
26
15
OUT3P
VDDO4
27
14
VDDO2
OUT8P
28
13
OUT2N
OUT8N
MODE
29
12
OUT2P
30
11
VDDO1
ERC
31
10
OUT1N
OE
32
9
OUT1P
UN1208LP
GND
(thermal pad )
5
6
7
8
IN2P
IN2N
ITTP
INSEL
DIVIDE
4
VDD
2
IN1N
IN1P
1
3
Pin Functions (1)
PIN
NAME
NO.
TYPE
DESCRIPTION
Thermal
Pad
Power
DIVIDE
1
Input
Input divider pin control
(HIGH = /4, LOW = /2, OPEN = /1)
INSEL
2
Input
Input multiplexer control
IN1P
3
Input
Universal input 1 – positive terminal
IN1N
4
Input
Universal input 1 – negative terminal, ground if using IN1 in single-ended mode
VDD
5
Power
IN2P
6
Input
Universal input 2 – positive terminal
IN2N
7
Input
Universal input 2 – negative terminal, ground if using IN2 in single-ended mode
ITTP
8
Input
Input type select (HIGH = HCSL, LOW = LVDS, OPEN = LVCMOS)
OUT1P
9
Output
Output 1 – positive terminal
OUT1N
10
Output
Output 1 – negative terminal
VDDO1
11
Power
Output power supply – OUT1, OUT2
OUT2P
12
Output
Output 2 – positive terminal
OUT2N
13
Output
Output 2 – negative terminal
VDDO2
14
Power
Output power supply – OUT3, OUT4; output bank OUT1 – OUT4 regulator power supply (apply
power if any of OUT1 – OUT4 are needed)
OUT3P
15
Output
Output 3 – positive terminal
OUT3N
16
Output
Output 3 – negative terminal
OUT4P
17
Output
Output 4 – positive terminal
OUT4N
18
Output
Output 4 – negative terminal
GND
(1)
4
Power supply ground and thermal relief
Device power supply; provides power to the input section and clock distribution section. Use a
power supply voltage that corresponds to the switching levels of clock inputs (such as 1.8 V, 2.5 V,
or 3.3 V).
This pin list applies to operation of the device in pin mode. In host mode, certain pins take on an alternate function, as outlined in
Table 8.
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Pin Functions(1) (continued)
PIN
TYPE
DESCRIPTION
NAME
NO.
OTTP
19
Output
Output type select (HIGH = HCSL, LOW = LVDS, OPEN = LVCMOS)
OUT5P
20
Output
Output 5 – positive terminal
OUT5N
21
Output
Output 5 – negative terminal
VDDO3
22
Power
Output power supply - OUT5, OUT6
OUT6P
23
Output
Output 6 – positive terminal
OUT6N
24
Output
Output 6 – negative terminal
OUT7P
25
Output
Output 7 – positive terminal
OUT7N
26
Output
Output 7 – negative terminal
VDDO4
27
Power
Output power supply – OUT7, OUT8 output bank OUT5 – OUT8 regulator power supply (apply
power if any of OUT5 – OUT8 are needed)
OUT8P
28
Output
Output 8 – positive terminal
OUT8N
29
Output
Output 8 – negative terminal
MODE
30
Input
Device control mode select
OPEN = Device configured through pins (pin mode)
HIGH = Device configured through I2C
LOW = Device configured through SPI
Note: For information on control through the serial interface (I2C/ SPI), see Device Control Using
the Host Interface section.
ERC
31
Input
Output edge rate control
HIGH = Medium, LOW = Slow, OPEN = Fast
OE
32
Input
Device output enable
HIGH = Enable, LOW = Disable
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
(1)
Supply voltage (2)
VDDxx
(3)
MIN
MAX
UNIT
–0.5
4.6
V
–0.5
VDD + 0.5
V
–0.5
VDDOx + 0.5
VIN
Input voltage
VOUT
Output voltage (3)
IIN
Input current
20
IOUT
Output current
50
TJ
Junction temperature
Tstg
Storage temperature
(1)
(2)
(3)
V
mA
mA
–65
125
°C
150
°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability.
All supply voltages must be supplied simultaneously
The input and output negative voltage ratings may be exceeded if the input and output clamp–current ratings are observed.
6.2 ESD Ratings
VALUE
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001
V(ESD)
(1)
(2)
Electrostatic discharge
(1)
UNIT
±2000
Charged device model (CDM), per JEDEC specification JESD22C101 (2)
V
±500
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
TA = –40°C TO 85°C
POWER SUPPLIES
MIN
NOM
MAX
UNIT
(1) (2) (3)
VDD
DC power supply - core
1.8-V mode
1.7
1.8
1.9
V
VDDOx
DC power supply - output
1.8-V mode
1.7
1.8
1.9
V
VDD
DC power supply - core
2.5-V mode
2.375
2.5
2.625
V
VDDOx
DC power supply - output
2.5-V mode
2.375
2.5
2.625
V
VDD
DC power supply - core
3.3-V mode
2.97
3.3
3.63
V
VDDOx
DC power supply - output
3.3-V mode
2.97
3.3
3.63
V
Core power supply slew rate
0.4-V to 1.8-V × 0.8 (in all voltage modes)
6500
2
ΔV/ΔT
V/s
TEMPERATURE
TA
(1)
(2)
(3)
6
Free- air temperature
–40
85
°C
For proper device operation, the core power supply voltage (pin 5) must be applied either before the application of any output power
supply, or simultaneously with the application of the output power supplies. The application of an output power supply prior to the
application of the core power supply could result in improper device behavior.
A minimum VDD slew rate of 6500 V/s should be obtained to ensure proper device functionality in pin mode. If the ambient temperature
of the device is > 0°C, the slew rate can be as slow as 5000 V/s. In host mode (I2C/SPI), the VDD slew rate is not limited, if the Reset bit
gets toggled after VDD ramp.
VDD and VDDOx can be operated from different supply voltages. Refer to Configuration of Output Type (OTTP) for more details.
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6.4 Thermal Information
CDCUN1208LP
THERMAL METRIC (1)
RHB Package
UNIT
32 PINS
RθJA
Junction-to-ambient thermal resistance
32.5
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
24.2
°C/W
RθJB
Junction-to-board thermal resistance
6.6
°C/W
ψJT
Junction-to-top characterization parameter
0.3
°C/W
ψJB
Junction-to-board characterization parameter
6.6
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
1.6
°C/W
(1)
For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report.
6.5 Digital Input Electrical Characteristics – OE (SCL), INSEL, ITTP, OTTP, Divide (SDA/MOSI),
ERC(ADDR/CS), Mode
TA = –40°C to 85°C
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
LVCMOS INPUT
VIL1.8
Low-level LVCMOS input voltage
VDD = 1.8 V
VIH1.8
High-level LVCMOS input voltage
VDD = 1.8 V
1.35
0.7
VIOPEN1.8
OPEN-level LVCMOS input voltage
VDD = 1.8 V
0.75
VIL2.5
Low-level LVCMOS input voltage
VDD = 2.5 V
VIH2.5
High-level LVCMOS input voltage
VDD = 2.5 V
1.71
VIOPEN2.5
OPEN-level LVCMOS input voltage
VDD = 2.5 V
1
VIL3.3
Low-level LVCMOS input voltage
VDD = 3.3 V
VIH3.3
High-level LVCMOS input voltage
VDD = 3.3 V
2.3
VIOPEN3.3
OPEN-level LVCMOS input voltage
VDD = 3.3 V
1.3
IIL
Low-level LVCMOS input current
VDD = VDDmax, VILCMOS = 0 V
IIH
High-level LVCMOS input current
VDD = VDDmax, VIHCMOS = 1.9 V
CI
LVCMOS input capacitance
VIK
Digital input clamp voltage
V
1.2
V
0.7
V
V
1.6
V
1
V
V
1.9
V
–120
μA
65
μA
6
VDD = 1.7V, II = –18 mA
pF
–1.2
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6.6 Universal Input (IN1, IN2) Characteristics
VDD = 1.8 V, 2.5 V, 3.3 V, TA = –40°C to 85°C
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
0.008
250
MHz
0.7 × VDD
VDD
V
0.2 × VDD
V
SINGLE-ENDED MODE
fIN1,2
Input frequency
Single ended (1)
VIH
Input voltage - high
250 MHz
VIL
Input voltage - low
250 MHz
DIFFERENTIAL MODE
fINDIFF
Input frequency
|VIN-DIFF|
VCM
Input swing
Input common mode voltage
0.008
400
MHz
VDD = 2.5 V, 3.3 V
0.15
1.6
V
VDD = 1.8 V
V
0.15
1
ITTP = LVDS, VDD = 3.3 V
0.8
2.5
ITTP = LVDS, VDD = 2.5 V, 1.8 V
0.8
VDD – 0.3
–0.15
0.75
ITTP = HCSL
V
GENERAL CHARACTERISTICS
IIH
Input current - high
VDD = 3.63 V, VIH = 3.63 V
IIL
Input current - low
VDD = 3.63 V, VIL = 0 V
ΔV/ΔT
Input edge rate
20%–80%
DCIN
Input duty cycle
CIN
Input capacitance
(1)
8
30
µA
–30
µA
0.75
V/ns
40%
60%
3.5
pF
When using an input in single-ended mode, ground the negative terminal (IN1N and/or IN2N) and drive the positive terminal (IN1P
and/or IN2P).
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6.7 Clock Output Buffer Characteristics (Output Mode = LVDS)
Unless otherwise noted, VDDOX = 1.8 V, 2.5 V, 3.3 V; TA = –40°C to 85°C. See Figure 15, Figure 16, and Figure 17.
PARAMETER
fOUT
TEST CONDITIONS
MIN
Output frequency
TYP
0.008
MAX
UNIT
400
MHz
Output common mode voltage,
VDDOx = 2.5/3.3 V
RL = 100 Ω
Output common mode voltage,
VDDOx = 1.8 V
RL = 100 Ω
|VOD|
Differential output voltage
RL = 100 Ω, single-ended Pk-Pk
250
ΔVOD
Change in magnitude of VOD for
complementary output states
RL = 100 Ω
–50
Vring
Output overshoot and undershoot
Percentage of output amplitude VOD
20%
VOS
Output AC common mode
VIN, DIFF, PP = 0.9 V, RL = 100 Ω, 2 pF
150
fout = 100 MHz, 10k-20M integration bandwidth,
RL = 100 Ω
200
fout = 400 MHz, 10k-20M integration bandwidth,
RL = 100 Ω
180
VCM
TADDJIT
tR/tF
Additive jitter (1)
Output rise/fall time
1.125
ERC = Slow, 20% to 80%, ZL = 100 Ω, 1pF,
VDDOx = 1.8 V
700
ERC = Medium., 20% to 80%, ZL = 100 Ω, 1pF,
VDDOx = 3.3 V
600
ERC = Medium., 20% to 80%, ZL = 100 Ω, 1pF,
VDDOx = 1.8 V
500
50/50 Input duty cycle
ISP
ISN
Output short circuit current (single ended)
Shorted to GND
|IPN|
Output short circuit current (differential)
V
V
550
mV
50
mV
mVP-P
fs, rms
ERC = Fast, 20% to 80%, Z L = 100 Ω, 1 pF
Propagation delay
400
800
Output duty cycle
1.275
0.9
ERC = Slow, 20% to 80%, ZL = 100 Ω, 1pF,
VDDOx = 3.3 V
ODC
TDLYO
1.2
ps
300
45%
55%
–24
24
mA
Complementary outputs shorted together
12
mA
ERC set to high rate. Input tr, tf > 0.6 V/ns, RL = 100 Ω,
VDD = 2.5 V, 3.3 V
3.3
ERC set to high rate. Input tr, tf > 0.6 V/ns, RL = 100 Ω,
VDD = 1.8 V
3.8
ns
tSKEW
Skew between outputs
ERC set to high rate. Input tr, tf > 0.6 V/ns, Equal VDDOx,
RL = 100 Ω
35
tOE
Output enable to stable clock output
Pin mode. fout = 100 MHz, device in active mode with
outputs disabled, OE asserted
20
µs
tPD
PD de-asserted to stable clock output
Host mode, fout = 100 MHz, device in power down mode,
PD de-asserted
20
µs
tPU
Time from power applied to stable clock
output (2)
Pin mode, fout = 100 MHz, OE asserted, measured from
time VDD is valid to stable output.
1
ms
(1)
(2)
50
ps
tRfin = tFfin > 0.6 V/ns.
Parameter depends significantly on power supply design and supply voltage rise time.
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6.8 Clock Output Buffer Characteristics (Output Mode = HCSL)
Unless otherwise noted, VDDOx = 1.8 V, 2.5 V, 3.3 V; TA = –40°C to 85°C. See Figure 18, Figure 19, and Figure 20.
Supporting PCIe Gen1, Gen2, Gen3.
PARAMETER
fOUT
TEST CONDITIONS
Output frequency
(1)
Vmax
Absolute maximum output voltage
Vmin
Absolute minimum output voltage (2)
Single-ended output voltage –
high (3)
VOH
MIN
TYP MAX
UNIT
0.008
400
MHz
1.15
V
See Figure 1
See Figure 1
–0.3
RL = single ended to GND = 50 Ω, CL = 2 pF,
VDDOx = 2.5 V, 3.3 V See Figure 18
600
RL = single ended to GND = 50 Ω, CL = 2 pF,
VDDOx = 1.8 V See Figure 18
550
mV
VOL
Single-ended output voltage – low (3)
RL = single ended to GND = 50 Ω, CL = 2 pF,
See Figure 18
VCROSS
Output crossing point voltage (3)
See Figure 1
VCROSSΔ
VCROSS Total variation (3)
See Figure 2
VRB
Ring back voltage margin (3)
See Figure 3
–100
Time before VRB is Allowed ,
See Figure 3
500
VOS
Output AC common mode
VIN, DIFF, PP = 0.9 V, RL = single ended to GND = 50 Ω,
2 pF
TjitHCSL
Additive jitter, input set to HCSL (5)
TjitLVDS
Additive jitter, input set to LVDS (5)
TSTABLE
(3) (4)
Output rise/fall time (6)
tR/tF
V
250
150
mV
550
mV
140
mV
100
mV
ps
75
125
mVP-P
fOUT = 100 MHz, 10k-20M integration bandwidth.
Differential measurement
380
fs, rms
fOUT = 100 MHz, 10k-20M integration bandwidth.
Differential measurement
280
fs, rms
Slow, +150-mV differential, see Figure 4, VDDOx = 3.3
V
300
Slow, +150-mV differential, see Figure 4, VDDOx = 1.8
V
230
Med., +150-mV differential, see Figure 4, VDDOx = 3.3
V
240
Med., +150-mV differential, see Figure 4, VDDOx = 1.8
V
180
Fast, +150-mV differential, see Figure 4
140
ps
TMRF
Output rise/fall time matching
See Figure 5
ODC
Output duty cycle (7)
Differential measurement, see Figure 6
20%
TDLYO
Propagation delay
ERC set to high rate. Input tr, tf > 0.6 V/ns, VDD = 2.5
V, 3.3 V
3.8
ERC set to high rate. Input tr, tf > 0.6 V/ns, VDD = 1.8 V
4.3
45%
tSKEW
Skew between outputs (8)
Differential Measurement, Input tr, tf > 0.6 V/ns
tOE
Output enable to stable clock output
Pin mode, fout = 100 MHz, device in active mode with
outputs disabled, OE asserted
tPD
PD de-asserted to stable clock
output
tPU
Time from power applied to stable
clock output (9)
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
10
55%
35
50
ns
ps
2
µs
Host mode, fout = 100 MHz, device in power down
mode, PD de-asserted
15
µs
Pin mode, fout = 100 MHz, OE asserted, measured
from time VDD is valid to stable output
1
ms
Single-ended measurement includes overshoot. Measurement is taken at load capacitors CL (see Figure 18).
Single-ended measurement, includes undershoot. Measurement is taken at load capacitors CL (see Figure 18).
Measurement is taken at load capacitors CL (see Figure 18). If VDDOx = 1.8 V, the specified minimum VOH is 550 mV.
TSTABLE is the time the differential clock must maintain a minimum ±150 mV differential voltage after rising/falling edges, before it is
allowed to return into the VRB ±100 mV differential range. See Figure 3.
tRfin = tFfin ≥ 0.6 V/ns.
Measured from –150 mV to +150 mV on the differential waveform. The signal must be monotonic through the measurement region for
rise and fall time. The 300-mV measurement window is centered on the differential zero crossing. Slow is 0.53 V/ns, medium is 1.05
V/ns, and fast is 2.1 V/ns. The PCIe CEM spec. has a window of 0.6 V/ns to 4 V/ns.
Assumes input duty cycle = 50%.
Skew measured between identical output types with identical loads, identical output power supplies, and identical edge rate settings.
Parameter depends significantly on power supply design and supply voltage rise time.
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6.9 Clock Output Buffer Electrical Characteristics (Output Mode = LVCMOS)
Unless otherwise noted, VDDOx as shown in Table sections, TA = –40°C to 85°C. ERC = Fast. For test configurations, see
Figure 21 and Figure 22.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
250
MHz
3.3-V MODE
fout
Output frequency range
0.0008
VDDOx = 2.97 V, IOH = –0.1 mA (All ERC Settings)
VDDOx = 2.97 V, IOH = –5 mA (ERC = SLOW)
VOH
LVCMOS high-level output voltage
VDDOx = 2.97 V, IOH = –8 mA (ERC = MED, FAST)
2.9
V
2.4
V
2.2
V
VDDOx = 2.97 V, IOH = –6 mA (ERC = SLOW)
VDDOx = 2.97 V, IOH = –10 mA (ERC = MED)
VDDOx = 2.97 V, IOH = –12 mA (ERC = FAST)
VDDOx = 2.97 V, IOL = 0.1 mA (All ERC Settings)
VDDOx = 2.97 V, IOL = 5 mA (ERC = SLOW)
VOL
LVCMOS low-level output voltage
VDDOx = 2.97 V, IOL = 8 mA (ERC = MED, FAST)
0.1
V
0.5
V
0.8
V
VDDOx = 2.97 V, IOL = 6 mA (ERC = SLOW)
VDDOx = 2.97 V, IOL = 10 mA (ERC = MED)
VDDOx = 2.97 V, IOL = 12 mA (ERC = FAST)
IOH
LVCMOS high-level output current
IOL
LVCMOS low-level output current
tPLH, tPHL
tSLEW-RATE
VDDOx = 3.3 V, VO = 0.5 V; TA = 25°C
–73
VDDOx = 3.3 V, VO = 1.0 V; TA = 25°C
–64
VDDOx = 3.3 V, VO = 1.65 V; TA = 25°C
–49
VDDOx = 3.3 V, VO = 2.8 V; TA = 25°C
78
VDDOx = 3.3 V, VO = 2.3 V; TA = 25°C
72
VDDOx = 3.3 V, VO = 1.65 V; TA = 25°C
58
ERC = Slow, 20% to 80%, fout = 100 MHz, CL = 8 pF
1.2
Propagation delay
Output rise/fall slew rate
mA
5
ERC = Medium 20% to 80%, fout = 100 MHz, CL = 8 pF
3
ERC = Fast, 20% to 80%, fout = 250 MHz, CL = 8 pF
6
tjitt-add
Additive jitter
tsk(o)
Output skew (1)
odc
Output duty cycle (2), (3)
fOUT = 100 MHz; Pdiv = 1
tOE
Output enable to stable clock output
Pin mode. fout = 100 MHz, device in active mode with
outputs disabled, OE asserted
tPD
PD de-asserted to stable clock output
tPU
Time from power applied to stable clock
output (4)
(1)
(2)
(3)
(4)
mA
fOUT = 100 MHz, 10k-20M integration bandwidth
45%
ns
V/ns
280
fs
90
ps
55%
2
µs
Host mode, fout = 100 MHz, device in power down mode,
PD de-asserted
10
µs
Pin mode, fout = 100 MHz, OE asserted, measured from
time VDD is valid to stable output.
1
ms
The tsk(o) specification is only valid for equal loading with identical edge rates and output supply voltages.
Assumes 50% duty cycle at the input.
odc depends on output rise and fall time (tR/tF).
Parameter depends significantly on power supply design and supply voltage rise time.
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6.10 Clock Output Buffer Electrical Characteristics (Output Mode = LVCMOS) (Continued)
Unless otherwise noted, VDDOx as shown in Table sections, TA = –40°C to 85°C. ERC = Fast. For test configurations, see
Figure 21 and Figure 22.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
250
MHz
2.5-V MODE
fout
Output frequency range
0.0008
VDDOx = 2.375 V, IOH = -0.1 mA (All ERC Settings)
2.2
VDDOx = 2.375 V, IOH = -4 mA (ERC = SLOW)
VOH
LVCMOS high-level output voltage
VDDOx = 2.375 V, IOH = - 6 mA (ERC = MED, FAST)
VDDOx = 2.375 V, IOH = -5 mA (ERC = SLOW)
VDDOx = 2.375 V, IOH = - 8 mA (ERC = MED, FAST)
1.7
V
1.6
V
VDDOx = 2.375 V, IOL = 0.1 mA (All ERC Settings)
VDDOx = 2.375 V, IOH = 4 mA (ERC = SLOW)
VOL
LVCMOS low-level output voltage
VDDOx = 2.375 V, IOH = 6 mA (ERC = MED, FAST)
VDDOx = 2.375 V, IOH = 5 mA (ERC = SLOW)
VDDOx = 2.375 V, IOL = 10 mA (ERC = MED, FAST)
IOH
LVCMOS high-level output current
IOL
LVCMOS low-level output current
tPLH, tPHL
tSLEW-RATE
VDDOx = 2.5 V, VO = 0.5 V; TA = 25°C
–45
VDDOx = 2.5 V, VO = 0.9 V; TA = 25°C
–39
VDDOx = 2.5 V, VO = 1.25 V; TA = 25°C
–32
VDDOx = 2.5 V, VO = 2.0 V; TA = 25°C
50
VDDOx = 2.5 V, VO = 1.65 V; TA = 25°C
47
VDDOx = 2.5 V, VO = 1.25 V; TA = 25°C
40
Propagation delay
Output rise/fall slew rate
0.8
ERC = Medium 20% to 80%, fout = 100 MHz, CL = 8 pF
1.4
tjitt-add
Additive jitter
tsk(o)
Output skew (1)
odc
Output duty cycle (2) (3)
fOUT = 100 MHz; Pdiv = 1
tOE
Output enable to stable clock output
Pin mode. fout = 100 MHz, device in active mode with
outputs disabled, OE asserted
tPD
PD de-asserted to stable clock output
tPU
Time from power applied to stable
clock output (4)
12
V
0.5
V
0.7
V
mA
mA
5.5
ERC = Slow, 20% to 80%, fout = 100 MHz, CL = 8 pF
ERC = Fast, 20% to 80%, fout = 250 MHz, CL = 8 pF
(1)
(2)
(3)
(4)
0.1
ns
V/ns
4
fOUT = 100 MHz, 10k-20M integration bandwidth
45%
280
fs
90
ps
55%
2
µs
Host mode, fout = 100 MHz, device in power down mode, PD
de-asserted
10
µs
Pin mode, fout = 100 MHz, OE asserted, measured from time
VDD is valid to stable output.
1
ms
The tsk(o) specification is only valid for equal loading with identical edge rates and output supply voltages.
Assumes 50% duty cycle at the input.
odc depends on output rise and fall time (tR/tF).
Parameter depends significantly on power supply design and supply voltage rise time.
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6.11 Clock Output Buffer Electrical Characteristics (Output Mode = LVCMOS) (Continued)
Unless otherwise noted, VDDOx as shown in Table sections, TA = –40°C to 85°C. ERC = Fast. For test configurations, see
Figure 21 and Figure 22.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
250
MHz
1.8-V MODE
fout
Output frequency range
0.0008
VDDOx = 1.7 V, IOH = –0.1 mA (All ERC Settings)
1.6
VDDOx = 1.7 V, IOH = –1.5 mA (ERC = SLOW)
VDDOx = 1.7 V, IOH = –3 mA (ERC = MED)
VOH
LVCMOS high-level output voltage
1.4
V
1.1
V
VDDOx = 1.7 V, IOH = –4 mA (ERC = FAST)
VDDOx = 1.7 V, IOH = –3 mA (ERC = SLOW)
VDDOx = 1.7 V, IOH = –5 mA (ERC = MED)
VDDOx = 1.7 V, IOH = –8 mA (ERC = FAST)
VDDOx = 1.7 V, IOL = 0.1 mA (All ERC Settings)
0.1
V
0.3
V
0.6
V
VDDOx = 1.7 V, IOL = 2 mA (ERC = SLOW)
VDDOx = 1.7 V, IOL = 3 mA (ERC = MED)
VOL
LVCMOS low-level output voltage
VDDOx = 1.7 V, IOL = 4 mA (ERC = FAST)
VDDOx = 1.7 V, IOL = 3 mA (ERC = SLOW)
VDDOx = 1.7 V, IOL = 5 mA (ERC = MED)
VDDOx = 1.7 V, IOL = 8 mA (ERC = FAST)
IOH
LVCMOS high-level output current
IOL
LVCMOS low-level output current
tPLH, tPHL
Propagation delay
tSLEW-RATE
VDDOx = 1.8 V, VO = 0.5 V; TA = 25°C
–23
VDDOx = 1.8 V, VO = 0.9 V; TA = 25°C
–18
VDDOx = 1.8 V, VO = 1.4 V; TA = 25°C
27
VDDOx = 1.8 V, VO = 0.9 V; TA = 25°C
23
mA
6.8
Output rise/fall slew rate
ERC = Slow, 20% to 80%, fout = 100 MHz, CL = 8 pF
0.5
ERC = Medium 20% to 80%, fout = 100 MHz, CL = 8 pF
0.8
ERC = Fast, 20% to 80%, fout = 250 MHz, CL = 8 pF
2.7
tjitt-add
Additive jitter
tsk(o)
Output skew (1)
odc
Output duty cycle (2), (3)
fOUT = 100 MHz; Pdiv = 1, ERC = MED, FAST
tOE
Output enable to stable clock output
Pin mode. fout = 100 MHz, device in active mode with outputs
disabled, OE asserted
tPD
PD de-asserted to stable clock output
tPU
Time from power applied to stable
clock output (4)
(1)
(2)
(3)
(4)
mA
fOUT = 100 MHz, 10k-20M integration bandwidth
45%
ns
V/ns
350
fs
130
ps
55%
2
µs
Host mode, fout = 100 MHz, device in power down mode, PD deasserted
10
µs
Pin mode, fout = 100 MHz, OE asserted, measured from time VDD
is valid to stable output.
1
ms
The tsk(o) specification is only valid for equal loading with identical edge rates and output supply voltages.
Assumes 50% duty cycle at the input.
odc depends on output rise and fall time (tR/tF).
Parameter depends significantly on power supply design and supply voltage rise time.
VMAX = 1.15V
REFCLK VCROSSMAX = 550 mV
VCROSSMIN = 250 mV
REFCLK +
VMIN = -0.3 V
Figure 1. HCSL Crossing Point Voltage
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REFCLK -
140 mV
REFCLK+
Figure 2. HCSL Variation of VCROSS Over All Rising Clock Edges
TSTABLE
VRB
VIH = +150 mV
VRB = +150 mV
0.0 V
VRB = -150 mV
VIL = -150 mV
REFCLK+
VRB
minus
REFCLK –
TSTABLE
Figure 3. HCSL Ring Back Margin and Timing
tr
tf
VIH - +150 mV
VIL - -150 mV
REFCLK +
Minus
REFCLK -
Figure 4. HCSL Rise Fall Time and Edge Speed
T
REFCLK VCROSS MEDIAN
REFCLK +
REFCLK VCROSS MEDIAN+ 75 mV
VCROSS MEDIAN
VCROSS MEDIAN - 75 mV
FA
LL
TR
E
IS
REFCLK +
Figure 5. HCSL Rise Fall Time Matching
14
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Clock Period (Differential )
Positive Duty Cycle
(Differential )
Negative Duty Cycle
(Differential)
0V
REFCLK+
Minus
REFCLK -
Figure 6. HCSL Duty Cycle
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6.12 Typical Characteristics
3.5
3.5
VDDOx = 3.3 V
3
VDDOx = 3.3 V
VOL - Low Level Output Voltage - V
VOH - High Level Output Voltage - V
3
2.5
VDDOx = 1.8 V
2
VDDOx = 2.5 V
1.5
1
0.5
2.5
VDDOx = 2.5 V
2
VDDOx = 1.8 V
1.5
1
0.5
0
-80
0
-70
-60
-50
-40
-30
IOH - High Level Output Current - mA
-20
-10
0
0
10
Figure 7. High-Level Output Voltage
vs Current - LVCMOS Mode
3.5
3
LVCMOS Output Signal Swing - V
LVCMOS Output Signal Swing - V
60
70
80
2.5
ERC_MED
2.5
ERC_SLOW
2
1.5
2
ERC_FAST
1.5
ERC_MED
ERC_SLOW
1
VDD = 2.5 V,
CL = 8 pF,
TA = 25°C
0.5
1
0
50
100
150
200
250
300
350
0
400
50
100
150
200
250
300
350
fOUT - MHz
fOUT - MHz
Figure 9. CDCUN1208LP LVCMOS Signal Swing
Characteristics (3.3-V Mode)
Figure 10. CDCUN1208LP LVCMOS Signal Swing
Characteristics (2.5-V Mode)
2
5
VDD = 1.8 V,
CL = 8 pF,
TA = 25°C
1.5
ERC_MED
1
ERC_SLOW
0.5
400
VDD = 3.3 V,
ERC = FAST,
TA = 25°C
4.5
LVCMOS Output Signal Swing - V
ERC_FAST
LVCMOS Output Signal Swing - V
30
40
50
IOL - Low Level Output Current - mA
Figure 8. Low-Level Output Voltage
vs Current - LVCMOS Mode
VDD = 3.3 V,
CL = 8 pF,
TA = 25°C
ERC_FAST
20
4
CL = 0 pF
CL = 10 pF
3.5
3
CL = 8 pF
2.5
2
1.5
1
0.5
0
16
0
50
100
150
200
250
300
350
400
0
0
50
100
150
200
250
300
350
400
fOUT - MHz
fOUT - MHz
Figure 11. CDCUN1208LP LVCMOS Signal Swing
Characteristics (1.8-V Mode)
Figure 12. CDCUN1208LP LVCMOS Capacitive Load Drive
Characteristics (3.3-V Mode)
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Typical Characteristics (continued)
3.5
3
CL = 10 pF
LVCMOS Output Signal Swing - V
LVCMOS Output Signal Swing - V
3
3.5
VDD = 2.5 V,
ERC = FAST,
TA = 25°C
2.5
2
CL = 0 pF
CL = 8 pF
1.5
1
2.5
CL = 8 pF
2
CL = 0 pF
1.5
CL = 10 pF
1
0.5
0.5
0
0
VDD = 1.8 V,
ERC = FAST,
TA = 25°C
50
100
150
200
250
300
350
400
0
0
50
fOUT - MHz
100
150
200
250
300
350
400
fOUT - MHz
Figure 13. CDCUN1208LP LVCMOS Capacitive Load Drive
Characteristics (2.5-V Mode)
Figure 14. CDCUN1208LP LVCMOS Capacitive Load Drive
Characteristics (1.8-V Mode)
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7 Parameter Measurement Information
7.1 Test Configurations
Oscilloscope
High
Impedance
Probes
CH2
CH1
50 W
100 W
LVDS
50 W
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Figure 15. CDCUN1208LP LVDS Output - Test Setup
Oscilloscope
CH1
PCB Trace
50 W
Cable
CH2
50 W
LVDS
50 W
SMA
(2)
Copyright © 2017, Texas Instruments Incorporated
Figure 16. CDCUN1208LP LVDS Output - Propagation Delay/Skew Measurement Setup
Spec Analyzer
PCB Trace
Cable
50 W
50 W
Cable
BALUN
RF
SMA
LVDS
50 W
50 W
50 W
SMA
(2)
SMA
(2)
50 W (3)
Copyright © 2017, Texas Instruments Incorporated
Figure 17. CDCUN1208LP LVDS Output - Phase Noise/Jitter Measurement Setup
Figure 18 shows the configuration used to measure the HCSL buffer characteristics. Either single-ended probes
with math or differential probes can be used for differential measurements. The 50-Ω differential trace length is
up to 15 inches.
18
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Test Configurations (continued)
Oscilloscope
High
Impedance
Probes
33.1 W (2)
CH2
CH1
50 W
HCSL
50 W
50 W (2)
2 pF (2)
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Figure 18. CDCUN1208LP HCSL Output – Measurement Configuration With Load
Oscilloscope
CH1
PCB Trace
CH2
50 W
50 W
HCSL
50 W
SMA
(2)
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Figure 19. CDCUN1208LP HCSL Output – Propagation Delay/Skew Measurement
Spec Analyzer
BALUN
Cable
PCB Trace
50 W
Cable
RF
50 W
HCSL
50 W
SMA
50 W
50 W (2)
SMA
(2)
50 W
SMA
(2)
Copyright © 2017, Texas Instruments Incorporated
Figure 20. CDCUN1208LP HCSL Output – Phase Noise/Jitter Measurement Configuration
Oscilloscope
450 W
LVCMOS
PCB Trace
50 W
Cable
CH1
CH2
50 W
SMA
8 pF
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Figure 21. CDCUN1208LP LVCMOS Output – Measurement Configuration
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Test Configurations (continued)
Spec Analyzer
PCB Trace
50 W
LVCMOS
RF
Cable
50 W
SMA
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Figure 22. CDCUN1208LP LVCMOS Output – Phase Noise/Jitter Measurement Setup
Signal Generator
REF
RF
BALUN
Cable
PCB Trace
50 W
50 W
50 W
50 W
100 W
Signal Generator
REF
RF
INx
(a)
50 W
50 W
50 W
50 W
INx
(b)
Vbias
50 W (2)
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Figure 23. CDCUN1208LP Universal Input - Differential Mode Measurement Setup
Signal Generator
REF
RF
PCB Trace
50 W
INx
50 W
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Figure 24. CDCUN1208LP Universal Input - Single-Ended Mode Measurement Setup
20
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SCAS928D – MAY 2012 – REVISED APRIL 2019
Test Configurations (continued)
Power Supply
VOUT
Power Supply
IOUT
GND
VOUT
+
IOUT
GND
VOUT
+
VDD
VDD
OUTx
50W (2)
OUTx
100W
OUTx
50W (2)
OUTx
REF
CLK
OUTx
OUTx
OUTx
OUTx
OUTx
OUTx
8 pF (2)
OUTx
8 pF (2)
INx
100W
INx
VDDOx
50W (2)
OUTx
100W
OUTx
8 pF (2)
50W (2)
OUTx
100W
OUTx
8 pF (2)
VDDOx
VDDOx
50W (2)
OUTx
100W
OUTx
8 pF (2)
50W (2)
OUTx
100W
OUTx
8 pF (2)
VDDOx
VDDOx
OUTx
8 pF (2)
A
REF
CLK
VDDOx
INx
VDDOx
OUTx
100W
INx
50W (2)
50W (2)
(a) HCSL
+
VDDOx
A
VDDOx
INx
OUTx
VDDOx
A
INx
IOUT
GND
VDD
VDDOx
REF
CLK
Power Supply
OUTx
VDDOx
100W
OUTx
(b) LVDS
8 pF (2)
(c) LVCMOS
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Figure 25. CDCUN1208LP Power Consumption Measurement Setup
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8 Detailed Description
8.1 Overview
The CDCUN1208LP is a 2:8 fan-out buffer featuring a wide operating supply range, two universal differential or
single-ended inputs, and universal outputs (HCSL, LVDS, or LVCMOS) with edge rate control. The clock buffer
supports PCIe Gen1, Gen2, and Gen3. One of the device inputs includes a divider that provides divide values of
/1, /2, /4, or /8. The device is flexible and easy to use. The state of certain pins determines device configuration
at power up. Alternately, the CDCUN1208LP provides a SPI/I2C port with which a host processor controls device
settings. The CDCUN1208LP delivers excellent additive jitter performance, and low power consumption. The
device can run in mixed output supply mode with a dedicated supply pin for each group of outputs. This allows
the device to work as an LVCMOS-level translator as well.
8.2 Functional Block Diagrams
LVCMOS
VDD
GND
Voltage
Regulator
LVCMOS
Power
Management
1.8V, 2.5V, or 3.3V
LVCMOS
LVCMOS
LVCMOS
INSEL
VDD
LVCMOS
LVCMOS
1.8V, 2.5V, or 3.3V
HCSL ITTP
LVCMOS
LVDS
LVCMOS
IN1P
IN2P
IN2N
/1,/2,/4,/8
INMUX
IN1N
LVCMOS
LVCMOS
1.8V, 2.5V, or 3.3V
LVCMOS
DIVIDE
NC
LVCMOS
MODE
LVCMOS
LVCMOS
1.8V, 2.5V, or 3.3V
VDD
LVCMOS
LVCMOS
HCSL OTTP
LVCMOS
LVDS
OE
ERC
CDCUN1208LP
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Figure 26. CDCUN1208LP Typical Application Example – LVCMOS Output Mode
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Functional Block Diagrams (continued)
VDD
VDD
INSEL
HCSL P
LVCMOS
NC
HCSL
ITTP
HCSL N
LVDS
INSEL
LVDS P
LVCMOS
NC
ITTP
LVDS P
HCSL P
IN1P
HCSL N
IN1P
INMUX
/1,/2,/4,/8
LVDS N
IN1N
INMUX
IN1N
IN2P
HCSL P
IN2P
HCSL N
/1,/2,/4,/8
IN2N
IN2N
DIVIDE
HCSL P
LVDS P
HCSL N
LVDS N
HCSL P
NC
MODE
LVDS P
LVDS N
HCSL N
VDD
LVCMOS
NC
HCSL P
LVDS
LVDS P
VDD
HCSL P
HCSL N
HCSL OTTP
LVCMOS
LVDS N
HCSL OTTP
LVDS P
LVDS
LVDS N
HCSL N
OE
OE
CDCUN1208LP
LVDS N
LVDS N
HCSL N
MODE
LVDS P
LVDS P
HCSL P
DIVIDE
NC
LVDS N
ERC
CDCUN1208LP
ERC
Copyright © 2017, Texas Instruments Incorporated
Figure 27. CDCUN1208LP Applications – HCSL and LVDS Fan-Out Buffer Mode
8.3 Feature Description
8.3.1 Device Control Using Configuration Pins
Figure 28 illustrates and Table 1 lists the CDCUN1208LP device settings using the configuration pins. Some pins
sense three different states (HIGH, LOW, OPEN) according to Figure 28 and Digital Input Electrical
Characteristics – OE (SCL), INSEL, ITTP, OTTP, Divide (SDA/MOSI), ERC(ADDR/CS), Mode. The device
samples the state of the pins at power up and configures the device accordingly. Certain pins including INSEL
and OE are sampled continuously; thus, changes of state of INSEL or OE control the device instantly.
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Feature Description (continued)
VDD
IN2
AUTO
NC
INSEL
IN1
VDD
HCSL
VDD
LVCMOS
NC
HCSL
LVCMOS
NC
OTTP
LVDS
ITTP
LVDS
OUT1P
IN1P
OUT1N
INMUX
IN1N
IN2P
OUT2P
OUT2N
/1,/2,/4,/8
IN2N
~
~
~ ~
~
~
VDD
NC
/4
/1
OUT8P
DIVIDE
OUT8N
/2
OE
VDD
MODE (PINS)
Medium
CDCUN1208LP
ERC
Fast
NC
Slow
Copyright © 2017, Texas Instruments Incorporated
Figure 28. CDCUN1208LP Pin Configuration Overview
Table 1. CDCUN1208LP Pin Configuration Summary
PIN NAME
PIN NUMBER
DEFINITION
DEVICE CONFIGURATION
DETAILS
Output type setting
See Table 2
DEVICE OUTPUTS
OTTP
19
ERC
31
Edge rate control
See Table 3
OE
32
Device global output enable
See Table 4
DEVICE INPUTS
24
ITTP
8
Input type setting
See Table 5
DIVIDE
1
IN2 input divider control
See Table 6
INSEL
2
Input multiplexer setting
See Table 7
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8.3.1.1 Configuration of Output Type (OTTP)
Table 2 shows how to set the output buffer type using the OTTP pin. This setting affects all device outputs
equally. Certain combinations of output buffers include a dedicated power supply pin, which must be properly
bypassed. If the device output configuration is set to LVCMOS, then the supply voltage applied establishes the
switching thresholds corresponding to the supply provided according to Clock Output Buffer Electrical
Characteristics (Output Mode = LVCMOS). For example, if OUT1 and OUT2 are supplied with a 1.8-V power
supply through the VDDO1 pin, the switching thresholds are set to the 1.8-V logic domain. The system may have
other logic supplies (1.8 V, 2.5 V, or 3.3 V) connected to the device on different output buffer supply domains
simultaneously. This enables the device to clock devices operating on different supplies, without the need for
external logic level translation buffers. The CDCUN1208LP automatically adjusts the switching thresholds
corresponding to these common logic power supply voltages. For more information regarding the power supplies
for the output section, see Device Power Supply Connections and Sequencing.
Table 2. CDCUN1208LP Pin Configuration of Output Type
OTTP (Pin 19)
OUTPUT TYPE
LOW
LVDS
HIGH
HCSL
OPEN
LVCMOS
8.3.1.2 Configuration of Edge Rate Control (ERC)
The CDCUN1208LP supports Edge Rate Control (ERC), to tailor jitter and EMI performance from device outputs.
Table 3 shows the edge rate control setting. This setting affects all device outputs equally. Each edge rate
setting is unique to the output buffer type selected as described in Clock Output Buffer Characteristics (Output
Mode = LVDS), Clock Output Buffer Characteristics (Output Mode = HCSL), and Clock Output Buffer Electrical
Characteristics (Output Mode = LVCMOS).
Table 3. CDCUN1208LP Pin Configuration of Output Edge Rate
ERC (Pin 31)
OUTPUT EDGE RATE
LOW
SLOW
HIGH
MEDIUM
OPEN
FAST
8.3.1.3 Control of Output Enable (OE)
Table 4 shows how the output enable pin controls the device outputs. The OE pin is sampled continuously, so
that the application may turn on/off the output buffers at any time.
Table 4. CDCUN1208LP Pin Control of Output Enable
(1)
OE (Pin 32)
OUTPUT ENABLE
LOW
DISABLED in tri-state
HIGH
ENABLED
OPEN
RESERVED (1)
Leaving the Output Enable pin OPEN causes the CDCUN1208LP to malfunction. This pin must be
driven high or low at all times.
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8.3.2 Input Ports (IN1, IN2)
8.3.2.1 Configuration of the Input Type (ITTP)
Table 5 describes how to set the input buffers to the appropriate switching levels using the ITTP pin. For proper
input termination, see Figure 46.
Table 5. CDCUN1208LP Pin Control of Input Type (ITTP)
ITTP (Pin 8)
ITTP SETTING
LOW
LVDS
HIGH
HCSL
OPEN
LVCMOS
8.3.2.2 Configuration of the IN2 Divider (INDIV)
Table 6 describes how to set the input divider using the DIVIDE pin. If the /8 setting is desired, then this feature
is accessed through the host configuration method only; refer to Device Control Using the Host Interface.
Table 6. CDCUN1208LP Pin Control of INDIV Divider
DIVIDE (Pin 1)
INDIV DIVIDER SETTING
LOW
/2
HIGH
/4
OPEN
/1
8.3.3 Smart Input Multiplexer (INMUX)
The smart multiplexer supports manual and automatic switching between IN1 and IN2. If enabled, the smart
multiplexer switches automatically between clock inputs based on a prioritization scheme shown in Table 7. If
using the smart multiplexer auto mode, the frequencies of the clocks applied to the smart multiplexer through IN1
and IN2 (through the divider) may differ by up to 20%. The phase relationship between clock inputs has no
restrictions. The smart multiplexer includes signal conditioning that provides glitch suppression.(1)
Upon the detection of a loss of signal on the input with higher priority, the smart multiplexer switches over to the
other clock input on the first incoming rising edge. During this switching operation, the output of the smart
multiplexer is low. Upon restoration of the higher priority clock, the smart multiplexer waits until it detects four
complete cycles from the higher priority clock prior to switching the output of the smart multiplexer back to the
higher priority clock. During this switching operation, the output of the smart multiplexer remains high until the
next falling edge as shown in Figure 29.
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8.3.3.1 Pin Configuration of the Smart Input Multiplexer (INMUX)
Table 7 shows how to control the smart input multiplexer. In pin configuration mode, the INSEL pin is sampled
continuously, so that the application may select the input clock at any time.
Table 7. Control of INMUX via the INSEL Pin
INSEL(Pin 2)
IN1 BUFFER SETTING
LOW
ON and selected by INSEL multiplexer
OFF
HIGH
OFF
ON and selected by INSEL mux
OPEN
IN2 BUFFER SETTING
Smart multiplexer selects input. IN1 is the primary input (it has the highest priority, therefore if it is available,
the smart multiplexer selects IN1)
PRI _REF
SEC _REF
Internal
Reference Clock
Primary Clock
Secondary Clock
Primary Clock
Figure 29. CDCUN1208LP Smart Multiplexer Operation
(1)
This implementation does not implement a phase build-out mechanism; rather, analog filtering insuring a smooth transition at device
outputs.
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8.4 Device Functional Modes
8.4.1 Device Control Using the Host Interface
Host configuration mode affords a greater degree of flexibility. Unlike pin configuration mode, in which the pin
settings affect the entire device, host configuration mode enables the user to apply different settings to each
input and output port, as depicted in Figure 30. This includes the ability to mix and match output type, edge rate
control, and output enable settings. The host interface is enabled or selected by strapping the MODE pin either
high (for I2C) or low (for SPI) and resetting the device. Additional device features are accessible only through the
host interface as well. For instance, the user can configure the input divider (IDIV) to /8 in host configuration
mode only. Additionally, the system can power down the device through device registers.
8.4.1.1 OE and INSEL in Host Configuration Mode
In host configuration mode, the OE pin is no longer available; thus buffers are controlled individually through the
host interface. The input multiplexer can be controlled either through the pin or through the device registers, in
accordance with Table 12.
LVCMOS
VDD
GND
Voltage
Regulator
LVCMOS
Power
Management
3.3V
LVCMOS
OUT2N
INSEL
LVCMOS
LVCMOS
IN1P
1.8V
IN2P
/1,/2,/4,/8
INMUX
IN1N
LVDS
LVDS
IN2N
LVDS
LVDS
3.3V
LVDS
Interface
&
Control
VDD
NC
PINS
I2C
Registers
SPI
LVDS
Microcontroller /
FPGA/DSP
LVDS
LVDS
3.3V
MODE
HCSL
HCSL
SPI
CDCUN1208LP
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Figure 30. CDCUN1208LP Host Configuration – Typical Application
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Device Functional Modes (continued)
When the host interface is enabled, certain pins take on alternative functions, according to Table 8.
Table 8. CDCUN1208LP Host Configuration Pins
PIN NAME
ALT PIN NAME
IN
IN PIN MODE
HOST MODE (MODE = OPEN)
MODE
PIN
NUMBER
PIN NAME IN PIN CONFIGURATION
MODE
(only if MODE/Pin 30 is OPEN)
PIN NAME IN HOST PROGRAMMING MODE
(MODE/Pin 30 is tied high or low)
30
Programming mode
1 = I2C, 0 = SPI,OPEN = Pins (alternative
description applies)
SDA/MOSI
DIVIDE
1
Host interface data (I2C) / SPI Master output
slave input (data In)
Input divider pin control
MISO
OTTP
19
SPI master input slave output (data out)
Output type (OTTP) pin control
SCL
OE
32
Host interface clock
Device output enable
1 = Enable, 0 = Disable
ADDR/CS
ERC
31
Host interface address (I2C) / chip select (SPI)
Pull ADDR to GND for I2C communication
Output edge rate control
1 = Fast, 0 = Slow, OPEN = Medium
MODE
Input
Control
OUTn
OUT2
OUT1
OE
High or Low
Pin Configuration Mode
IN2
IN1
CDCUN1208LP
INSEL
OUTn
MISO
SCK
SDA/MOSi
ADDR/CS
OUT2
OUT1
Device
Outputs
INSEL
CDCUN1208LP
Output
Control
Open
IN2
IN1
Power
On
Reset
(POR)
Device
Outputs
Device
Inputs
Power
On
Reset
(POR)
Device
Inputs
OTTP
ERC
Input
Host
Interface Control
ITTP
DIVIDE
Output
Settings
Input
Settings
The CDCUN1208LP samples the MODE pin after the device exits the power-on reset (POR) state. The device is
placed in the RESET state in one of two ways: a POR circuit automatically resets the device after power is
applied; or through the RESET bit (R15[1]) in register memory (see Table 12). This RESET bit is only accessible
in host configuration mode. If the MODE pin (pin 11) is open (no connection), then the device is placed in the pin
configuration mode and all settings are determined by the state of various pins according to Table 1 and
Figure 28. If the MODE pin is low, then device enables the SPI interface; and, if MODE is high, then I2C is
enabled.
MODE
Host Configuration Mode
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Figure 31. CDCUN1208LP Pin and Host Configuration Mode
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8.5 Programming
8.5.1 Host Interface Hardware Information
8.5.1.1 SPI Communication
A SPI communication link includes a master and one or more slaves (note that CDCUN1208LP supports only
single-device). Table 8 lists the four signal lines that form a SPI communication link. Figure 32 shows the format
for SPI messages. The SPI master (host) initiates communication by asserting SCS low. Information on SDI/SDO
is latched on each rising edge of SCL. The first bit transmitted on SDI establishes the direction of the SPI
transfer. Next, the master transmits the address to be written/read (up to 15 bits). If the operation is a write, the
master transmits 16 data bits on SDI. If the transfer is a read, the slave transmits 16 data bits on SDO (the
master continues to clock the transfer through SCL). Figure 34 and Table 9 show the timing specifications for
SPI.
WRITE
SCS
SCL
SDI
A8
A7
A6
A5
A4
A3
A2
A1
A0 D15 D14 D13 D12 D11 D10 D9
D8
R A14 A13 A12 A11 A10 A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
'RQ¶W &DUH
D7
D6
D5
D4
D3
D2
D1
D0
D5
D4
D3
D2
D1
D0
READ
SDI
W A14 A13 A12 A11 A10 A9
Hi-Z
SDO
D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
Figure 32. SPI Message Format
8.5.1.1.1 CDCUN1208LP SPI Addressing
Figure 33 shows how to construct the address field for SPI messages to and from the CDCUN1208LP. The
device is assigned a 4-bit fixed address (0001b). For the host to communicate with the CDCUN1208LP, the
address must include this fixed value in the correct position for the device to recognize the message.
SCL
SDI
W A14 A13 A12 A11 A10 A9
A8
A7
A6
A5
A4
A3
A2
A1
A0 D15 D14 D13 D12 D11 D10 D9
D8
SDI
R A14 A13 A12 A11 A10 A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
'RQ¶W &DUH
D7
D6
D5
D4
D3
D2
D1
D0
D5
D4
D3
D2
D1
D0
READ
WRITE
SCS
SDO
D15 D14 D13 D12 D11 D10 D9
Hi-Z
msb
D8
D7
D6
lsb
0
0
0
1
0
0
0
SPI Fixed Address
0
0
0
0
A3
A2
A1
A0
CDCUN1208LP Register Address
Figure 33. CDCUN1208LP Device Addressing - SPI Mode
8.5.1.1.2 Writing to the CDCUN1208LP
To initiate a SPI data transfer, the master (host) asserts the SCS (serial chip select) pin low (see Figure 32). The
first rising edge of the clock signal (SCL) transfers the bit presented on the SDI pin of the CDCUN1208LP. This
bit signals if a read (first bit high) or a write (first bit low) will transpire. The master shifts data to the slave with
each rising edge of SCL. Following the W/R bit are 4 fixed bits followed by 11 bits that specify the address of the
target register in the register file (see Figure 33). The 16 bits that follow are the data payload. If the master sends
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Programming (continued)
an incomplete message, (that is, the master de-asserts the SCS pin high prior to a complete message
transmission), then the slave aborts the transfer, and device makes no changes to the register file or the
hardware. The master signals the slave of the completed transfer and disables the SPI port by de-asserting the
SCS pin high. At no time should the clock be toggled while SCS is high. CDCUN1208LP should always be used
in single-slave SPI configuration.
8.5.1.1.3 Reading From the CDCUN1208LP
As with the write operation, the master first initiates a SPI transfer by asserting the SCS pin low. The host signals
a read operation by shifting a logical high in the first bit position, signaling the slave that the master is initiating a
read data transfer from the slave. Thereafter, the master specifies the address of interest according to Figure 33.
During the 16 clock cycles that follow, the slave presents the data from the register specified in the first half of
the message on the SDO pin. The master signals the slave that the transfer is complete by de-asserting the SCS
pin high. At no time should the clock be toggled while SCS is high. CDCUN1208LP should always be used in
single-slave SPI configuration.
8.5.1.1.4 Block Write/Read Operation
The CDCUN1208LP supports a block write and block read operation. The master need only specify the lowest
address of the sequence of addresses that the host needs to access. The CDCUN1208LP automatically
increments the internal register address pointer if the SCS pin remains active low after the SPI port finishes the
initial 32-bit transmission sequence. Each transmission of 16 bits (a data payload width) results in the slave
automatically incrementing the address pointer (provided the SCS pin remains active low for all sequences).
Figure 34. SPI Timing Diagram
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Programming (continued)
Table 9. SPI Timing Specifications
PARAMETER
MIN
TYP
MAX
UNIT
20
MHz
fClock
Clock frequency for the SCL
t1
SCS to SCL setup time
10
ns
t2
SDI to SCL setup time
10
ns
t3
SDI to SCL hold time
10
ns
t4
SCL high duration
25
ns
t5
SCL low duration
25
ns
t6
SCL to SDO Setup time
10
ns
t7
SCS pulse width
20
ns
t8
SCL falling edge to SCS release time
10
ns
8.5.1.2 I2C Communication
The CDCUN1208LP incorporates an I2C port compliant with I2C Bus Specification V2.1 (7-bit addressing). Some
highlights are contained herein to provide clarity with respect to how communication between the host and the
CDCUN1208LP is facilitated. The I2C bus comprises two signals (clock – SCL, and data – SDA). I2C implements
a master-slave protocol and supports multi-master implementations. Unlike SPI that implements a chip select
signal for device-level addressing and separate data signals for transmit and receive, I2C embeds the device
address in the serial data stream. Because of this, devices that reside on the I2C must have a unique bus
address. I2C also uses the protocol to control the direction of data flow through the data signaling line.
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8.5.1.2.1 Message Transmission
8.5.1.2.1.1 Data and Address Bits
When transmitting address or data bits, the transmitter must only change the state of SDA when SCL is low.
During the time that SCL is high, SDA must be stable (no transitions).
SDA
SCL
SDA Stable,
Data Valid
SDA State
Change
Permitted
Figure 35. I2C Data/Address Bit Transmission
8.5.1.2.1.2 Special Symbols – Start (S) and Stop (P)
Messages are framed by the master by generating a START and a STOP symbol. The START symbol is
signaled by transitioning the SDA line from high to low while the SCL line is high. The STOP symbol is signaled
by transitioning the SDA line from low to high while the SCL line is high.
~
~
MESSAGE BODY
SDA
~
~
~
~
SCL
START
STOP
2
Figure 36. I C Bus START and STOP Symbol Generation
8.5.1.2.1.3 Special Symbols – Acknowledge (ACK)
The acknowledge symbol must be sent by the receiver during the 9th clock cycle after the transmitter sends a
byte of data. The transmitter allows the SDA pin to go high, and the receiver pulls the line low to acknowledge
the receipt of the byte (leaving the SDA high indicates that the byte was not received). If this occurs the
transmitter issues a STOP and retransmits the message. If the receiver is not prepared to receive another byte, it
can suspend transmission by holding the SDA line low during the ACK time slot. When the receiver is ready to
receive another byte, it releases the SDA line.
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8.5.1.2.1.4 Generic Message Frame
Figure 37 shows a typical format for I2C messages. The message frame is bracketed by the START and STOP
symbols (both generated by the master). If a START symbol has not been transmitted, then the bus is
considered ‘available’. If a START symbol has been transmitted and a STOP symbol has not been transmitted,
the bus is considered ‘busy’. The first 8 bits transmitted include the R/W bit and a 7-bit I2C address field. The
reception of each byte grouping that is transmitted must be acknowledged by the receiver. Next, the high byte of
the data pay load is transmitted (MSB first) followed by an acknowledgment by the receiver. Finally, the low byte
is sent. After acknowledgment, the master sends a STOP symbol to end the message frame.
~
~
~
~
~
~
SDA
1-7
8
9
I2C
ADDRESS
R/W
ACK
~
~
~
~
~
~
START
~
~
~
~
~
~
SCL
1-7
8
9
1-7
ACK
DATA
(HIGH
BYTE)
8
9
ACK
DATA
(LOW
BYTE)
STOP
Figure 37. I2C Message Format
8.5.1.2.1.5 CDCUN1208LP Message Format
Figure 38 shows the format of addressing and flow control for I2C messages to and from the CDCUN1208LP. A
message includes two address fields. The I2C address is used to support multiple devices on the bus (each
device must have a unique I2C address). The register address specifies which register of the device identified by
the I2C address is to be written/read.
Byte: 1
Block: 0
Read: 1
Write: 0
S
T
A
R
T
1
0
I2C Address
R/W
7 Bits
1 Bit
1
0
0
0
A
C
K
Y/B
Slave Address
7 Bits
1 Bit
0
CDCUN1208LP
I2C Address
0
0
A
C
K
~
~
0
~
~
Message
Addressing
and Control
A3 A2 A1 A0
CDCUN1208LP
Register Address
Figure 38. CDCUN1208LP I2C Message - Addressing
8.5.1.2.1.6 CDCUN1208LP Device Addressing (I2C Address)
Figure 38 outlines the construction of the I2C address shown in Figure 37. The I2C address is set to 7b'0101000,
or 0x28. The ADDR pin must be pulled to ground. The next 8 bits transmitted is called the register address.
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8.5.1.2.1.7 CDCUN1208LP Device Addressing (Register Address)
Figure 38 shows the format of the register address field of the I2C message. The first bit determines if the
transfer is a byte or a block (more than one byte). The CDCUN1208LP register width is 16 bits (2 bytes),
therefore, generally block addressing is used to access each register in its entirety. Because the I2C protocol
requires that the slave address is a 7-bit field, the leading 3-bits are all ‘0’ while the trailing 4-bits specify the
device register of interest.
8.5.1.2.2 I2C Master and Slave Handshaking
Figure 39 shows the handshaking between the master (host) and the slave (CDCUN1208LP) that the I2C
protocol supports. In all cases, the master drives the SCL (clock line); however, depending on the direction of
transfer/acknowledgment, the master or the slave device drives SDA (data line).
WRITE
Word
READ
Word
S
T
A
R
T
I2C Address
S
T
A
R
T
I2C Address
7 Bits
7 Bits
W
R
I
T
E
B
W
R
I
T
E
B
A L
A
0 C 0OC Slave Address C
K K
K
7 Bits
A L
A
0 C 0OC Slave Address C
K K
K
7 Bits
Data
(High Byte)
S
T
O
P
S
T
A
R
T
A
C
K
A
C
I2C Address
K
7 Bits
Data
(Low Byte)
A
R
1EA C
D
K
A
C
K
S
T
O
P
Data
(High Byte)
Slave Drives SDA
A
C
K
Data
(Low Byte)
A
C
K
S
T
O
P
Master Drives SDA
Figure 39. I2C Master and Slave Handshaking Example
8.5.1.2.3 Block Read/Write
For block write/read operations, the bytes are accessed in sequential order from lowest to highest byte (with
most significant bit first), with the ability to stop after any complete byte has been transferred. The start address
of the transfer is specified in the same way a single word transfer is initiated.
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8.5.1.2.4 I2C Timing
Figure 40 and Table 10 provide details regarding the timing requirements for I2C:
STOP
ACK
START
tW(SCLL)
tW(SCLH)
tr(SM)
STOP
tf(SM)
~
~
VIH(SM)
SCL
VIL(SM)
~
~
th(START)
tSU(START)
tr(SM)
tSU(SDATA )
th(SDATA )
tSU(STOP)
tf(SM)
tBUS
~
~
~
~
VIH(SM)
SDA
VIL(SM)
~
~
Figure 40. I2C Timing Diagram
Table 10. I2C Timing Requirements
PARAMETER
MIN
MAX
UNIT
0
100
kHz
fSCL
SCL clock frequency
tsu(START)
START setup time (SCL high before SDA low)
th(START)
START hold time (SCL low after SDA low)
tw(SCLL)
SCL low-pulse duration
tw(SCLH)
SCL high-pulse duration
th(SDA)
SDA hold time (SDA valid after SCL low)
tsu(SDA)
SDA setup time
tr
SCL / SDA input rise time
1000
ns
tf
SCL / SDA input fall time
300
ns
tsu(STOP)
STOP setup time
tBUS
Bus free time between a STOP and START condition
36
4.7
µs
4
µs
4.7
µs
4
µs
0
3.45
250
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µs
ns
4
µs
4.7
µs
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8.6 Register Maps
8.6.1 Device Registers
8.6.1.1 Device Registers: Register 00-07
Register
Register
Register
Register
Register
Register
Register
Register
00:
01:
02:
03:
04:
05:
06:
07:
OUT1
OUT2
OUT3
OUT4
OUT5
OUT6
OUT7
OUT8
Table 11. CDCUN1208LP Register 0–7 Bit Definitions
RAM BIT
BIT NAME
RELATED BLOCK
DESCRIPTION / FUNCTION
POWER UP CONDITION
15
14
13
TI RESERVED
TI RESERVED
12
11
10
OUTx CMOS MODE
1 – Both sides pseudo differential
0 – Both sides in phase
OUTx_CMOS_MODE
9
8
OUTx Edge Rate Control
111 – Medium
100 - Fast
000 - Slow
OUTx_ERC[2:0]
7
6
5
TI RESERVED
4
OUTx_OE[1:0]
3
TI RESERVED
Reg 00: OUT1
Reg 01: OUT2
Reg 02: OUT3
Reg 03: OUT4
Reg 04: OUT5
Reg 05: OUT6
Reg 06: OUT7
Reg 07: OUT8
2
1
0
OUTx_OTTP[1:0]
OUTx_PD
OUTx Output Enable
OTTP = LVCMOS
11 – OUT1P: ON | OUT1N: ON
10 – OUT1P: ON |OUT1N: OFF
01 – OUT1P: OFF| OUT1N: ON
00 – OUT1P: OFF| OUT1N: OFF
0
0
0
0
0
0
0
OTTP = Differential (LVDS, HCSL)
00 – OFF
11 - ON
0
OUTx Output Type
11 – HCSL
10 – Reserved
01 – LVCMOS
00 - LVDS
0
OUTx Buffer
1 – Disabled in Tri-State
0 - Enabled
0
0
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Table 12. CDCUN1208LP Registers 11–15 Bit Definitions
REGISTER
ADDRESS
BIT NAME
15
TI RESERVED
14
TI RESERVED
13
TI RESERVED
12
TI RESERVED
11
TI RESERVED
10
TI RESERVED
9
TI RESERVED
8
TI RESERVED
0
7
TI RESERVED
0
6
TI RESERVED
5
IN_DIV[1]
4
IN_DIV[0]
3
IN_TYPE[1]
11
RELATED BLOCK
0
Input
(IN2 – Divider)
(1)
12-14
2
IN_TYPE[0]
1
INSEL[1]
0
INSEL[0]
ALL
TI RESERVED
2-15
TI RESERVED
1
RESET
0
PD
15
(1)
38
DESCRIPTION / FUNCTION
POWER UP
CONDITION
RAM BIT
Input
(IN1 and IN2 Type)
Input
(multiplexer)
Input Divider Control
1 1 = /8
1 0 = /4
0 1 = /2
0 0 = /1
0
Input Type
1 1 = HCSL
1 0 = LVCMOS
0 1 = LVCMOS
0 0 = LVDS
0
Input Multiplexer Control
1 1 = Control through INSEL pin
1 0 = Smart MUX enabled, IN
1=primary
0 1 = IN2 buffer selected
0 0 = IN1 buffer selected
0
0
0
0
Device Reset
1 = Reset device
0 = Run device
0
Device Power Down
1 = Device is powered down
0 = Device is active
0
When configuring device inputs as LVCMOS, apply the single-ended clock signal to INxP and leave INxN either floating or ground it.
The power supply voltage (1.8 V, 2.5 V, or 3.3 V) applied to VDD (pin 5) establishes the switching thresholds for IN1 and IN2 in
LVCMOS mode.
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The CDCUN1208LP is a low additive jitter, 2:8 fan-out buffer with universal inputs and outputs. The low-power
consumption, low output skew, and low additive jitter make for a flexible device in demanding applications.
9.2 Typical Application
9.2.1 PCI Express Applications
Texas Instruments offers a complete clock solution for PCI Express applications. The CDCUN1208LP can be
used to fan out the 100-MHz clock signal provided by the CDCM9102 as depicted in Figure 41.
VDD
HCSL output
VDD
471Ÿ
471Ÿ
100 MHz LVPECL
ITTP
OUT1P
OUT1N
OUT2P
OUT2N
OTTP
CDCUN1208LP
HCSL input
OUT3P
OUT3N
Up to 8x
OUT4P
OUT4N
HCSL
outputs
IN1P
25MHz
CDCM9102
100MHz
IN1N
150 Ÿ
150 Ÿ
56 Ÿ
56 Ÿ
OUT8P
OUT8N
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Figure 41. Clock Solution for PCIe Express Applications
9.2.1.1 Design Requirements
For this design example, use the parameters shown in Table 13.
Table 13. Design Parameters
PARAMETER
VALUE
fIN1,2
Input single ended frequency of at
least 800 kHz and at most 250
MHz.
fINDIFF
Input differential frequency of at
least 800 kHz and at most 400
MHz (here 100 MHz).
ΔV/ΔT Input edge rate
Input slew rate of at least 0.75
V/ns.
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9.2.1.2 Detailed Design Procedure
The CDCUN1208LP is a easy-to-use device. The user determines the following parameters in order:
In control mode:
• Pin control mode or SPI mode (host interface) : this is done by externally pulling up or pulling down the
MODE pin.
In pin control mode:
• The input type, optional input divider ratio and input multiplexer selection should be set.
• The output type, optional output edge rate control, and output enable should be set. This is described in detail
in Device Control Using Configuration Pins.
In host control mode:
• SPI interface should be connected to the host (only one CDCUN1208LP device can be connected to the bus).
• Communication should follow the procedure described in Device Control Using the Host Interface.
9.2.1.3 Application Curves
Figure 42. Output 1 (LVCMOS) Phase Noise With Clean
122.88-MHz Source
40
Figure 43. Output 2 (LVCMOS) Phase Noise With Clean
122.88-MHz Source
(PN is Slightly Worse Due to the Mux and the Divider)
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9.3 Systems Examples
Figure 44 shows a typical application in which the receiver is off-board. The PCIe Specification (CEM2.0)
requires that all source termination is on the motherboard (not on the daughter card). For this reason, the
termination resistors are placed as shown. Additionally, source resistors are employed to eliminate ringing. In this
case, ZL can vary between 40 Ω and 60 Ω and RS can range from 22 Ω to 33 Ω.
RS (2)
Motherboard Traces
1" Trace
PCIe
Connector
ZL (2)
CL = 2 pF (2)
Copyright © 2017, Texas Instruments Incorporated
Figure 44. Typical Configuration – Off-Board Receiver
Figure 45 shows a typical application in which the receiver is on-board. In this case, series resistors are not
required to eliminate ringing as proper termination is achieved. In this case, two termination resistors, ZL = 49.9
Ω, are placed close to the receiver.
Motherboard
Traces
1" Trace
ZL (2)
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Figure 45. Typical Configuration – On-Board Connection
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10 Power Supply Recommendations
10.1 CDCUN1208LP Power Consumption
Table 14. CDCUN1208LP Power Consumption (TA = –40°C to 85°C)
DEVICE SETTINGS (See Table 1) (1)
PARAMETER
IPD1.8,3.3
ICORE1.8,3.3
MAX CURRENT
VDD= 1.8V
fOUT = fin = 100 MHz
MAX CURRENT
VDD = 3.3V
fOUT = fin = 100MHz
UNIT
Device power down
3
4
mA
Device outputs off
26
35
mA
23
23
mA
TEST
CONFIGURATION
MODE
OE
ERC
OTTP
INSEL
ITTP
PD Bit
L or H
L
X
X
X
L
H
Host configuration
mode
(see Host
Configuration Mode)
O
L
X
X
X
L
X
Figure 25a,b,c
DESCRIPTION
IHCSL1.8,3.3
O
H
O
H
L
O
X
Figure 25a
HCSL buffer current
consumption (2)
ILVDS1.8,3.3
O
H
O
L
L
O
X
Figure 25b
LVDS buffer current
consumption (2)
9
9
mA
8
11
mA
ILVCMOS1.8,3.3
O
H
O
O
L
O
X
Figure 25c
LVCMOS buffer
current consumption
(one side) (2)
IDEV-HCSL1.8,3.3
O
H
O
H
L
O
X
Figure 25a
Device current
consumption – HCSL
mode
200
200
mA
IDEV-LVDS1.8,3.3
O
H
O
L
L
O
X
Figure 25b
Device current
consumption – LVDS
mode
80
90
mA
IDEV-LVCMOS1.8,3.3
O
H
O
O
L
O
X
Figure 25c
Device current
consumption –
LVCMOS mode
130
210
mA
(1)
(2)
H = input high, L = input low; O = input open
Buffer current consumption values represent the average of the current drawn by VDDO1, VDDO2, VDDO3, and VDDO4, divided by 8
(differential mode) or 16 (single-ended mode).
10.2 Device Power Supply Connections and Sequencing
VDD (pin 5) is the core power supply of the device while VDDOx (pins 11, 14, 22, and 27) provide power for the
output sections. The core supply must be present either before the application of the output power supplies or be
present simultaneously. Applying an output power supply voltage on any of the VDDOx pins prior to the
application of power to the core supply pin potentially results in improper device operation.
VDDO2 (pin 14) and VDDO4 (pin 27) provide power for OUT1/OUT2 and OUT7/OUT8, respectively. Additionally,
these pins provide power to integrated voltage regulators that condition power for two banks of outputs. For
example, the regulator associated with OUT1–OUT4 receives power from the VDDO2 pin. Consequently, if the
application requires one or two outputs from a bank of four, then the application must use OUT3/OUT4 and apply
power through VDDO2 (1). Likewise, the regulator that conditions power for OUT5–OUT8 receives power from
VDDO4 (pin 27). If the application uses subset of OUT5–OUT8, then OUT7/OUT8 must be used. For example, if
the application uses 6 of the 8 output channels, then VDDO1, VDDO2, and VDDO4 (along with OUT1–OUT4,
and OUT7–OUT8) must be used. If the application requires the use of 7 of the 8 output channels, the
VDDO1–VDDO4 are used, and OUT1–OUT7 or OUT1–OUT6 and OUT8 could be used.
(1)
42
If OUT1 or OUT2 are used and VDDO1 is powered but not VDDO2, the CDCUN1208LP will not function properly. Likewise, if OUT5 or
OUT6 are used and VDDO3 is powered but not VDDO4, then the device will not function properly either.
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10.3 Device Inputs (IN1, IN2)
Figure 46 shows how to interface certain common signaling formats to the device inputs of the CDCUN1208LP.
This entails both proper signal termination as well as input buffer configuration through the input type (ITTP) pin.
CDCUN1208LP
INxP
~
~
INxN
HCSL
100W
INxN
~
~
~
~
LVDS
INxN
CDCUN1208LP
INxP
~
~
~
~
LVCMOS
CDCUN1208LP
INxP
50W (2)
VDD
LVCMOS
NC
VDD
HCSL
ITTP
LVDS
LVCMOS
NC
HCSL
ITTP
VDD
LVDS
LVCMOS
HCSL
ITTP
NC
LVDS
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Figure 46. Common Interfaces to Device Inputs – DC Coupling
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11 Layout
11.1 Layout Guidelines
•
•
•
•
•
Keep the connections between the bypass capacitors and the power supply on the device as short as
possible.
Ground the other side of the capacitor using a low impedance connection to the ground plane.
If the capacitors are mounted on the back side, 0402 components can be employed.
For component side mounting, use 0201 body size capacitors to facilitate signal routing.
Use a matrix of ground vias to connect the thermal pad to the ground layer.
11.2 Layout Example
Figure 47. Example Layout
44
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12 Device and Documentation Support
12.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.3 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
CDCUN1208LPRHBR
ACTIVE
VQFN
RHB
32
3000
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
UN
1208LP
CDCUN1208LPRHBT
ACTIVE
VQFN
RHB
32
250
RoHS & Green
NIPDAU
Level-2-260C-1 YEAR
-40 to 85
UN
1208LP
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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