CDCV857AGQLR

CDCV857A 2.5-V PHASE LOCK LOOP CLOCK DRIVER SCAS667A – APRIL 2001 – REVISED AUGUST 2002 D D D D D Phase-Lock Loop Clock Driver for Double Data-Rate Synchronous DRAM Applications Spread Spectrum Clock Compatible Operating Frequency: 60 to 180 MHz Low Jitter (cyc–cyc): ±50 ps Distributes One Differential Clock Input to Ten Differential Outputs D D D D D Three-State Outputs When the Input Differential Clocks Are 20 MHz input signal this detection circuit turns on the PLL again and enables the outputs. When AVDD is strapped low, the PLL is turned off and bypassed for test purposes. The CDCV857A is also able to track spread spectrum clocking for reduced EMI. Since the CDCV857A is based on PLL circuitry, it requires a stabilization time to achieve phase-lock of the PLL. This stabilization time is required following power up. The CDCV857A is characterized for operation from 0°C to 85°C. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. MicroStar Junior is a trademark of Texas Instruments Incorporated. Copyright  2002, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 CDCV857A 2.5-V PHASE LOCK LOOP CLOCK DRIVER SCAS667A – APRIL 2001 – REVISED AUGUST 2002 44 6 43 7 42 8 41 9 40 10 39 11 38 12 37 13 36 14 35 15 34 16 33 17 32 18 31 19 30 20 29 21 28 22 27 23 26 24 25 2 Y5 GND V DDQ Y5 5 6 A Y1 Y1 B Y6 Y6 C NC GND GND Y2 Y2 VDDQ VDDQ CLK CLK D NC NC GND GND NC Y7 Y7 NC E F NC NC G NC NC H NC NC PWRDN VDDQ FBIN FBIN VDDQ FBOUT VDDQ AVDD AGND GND Y3 Y3 POST OFFICE BOX 655303 FBOUT GND J Y8 Y8 K • DALLAS, TEXAS 75265 Y9 45 5 4 Y9 4 3 GND 46 2 V DDQ 47 3 1 GND 2 GND Y5 Y5 VDDQ Y6 Y6 GND GND Y7 Y7 VDDQ PWRDWN FBIN FBIN VDDQ FBOUT FBOUT GND Y8 Y8 VDDQ Y9 Y9 GND V DDQ 48 Y4 1 Y4 GND Y0 Y0 VDDQ Y1 Y1 GND GND Y2 Y2 VDDQ VDDQ CLK CLK VDDQ AVDD AGND GND Y3 Y3 VDDQ Y4 Y4 GND V DDQ GND DGG PACKAGE (TOP VIEW) Y0 Y0 MicroStar Junior (GQL) Package (TOP VIEW) CDCV857A 2.5-V PHASE LOCK LOOP CLOCK DRIVER SCAS667A – APRIL 2001 – REVISED AUGUST 2002 FUNCTION TABLE (Select Functions) INPUTS OUTPUTS PLL AVDD GND PWRDWN CLK CLK Y[0:9] Y[0:9] FBOUT FBOUT H L H L H L H Bypassed/Off GND H H L H L H L Bypassed/Off X L L H Z Z Z Z Off X L H L Z Z Z Z Off 2.5 V (nom) H L H L H L H On 2.5 V (nom) H H L H L H L On 2.5 V (nom) X VDDQ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Continuous output current, IO (VO = 0 to VDDQ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Continuous current to GND or VDDQ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA Package thermal impedance, θJA (see Note 3): DGG package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89°C/W GQL package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137.6°C/W Storage temperature range Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. This value is limited to 3.6 V maximum. 3. The package thermal impedance is calculated in accordance with JESD 51. 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 CDCV857A 2.5-V PHASE LOCK LOOP CLOCK DRIVER SCAS667A – APRIL 2001 – REVISED AUGUST 2002 recommended operating conditions (see Note 4) MIN Supply voltage, VDDQ, AVDD TYP PWRDWN CLK, CLK, FBIN, FBIN High level input voltage, voltage VIH PWRDWN DC input signal voltage (see Note 5) V –0.3 VDDQ/2 – 0.18 0.7 V VDDQ/2 + 0.18 1.7 VDDQ + 0.3 VDDQ –0.3 Differential input signal voltage voltage, VID (see Note 6) DC CLK, FBIN 0.36 AC CLK, FBIN 0.7 Output differential cross-voltage, VOX (see Note 7) Input differential pair cross-voltage, VIX (see Note 7) UNIT 2.7 CLK, CLK, FBIN, FBIN Low level input voltage voltage, VIL MAX 2.3 VDDQ/2 – 0.2 VDDQ/2 – 0.2 High-level output current, IOH VDDQ + 0.6 VDDQ + 0.6 VDDQ/2 VDDQ/2 + 0.2 VDDQ/2 + 0.2 –12 Low-level output current, IOL V V V V V mA 12 mA Input slew rate, SR 1 4 V/ns Operating free-air temperature, TA 0 85 °C NOTES: 4. Unused inputs must be held high or low to prevent them from floating. 5. DC input signal voltage specifies the allowable dc execution of differential input. 6. Differential input signal voltage specifies the differential voltage |VTR – VCP| required for switching, where VTR is the true input level and VCP is the complementary input level. 7. Differential cross-point voltage is expected to track variations of VCC and is the voltage at which the differential signals must be crossing. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 CDCV857A 2.5-V PHASE LOCK LOOP CLOCK DRIVER SCAS667A – APRIL 2001 – REVISED AUGUST 2002 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MAX UNIT –1.2 V Input voltage VOH High level output voltage High-level VOL Low level output voltage Low-level IOH IOL VO Output voltage swing VOX Output differential cross-voltagew II Input current VDDQ = 2.7 V, VI = 0 V to 2.7 V ±10 µA IOZ High-impedance-state output current VDDQ = 2.7 V, VO= VDDQ or GND ±10 µA IDDPD Power down current on VDDQ + AVDD CLK and CLK = 0 MHz; PWRDWN = Low; Σ of IDD and AIDD 100 200 µA AIDD VDDQ = 2.3 V, II = –18 mA VDDQ = min to max, IOH = –1 mA TYP† VIK IDD All inputs MIN High-level output current VDDQ = 2.3 V, VDDQ = 2.3 V, IOL = 12 mA VO = 1 V Low-level output current VDDQ = 2.3 V, VO = 1.2 V Dynamic current on VDDQ Supply current on AVDD CI VDDQ– 0.1 1.7 VDDQ = 2.3 V, IOH = –12 mA VDDQ = min to max, IOL = 1 mA Differential outputs are terminated with 120 Ω V 0.1 V 0.6 –18 –32 mA 26 35 mA 1.1 VDDQ/2 – 0.2 VDDQ– 0.4 VDDQ/2 Differential outputs terminated with 120 Ω/CL = 14 pF fO = 180 MHz 275 330 fO = 167 MHz 250 300 Differential outputs terminated with 120 Ω/CL = 0 pF fO = 180 MHz 225 275 fO = 167 MHz 210 250 10 12 8 10 fO = 180 MHz fO = 167 MHz VCC = 2.5 V V VDDQ/2 + 0.2 mA mA Input capacitance VI = VCC or GND 2 2.5 3 pF CO Output capacitance VCC = 2.5 V VO = VCC or GND 2.5 3 3.5 pF † All typical values are at respective nominal VDDQ. ‡ The value of VOC is expected to be |VTR + VCP|/2. In case of each clock directly terminated by a 120-Ω resistor, where VTR is the true input signal voltage and VCP is the complementary input signal voltage. § Differential cross-point voltage is expected to track variations of VDDQ and is the voltage at which the differential signals must be crossing. timing requirements over recommended ranges of supply voltage and operating free-air temperature fCLK Operating clock frequency Application clock frequency Input clock duty cycle MIN MAX UNIT 60 180 MHz 40% 60% Stabilization timeW (PLL mode) 10 µs Stabilization timeW (Bypass mode) 30 ns ¶ Time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal. For phase lock to be obtained, a fixed-frequency, fixed-phase reference signal must be present at CLK. Until phase lock is obtained, the specifications for propagation delay, skew, and jitter parameters given in the switching characteristics table are not applicable. This parameter does not apply for input modulation under SSC application. 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 CDCV857A 2.5-V PHASE LOCK LOOP CLOCK DRIVER SCAS667A – APRIL 2001 – REVISED AUGUST 2002 switching characteristics PARAMETER tPLH} tPHL} tjit(per) jit( )w TEST CONDITIONS Low to high level propagation delay time Test mode/CLK to any output High-to low level propagation delay time Test mode/CLK to any output Jitter (period), (period) See Figure 6 tjit(cc) jit( )w Jitter (cycle-to-cycle), (cycle to cycle) See Figure 3 tjit(hper) jit(h )w Half period jitter Half-period jitter, See Figure 7 tslr(i) tslr(o) ns –35 35 ps 66 MHz –60 60 100/133/167/180 MHz –50 50 –100 100 –75 75 1 4 V/ns V/ns ps ps 1 2 66 MHz –180 180 100/133 MHz –130 130 167/180 MHz –90 90 66 MHz –230 230 100/133 MHz –170 170 167/180 MHz –100 100 66 MHz –150 150 100/133/167/180 MHz –100 100 75 ps 650 900 ps Dynamic phase offset ((this includes jjitter), y ), See Figure 4(b) SSC on tr, tf Output rise and fall times (20% – 80%) Load: 120 Ω/14 pF † All typical values are at a respective nominal VDDQ. ‡ Refers to transition of noninverting output. § This parameter is assured by design but can not be 100% production tested. ¶ All differential output pins are terminated with 120 Ω/14 pF. POST OFFICE BOX 655303 4.5 100/133/167/180 MHz Output clock slew rate, See Figure 8 Output skew, See Figure 5 ns ps Input clock slew rate, See Figure 8 tsk(o)W UNIT 55 100/133/167/180 MHz offset See Figure 4(a) Static phase offset, MAX 4.5 –55 66 MHz t(Ø) TYP{ 66 MHz SSC off td(Ø)w MIN • DALLAS, TEXAS 75265 ps ps 7 CDCV857A 2.5-V PHASE LOCK LOOP CLOCK DRIVER SCAS667A – APRIL 2001 – REVISED AUGUST 2002 PARAMETER MEASUREMENT INFORMATION VDD V(CLK) R = 60 Ω R = 60 Ω VDD/2 V(CLK) CDCV857 GND Figure 1. IBIS Model Output Load (used for slew rate measurement) VDD/2 C = 14 pF CDCV857A R = 10 Ω Z = 60 Ω SCOPE –VDD/2 Z = 50 Ω R = 50 Ω V(TT) Z = 60 Ω R = 10 Ω Z = 50 Ω R = 50 Ω V(TT) C = 14 pF –VDD/2 –VDD/2 NOTE: V(TT)= GND Figure 2. Output Load Test Circuit Yx, FBOUT Yx, FBOUT tc(n) tc(n+1) tjit(cc) = tc(n) – tc(n+1) Figure 3. Cycle-to-Cycle Jitter 8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 CDCV857A 2.5-V PHASE LOCK LOOP CLOCK DRIVER SCAS667A – APRIL 2001 – REVISED AUGUST 2002 PARAMETER MEASUREMENT INFORMATION CLK CLK FBIN FBIN t( ) n ∑1 t ( ) n+1 n=N t( ) = t( ) n N (N is a large number of samples) (a) Static Phase Offset CLK CLK FBIN FBIN t( ) td( ) t( ) td( ) td( ) td( ) (b) Dynamic Phase Offset Figure 4. Phase Offset Yx Yx Yx, FBOUT Yx, FBOUT tsk(o) Figure 5. Output Skew POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9 CDCV857A 2.5-V PHASE LOCK LOOP CLOCK DRIVER SCAS667A – APRIL 2001 – REVISED AUGUST 2002 PARAMETER MEASUREMENT INFORMATION Yx, FBOUT Yx, FBOUT tc(n) Yx, FBOUT Yx, FBOUT 1 fo tjit(per) = tcn – 1 fo Figure 6. Period Jitter Yx, FBOUT Yx, FBOUT t(hper_n+1) t(hper_n) 1 fo tjit(hper) = t(hper_n) – 1 2xfo Figure 7. Half-Period Jitter 80% 80% VID, VOD Clock Inputs and Outputs 20% 20% tslrr(i), tslrr(o) tslrf(i), tslrf(o) Figure 8. Input and Output Slew Rates 10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PACKAGE OPTION ADDENDUM www.ti.com 14-Oct-2022 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) CDCV857ADGG NRND TSSOP DGG 48 40 RoHS & Green NIPDAU Level-2-260C-1 YEAR 0 to 85 CDCV857A CDCV857ADGGG4 NRND TSSOP DGG 48 40 RoHS & Green NIPDAU Level-2-260C-1 YEAR 0 to 85 CDCV857A CDCV857ADGGR NRND TSSOP DGG 48 2000 RoHS & Green NIPDAU Level-2-260C-1 YEAR 0 to 85 CDCV857A (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of