Product
Folder
Sample &
Buy
Support &
Community
Tools &
Software
Technical
Documents
CDCVF2505
SCAS640G – JULY 2000 – REVISED AUGUST 2016
CDCVF2505 3.3-V Clock Phase-Lock Loop Clock Driver
1 Features
3 Description
•
The CDCVF2505 is a high-performance, low-skew,
low-jitter, phase-lock loop (PLL) clock driver. This
device uses a PLL to precisely align the output clocks
(1Y[0-3] and CLKOUT) to the input clock signal
(CLKIN) in both frequency and phase. The
CDCVF2505 operates at 3.3 V and also provides
integrated series-damping resistors that make it ideal
for driving point-to-point loads.
1
•
•
•
•
•
•
•
•
•
•
•
Phase-Lock Loop Clock Driver for Synchronous
DRAM and General-Purpose Applications
Spread Spectrum Clock Compatible
Operating Frequency: 24 MHz to 200 MHz
Low Jitter (Cycle-to-Cycle): < |150 ps|
(Over 66 MHz to 200 MHz Range)
Distributes One Clock Input to One Bank of Five
Outputs (CLKOUT Used to Tune the Input-Output
Delay)
Three-States Outputs When There Is No Input
Clock
Operates From Single 3.3-V Supply
Available in 8-Pin TSSOP and 8-Pin SOIC
Packages
Consumes Less Than 100 mA (Typical) in PowerDown Mode
Internal Feedback Loop Is Used to Synchronize
the Outputs to the Input Clock
25-Ω On-Chip Series Damping Resistors
Integrated RC PLL Loop Filter Eliminates the
Need for External Components
One bank of five outputs provides low-skew, low-jitter
copies of CLKIN. Output duty cycles are adjusted to
50 percent, independent of duty cycle at CLKIN. The
device automatically goes into power-down mode
when no input signal is applied to CLKIN.
The loop filter for the PLLs is included on-chip. This
minimizes the component count, space, and cost.
The CDCVF2505 is characterized for operation from
–40°C to 85°C.
Device Information(1)
PART NUMBER
CDCVF2505
PACKAGE
BODY SIZE (NOM)
SOIC (8)
4.90 mm × 3.90 mm
TSSOP (8)
4.40 mm × 3.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
2 Applications
•
•
•
Synchronous DRAMs
Industrial Applications
General-Purpose Zero-Delay Clock Buffers
Functional Block Diagram
8
CLKIN
1
PLL
25 W
3
25 W
CLKOUT
1Y0
2
1Y1
25 W
Power Down
5
25 W
7
25 W
Edge Detect
Typical VDD)
±50
mA
IOK
Output clamp current (VO < 0 or VO > VDD)
±50
mA
IO
Continuous total output current (VO = 0 to VDD)
±50
mA
Tstg
Storage temperature
150
°C
(1)
(2)
(3)
–65
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
This value is limited to 4.3 V maximum.
7.2 ESD Ratings
VALUE
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001
V(ESD)
(1)
(2)
Electrostatic discharge
(1)
UNIT
±2000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
±1000
Machine model (MM)
±300
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
3
3.3
3.6
UNIT
VDD
Supply voltage
VIH
High-level input voltage
VIL
Low-level input voltage
VI
Input voltage
VDD
V
IOH
High-level output current
–12
mA
IOL
Low-level output current
12
mA
TA
Operating free-air temperature
85
°C
0.7 VDD
V
V
0.3 VDD
0
–40
V
7.4 Thermal Information
CDCVF2505
THERMAL METRIC
(1)
D (SOIC)
PW (TSSOP)
8 PINS
8 PINS
UNIT
175.8
°C/W
RθJA
Junction-to-ambient thermal resistance (2)
112.3
RθJC(top)
Junction-to-case (top) thermal resistance
55.8
61.8
°C/W
RθJB
Junction-to-board thermal resistance
53.1
104.3
°C/W
ψJT
Junction-to-top characterization parameter
12.8
7.7
°C/W
ψJB
Junction-to-board characterization parameter
52.5
102.6
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
—
—
°C/W
(1)
(2)
4
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
The package thermal impedance is calculated in accordance with JESD 51.
Submit Documentation Feedback
Copyright © 2000–2016, Texas Instruments Incorporated
Product Folder Links: CDCVF2505
CDCVF2505
www.ti.com
SCAS640G – JULY 2000 – REVISED AUGUST 2016
7.5 Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
VIK
TEST CONDITIONS
Input voltage
MIN
II = –18 mA, VDD = 3 V
IOH = –100 µA, VDD = MIN to MAX
VOH
TYP (1)
High-level output voltage
Low-level output voltage
IOH = –12 mA, VDD = 3 V
2.1
IOH = –6 mA, VDD = 3 V
2.4
V
0.2
0.8
0.55
VO = 1 V, VDD = 3 V
IOL
Low-level output current
II
Input current
VI = 0 V or VDD
CI
Input capacitance
VI = 0 V or VDD, VDD = 3.3 V
(1)
V
IOH = 6 mA, VDD = 3 V
High-level output current
Output capacitance
–1.2
IOH = 12 mA, VDD = 3 V
IOH
Co
UNIT
VDD – 0.2
IOH = 100 µA, VDD = MIN to MAX
VOL
MAX
–27
VO = 1.65 V, VDD = 3.3 V
mA
–36
VO = 2 V, VDD = 3 V
27
VO = 1.65 V, VDD = 3.3 V
VI = 0 V or VDD, VDD = 3.3 V
V
mA
40
±5
µA
4.2
Yn
2.8
CLKOUT
5.2
pF
pF
All typical values are at respective nominal VDD and 25°C
7.6 Timing Requirements
over recommended operating free-air temperature range (unless otherwise noted)
MIN
TYP
MAX
UNIT
MHz
SUPPLY VOLTAGE, VDD = 3.3 V ±0.3 V
fclk
Clock frequency
Input clock duty cycle
24
200
24 MHz to 85 MHz (1)
30%
85%
86 MHz to 200 MHz
40%
50%
Stabilization time (2)
60%
100
µs
MHz
SUPPLY VOLTAGE, VDD = 2.7 V
fclk
Clock frequency
Input clock duty cycle
Stabilization time
(1)
(2)
42
166
42 MHz to 85 MHz (1)
30%
70%
86 MHz to 166 MHz
40%
(2)
50%
60%
100
µs
Assured by design but not 100% production tested
Time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal. For phase lock to be
obtained, a fixed-frequency, fixed-phase reference signal must be present at CLKIN. Until phase lock is obtained, the specifications for
propagation delay, skew, and jitter parameters given in the switching characteristics table are not applicable. This parameter does not
apply for input modulation under SSC application.
Submit Documentation Feedback
Copyright © 2000–2016, Texas Instruments Incorporated
Product Folder Links: CDCVF2505
5
CDCVF2505
SCAS640G – JULY 2000 – REVISED AUGUST 2016
www.ti.com
7.7 Switching Characteristics
over recommended ranges of supply voltage and operating free-air temperature, CL = 25 pF, VDD = 3.3 V ±0.3 V (1)
PARAMETER
TEST CONDITIONS
Propagation delay, normalized
(see Figure 2)
tpd
tsk(o)
Output skew
CLKIN to Yn, f = 66 MHz to 200 MHz
(3)
MAX
UNIT
150
ps
150
ps
f = 66 MHz to 200 MHz
70
150
f = 24 MHz to 50 MHz
200
400
Jitter (cycle-to-cycle)
(see Figure 4)
odc
Output duty cycle
(see Figure 3)
f = 24 MHz to 200 MHz at 50% VDD
tr
Rise time
tf
Fall time
(2)
(3)
–150
Yn to Yn
tc(jit_cc)
(1)
TYP (2)
MIN
ps
45%
55%
VO = 0.4 V to 2 V
0.5
2
ns
VO = 2 V to 0.4 V
0.5
2
ns
Time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal. For phase lock to be
obtained, a fixed-frequency, fixed-phase reference signal must be present at CLKIN. Until phase lock is obtained, the specifications for
propagation delay, skew, and jitter parameters given in the switching characteristics table are not applicable. This parameter does not
apply for input modulation under SSC application.
All typical values are at respective nominal VDD and 25°C
The tsk(o) specification is only valid for equal loading of all outputs.
7.8 Typical Characteristics
at 3.3 V, 25°C (unless otherwise noted)
500
150
tpd − Propagation Delay Time − ps
tpd − Propagation Delay Time − ps
Load: CLKOUT = 12 pF || 500 W,
Yn = 25 pF || 500 W
400
300
200
100
0
Load: CLKOUT = 21 pF || 500 W,
Yn = 25 pF || 500 W
100
50
0
−50
−100
−150
25
50
75
100
125
150
175
200
0
50
f − Frequency − MHz
200
Figure 2. tpd, Typical Propagation Delay Time
vs Frequency (Tuned for Minimum Delay)
500
55.0
Typical Values @ 3.3 V,
TA = 25°C
tc(jit_CC) − Cycle-to-Cycle Jitter − ps
Load: CLKOUT = 12 pF || 500 W,
Yn = 25 pF || 500 W
52.5
Duty Cycle − %
150
G003
Figure 1. tpd, Propagation Delay Time vs Frequency
50.0
47.5
400
300
200
100
0
45.0
25
50
75
100
125
150
175
200
25
50
75
100
125
150
175
200
f − Frequency − MHz
f − Frequency − MHz
G004
Figure 3. Duty Cycle vs Frequency
6
100
f − Frequency − MHz
G002
G005
Figure 4. Cycle-Cycle Jitter vs Frequency
Submit Documentation Feedback
Copyright © 2000–2016, Texas Instruments Incorporated
Product Folder Links: CDCVF2505
CDCVF2505
www.ti.com
SCAS640G – JULY 2000 – REVISED AUGUST 2016
8 Parameter Measurement Information
From Output Under Test
Yn = 25 pF || 500 W
CLKOUT = 12 pF || 500 W
500 W
S0283-01
Figure 5. Test Load Circuit
3V
50% VDD
CLKIN
0V
tpd
2V
1Y0–1Y3
0.4 V
tr
VOH
2V
50% VDD
0.4 V
VOL
tf
T0262-01
Figure 6. Voltage Threshold for Measurements, Propagation Delay (Tpd)
Any Y
50 % VDD
tsk(o)
Any Y
50 % VDD
T0263-01
Figure 7. Output Skew
tc1
tc2
tc(jit_CC) = tc1 – tc2
T0264-01
Figure 8. Cycle-to-Cycle Jitter
Submit Documentation Feedback
Copyright © 2000–2016, Texas Instruments Incorporated
Product Folder Links: CDCVF2505
7
CDCVF2505
SCAS640G – JULY 2000 – REVISED AUGUST 2016
www.ti.com
9 Detailed Description
9.1 Overview
The CDCVF2505 is designed for synchronous DRAM in server systems. This makes the device ideal for
applications which require the lowest possible skew between a provided reference clock and the clock copies
generated from the internal oscillator. At the same time, the phase-locked-loop has a high enough bandwidth to
track a spread-spectrum reference clock.
9.2 Functional Block Diagram
8
CLKIN
1
PLL
25 W
3
25 W
CLKOUT
1Y0
2
1Y1
25 W
Power Down
5
25 W
7
25 W
Edge Detect
Typical