CDCVF25081
SCAS671B – OCTOBER 2001 – REVISED JANUARY 2022
CDCVF25081 3.3-V Phased-Lock Loop Clock Driver
1 Features
3 Description
•
The CDCVF25081 is a high performance, low skew,
low jitter, phased-locked loop clock driver. It uses a
PLL to precisely align, in both frequency and phase,
the output clocks to the input clock signal. The outputs
are divided into 2 banks for a total of 8 buffered
CLKIN outputs. The device automatically puts the
outputs to a low state when no CLKIN signal is
present (power down mode).
•
•
•
•
•
•
•
•
Phase-locked loop based, zero-delay buffer
– 1 clock input to 2 banks of 4 outputs
– No external RC network required
Supply voltage: 3 V to 3.6 V
Operating frequency: 8 MHz to 200 MHz
Low additive jitter (cycle-cycle): ±100 ps for
66 MHz to 200 MHz
Power-down mode available
– Current consumption: < 20 µA in
Power-down mode
25-Ω on-chip series damping resistors
Industrial temperature range: –40°C to 85°C
Spread Spectrum Clock Compatible (SSC)
Packaged in
– 9.9-mm × 3.91-mm, 16-pin SOIC (D)
– 5.0-mm × 4.4-mm, 16-pin TSSOP (PW)
2 Applications
•
•
•
•
•
Defense radio
Production switchers and mixers
Radar
In-vitro diagnostics
CT & PET scanner
The S1 and S2 pins allow selection between PLL or
bypassed PLL outputs. When left open, the outputs
are disabled to a logic low state.
The part supports a fail-safe function. The device
further incorporates an input hysteresis which
prevents random oscillation of the outputs in the
absence of an input signal.
The device operates in 3.3V supply environment
and is characterized from –40°C to 85°C (ambient
temperature).
Device Information(1)
PART NUMBER
CDCVF25081
(1)
PACKAGE
BODY SIZE (NOM)
SOIC (16)
9.90 mm × 3.91 mm
TSSOP (16)
5.00 mm × 4.40 mm
For all available packages, see the orderable addendum at
the end of the data sheet.
2
1Y0
25 Ω
FBIN
CLKIN
16
1
PLL
M
U
X
3
1Y1
25 Ω
14
1Y2
25 Ω
15
1Y3
25 Ω
S2
S1
8
9
Input
Select
Decoding
6
2Y0
25 Ω
7
2Y1
25 Ω
10
2Y2
25 Ω
11
2Y3
25 Ω
Functional Block Diagram
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
CDCVF25081
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Table of Contents
1 Features............................................................................1
2 Applications..................................................................... 1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings........................................ 4
6.2 ESD Ratings............................................................... 4
6.3 Recommended Operating Conditions.........................4
6.4 Thermal Information....................................................5
6.5 Electrical Characteristics.............................................5
6.6 Timing Requirements.................................................. 5
6.7 Switching Characteristics............................................6
6.8 Typical Characteristics................................................ 7
7 Parameter Measurement Information............................ 8
8 Detailed Description......................................................10
8.1 Overview................................................................... 10
8.2 Functional Block Diagram......................................... 10
8.3 Feature Description...................................................11
8.4 Device Functional Modes..........................................11
9 Application and Implementation.................................. 12
9.1 Application Information............................................. 12
9.2 Typical Application.................................................... 12
10 Power Supply Recommendations..............................14
11 Layout........................................................................... 15
11.1 Layout Guidelines................................................... 15
11.2 Layout Example...................................................... 15
12 Device and Documentation Support..........................16
12.1 Documentation Support.......................................... 16
12.2 Receiving Notification of Documentation Updates..16
12.3 Support Resources................................................. 16
12.4 Trademarks............................................................. 16
12.5 Electrostatic Discharge Caution..............................16
12.6 Glossary..................................................................16
13 Mechanical, Packaging, and Orderable
Information.................................................................... 16
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (February 2003) to Revision B (January 2022)
Page
• Updated the numbering format for tables, figures, and cross-references throughout the document..................1
• Added ESD Ratings table, Thermal Information table, Feature Description section, Device Functional Modes,
Application and Implementation section, Power Supply Recommendations section, Layout section, Device
and Documentation Support section, and Mechanical, Packaging, and Orderable Information section............ 1
2
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5 Pin Configuration and Functions
CLKIN
1
16
FBIN
1Y0
2
15
1Y3
1Y1
3
14
1Y2
VDD
4
13
VDD
GND
5
12
GND
2Y0
6
11
2Y3
2Y1
7
10
2Y2
S2
8
9
S1
Not to scale
Figure 5-1. D or PW Package 16-Pin SOIC or TSSOP Top View
Table 5-1. Pin Functions
PIN
NAME
NO.
I/O TYPE(1)
DESCRIPTION
INPUT CLOCK
CLKIN
1
I
Clock input. CLKIN must have a fixed frequency and phase in order for the PLL
to acquire lock. Once the circuit is powered up and a valid signal is applied, a
stabilization time is required for the PLL to phase lock the feedback signal to
CLKIN.
9, 8
I
Input Selection. Selects input port. (See Table 8-2.)
16
I
Feedback input. FBIN provides the feedback signal to the internal PLL. FBIN must
be wired to one of the outputs to complete the feedback loop of the internal PLL.
The integrated PLL synchronizes the FBIN and output signal so there is nominally
zero-delay from input clock to output clock.
2
O
Bank 1 Y0 clock output with an integrated 25-Ω series-damping resistor.
1Y1
3
O
Bank 1 Y1 clock output with an integrated 25-Ω series-damping resistor.
1Y2
14
O
Bank 1 Y2 clock output with an integrated 25-Ω series-damping resistor.
1Y3
15
O
Bank 1 Y3 clock output with an integrated 25-Ω series-damping resistor.
2Y0
6
O
Bank 2 Y0 clock output with an integrated 25-Ω series-damping resistor.
2Y1
7
O
Bank 2 Y1 clock output with an integrated 25-Ω series-damping resistor.
2Y2
10
O
Bank 2 Y2 clock output with an integrated 25-Ω series-damping resistor.
2Y3
11
O
Bank 2 Y3 clock output with an integrated 25-Ω series-damping resistor.
INPUT SELECT
S1, S2
FEEDBACK
FBIN
OUTPUT CLOCKS
1Y0
SUPPLY VOLTAGE AND GROUND
VDD
4, 13
P
3.3V power supply for output channels and core voltage.
GND
5, 12
G
Ground. Connect ground pad to system ground.
(1)
The definitions below define the I/O type for each pin.
•
•
•
•
I = Input
O = Output
P = Power Supply
G = Ground
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
VDD
Power supply voltage
range(2) (3)
MIN
MAX
−0.5
4.6
UNIT
V
−0.5
4.6
V
−0.5
VDD, + 0.5
V
VI
Input voltage
VO
Output voltage range(2) (3)
IIK
Input clamp current (VI < 0)
-50
mA
IOK
Output clamp current (VO < 0)
-50
mA
IO
Continuous total output current (VO = 0 to VDD)
-50
θJA
Package thermal
impedance(4)
Tstg
Storage temperature
(1)
(2)
(3)
(4)
mA
PW package
D package
−65
147
°C/W
112
°C/W
150
°C
Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions.
If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully
functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.
The input and output negative voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
This value is limited to 4.6 V maximum.
The package thermal impedance is calculated in accordance with JESD 51.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC
JS-001, all pins(1)
±2000
Charged device model (CDM), per JEDEC
specification JESD22-C101, all pins(2)
±1000
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
MIN
Supply voltage, VDD
NOM
3
Low level input voltage, VIL
High level input voltage, VIH
2
Input voltage, VI
0
UNIT
3.6
V
0.8
V
V
3.6
V
High-level output current, IOH
-12
mA
Low-level output current, IOL
12
mA
85
°C
Operating free-air temperature, TA
4
3.3
MAX
–40
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6.4 Thermal Information
CDCVF25081
THERMAL
METRIC(1)
SOIC (D)
TSSOP (PW)
16 PINS
16 PINS
UNIT
RθJA
Junction-to-ambient thermal resistance
87.5
109.9
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
46.0
40.4
°C/W
RθJB
Junction-to-board thermal resistance
46.2
56.1
°C/W
ΨJT
Junction-to-top characterization parameter
11.7
3.6
°C/W
ΨJB
Junction-to-board characterization parameter
45.8
55.6
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report (SPRA953).
6.5 Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP(1)
MAX
UNIT
–1.2
V
VI = 0 V or VDD
±5
µA
fCLKIN = 0 MHz, VDD= 3.3 V
20
µA
±5
µA
VIK
Input voltage
VDD = 3 V, II = –18 mA
II
Input current
IPD (2)
Power down current
IOZ
Output 3-state
Vo = 0 V or VDD, VDD = 3.6 V
CI
Input capacitance at FBIN, CLKIN
VI = 0 V or VDD
4
pF
CI
Input capacitance at S1, S2
VI = 0 V or VDD
2.2
pF
CO
Output capacitance
VI= 0 V or VDD
3
pF
VOH
High-level output voltage
VDD = min to max, IOH = –100 µA
VDD – 0.2
VDD = 3 V, IOH = –12 mA
2.1
VDD = 3 V, IOH = –6 mA
2.4
V
VDD = min to max, IOL = 100 µA
VOL
Low-level output voltage
0.2
VDD = 3 V, IOL = 12 mA
0.8
VDD = 3 V, IOL = 6 mA
0.55
VDD = 3 V, VO = 1 V
IOH
High-level output current
–24
VDD = 3.3 V, VO = 1.65 V
–15
VDD = 3 V, VO = 1.95 V
26
VDD = 3.3 V, VO = 1.65 V
Low-level output current
mA
–30
VDD = 3.6 V, VO = 3.135 V
IOL
33
mA
VDD = 3.6 V, VO = 0.4 V
(1)
(2)
V
14
All typical values are at respective nominal VDD.
For IDD over frequency see Figure 9-2.
6.6 Timing Requirements
over recommended ranges of supply voltage, load, and operating free-air temperature
MIN
Clock frequency, fclk
NOM
MAX
CL = 25 pF
8
100
CL = 15 pF
66
200
UNIT
MHz
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6.7 Switching Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
t(lock)
PLL lock time
t(phoffset)
tPLH
MIN
f = 100 MHz
TYP(1)
MAX
10
–200
200
f = 66 MHz to 200 MHz,
Vth = VDD/2 (3)
–150
150
2.5
6
2.5
6
Low-to-high level output propagation delay S2 = High, S1 = Low (PLL bypass),
High-to-low level output propagation delay f = 1 MHz, CL = 25 pF
tsk(o)
Output skew (Yn to Yn) (2)
UNIT
µs
f = 8 MHz to 66 MHz,
Vth = VDD/2 (3)
tPHL
ps
150
S2 = high, S1 = high (PLL mode)
600
S2 = high, S1 = low (PLL bypass)
700
tsk(pp)
Part-to-part skew
f = 66 MHz to 200 MHz, CL = 15 pF
±100
tjit(cc)
Jitter (cycle-to-cycle)
f = 66 MHz to 100 MHz, CL = 25 pF,
f = 8 MHz to 66 MHz (see Figure 6-2)
±150
odc
Output duty cycle
f = 8 MHz to 200 MHz
tsk(p)
Pulse skew
S2 = High, S1 = low (PLL bypass),
f = 1 MHz, CL = 25 pF
tRISE
Rise time rate
tFALL
Fall time rate
(1)
(2)
(3)
6
Phase offset (CLKIN to FBIN)
TEST CONDITIONS
43%
ns
ps
ps
ps
57%
0.7
CL = 15 pF, See Figure 7-4
0.8
3.3
CL = 25 pF, See Figure 7-4
0.5
2
CL = 15 pF, See Figure 7-4
0.8
3.3
CL = 25 pF, See Figure 7-4
0.5
2
ns
V/ns
V/ns
All typical values are at respective nominal VDD.
The tsk(o)specification is only valid for equal loading of all outputs.
Similar waveform at CLKIN and FBIN are required. For phase displacement between CLKIN and Y-outputs see Figure 6-1.
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6.8 Typical Characteristics
Figure 6-1 captures the variation of the CDCVF25081 current consumption with capacitive load and phase displacement.
Figure 6-2 shows the variation of the cycle-to-cycle jitter across frequency.
.
Figure 6-1. Phase Displacement vs. Load
Figure 6-2. Cycle-to-Cycle Jitter vs. Frequency
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7 Parameter Measurement Information
VDD
1000 Ω
From Output Under Test
CL = 25 pF at f = 8 MHz to 100 MHz
CL = 15 pF at f = 66 MHz to 200 MHz
1000 Ω
NOTES: A. CL includes probe and jig capacitance.
B. All input pulses are supplied by generators having the following characteristics: ZO = 50 Ω, tr < 1.2 ns, tf < 1.2 ns.
C. The outputs are measured one at a time with one transition per measurement.
Figure 7-1. Test Load Circuit
VDD
50% VDD
CLKIN
0V
t(phoffset)
VOH
50% VDD
FBIN
VOL
Figure 7-2. Voltage Thresholds for Measurements, Phase Offset (PLL Mode)
50% VDD
Any Y
50% VDD
50% VDD
Any Y
t1
tsk(0)
tsk(0)
t2
NOTE: odc = t1/(t1 + t2) x 100%
Figure 7-3. Output Skew and Output Duty Cycle (PLL Mode)
8
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VDD
50% VDD
CLKIN
0V
tPLH
tPHL
80%
50% VDD
20%
80%
50% VDD
20%
Any Y
VOH
VOL
tr
tf
NOTE: tsk(p)=|tPLH-tPHL|
Figure 7-4. Propagation Delay and Pulse Skew (Non-PLL Mode)
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8 Detailed Description
8.1 Overview
The CDCVF25081 is a low jitter, low skew, phase-locked loop clock buffer solution. Unlike many products
containing PLLs, the CDCVF25081 does not require an external RC network. The loop filter for the PLL
is included on-chip, minimizing component count, space, and cost. Two banks of four outputs each provide
buffered copies of the CLKIN.
8.2 Functional Block Diagram
2
1Y0
25 Ω
FBIN
CLKIN
16
1
PLL
M
U
X
3
1Y1
25 Ω
14
1Y2
25 Ω
15
1Y3
25 Ω
S2
S1
8
9
Input
Select
Decoding
6
2Y0
25 Ω
7
2Y1
25 Ω
10
2Y2
25 Ω
11
2Y3
25 Ω
Figure 8-1. Functional Block Diagram
10
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8.3 Feature Description
The CDCVF25081 has an integrated PLL with a dedicated feedback pin (FBIN) for synchronization and zerodelay. FBIN must be directly routed to a clock output to complete the feedback loop. When no input is applied to
the CLKIN pin, the device powers down the outputs by setting them to a low logic level.
Because it is based on a PLL circuitry, the CDCVF25081 requires a stabilization time to achieve phase lock
of the feedback signal to the reference signal. This time is required following power up and application of a
fixed-frequency signal at CLKIN and any changes to the PLL reference.
Output duty cycles are adjusted to 50%, independent of duty cycle at CLKIN. Each output has an internal series
damping resistor of 25 ohms useful in driving point-to-point loads. Unused outputs can be left floating to reduce
overall system cost.
Table 8-1 lists the output bank mapping of the CDCVF25081.
Table 8-1. Output Bank Mapping
BANK
CLOCK OUTPUTS
0
1Y0, 1Y1, 1Y2, 1Y3
1
2Y0, 2Y1, 2Y2, 2Y3
8.4 Device Functional Modes
The CDCVF25081 operates from a 3.3-V supply. Table 8-2 shows the output logic states of the device based
on the selection pins. Based on the input selection pins (S1 and S2), the two output banks can be set as PLL
outputs, bypassed PLL outputs, or high impedance.
Table 8-2. Output Logic Table
(1)
S2
S1
Bank 1
Bank 2
0
0
OUTPUT SOURCE
PLL SHUTDOWN
0
Hi-Z
1
Active
Hi-Z
N/A
Yes
Hi-Z
PLL(1)
No
1
0
1
1
Active
Active
Input clock (PLL bypass)
Yes
Active
Active
PLL(1)
No
If CLKIN < 2 MHz, then the outputs are switched to a LOW level.
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9 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
9.1 Application Information
The CDCVF25081 is a low additive jitter, phase-locked loop driver that can operate up to 200 MHz with a 3.3-V
supply. The PLL circuitry is internal to device requiring no additional configuration by the user.
9.2 Typical Application
Data
Data
Memory
Controller
SDRAM
1Y0
CLKIN
SDRAM
2Y0
CDCVF25081
SDRAM
1Y1
2Y1
SDRAM
Figure 9-1. System Configuration Example
9.2.1 Design Requirements
Any output pin can be used to synchronize the FBIN to the outputs. TI recommends to not have a load on the
output routed to the FBIN pin for optimum results.
9.2.2 Detailed Design Procedure
Unused outputs can be left floating. See the Power Supply Recommendations section for recommended filtering
techniques.
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9.2.3 Application Curves
Figure 9-2. Supply Current vs. Frequency
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10 Power Supply Recommendations
High-performance clock buffers can be sensitive to noise on the power supply, which may dramatically increase
the additive jitter of the buffer. Thus, it is essential to manage any excessive noise from the system power
supply, especially for applications where the jitter and phase noise performance is critical.
Filter capacitors are used to eliminate the low-frequency noise from the power supply, where the bypass
capacitors provide the very low impedance path for high-frequency noise and guard the power supply system
against induced fluctuations. These bypass capacitors also provide instantaneous current surges as required
by the device and should have low equivalent series resistance (ESR). To properly bypass the supply, the
decoupling capacitors must be placed very close to the power-supply terminals, be connected directly to
the ground plane, and laid out with short loops to minimize inductance. TI recommends adding as many
high-frequency (for example, 0.1 µF) bypass capacitors, as there are supply terminals in the package. TI
recommends, but does not require, inserting a ferrite bead between the board power supply and the chip power
supply that isolates the high-frequency switching noises generated by the clock buffer. These beads prevent the
switching noise from leaking into the board supply. It is imperative to choose an appropriate ferrite bead with
very low DC resistance to provide adequate isolation between the board supply and the chip supply, as well
as to maintain a voltage at the supply terminals that is greater than the minimum voltage required for proper
operation.
Figure 10-1 shows the recommended power supply decoupling method.
Board
Supply
Chip
Supply
Ferrite Bead
10 μF
1 μF
0.1 μF (x2)
Figure 10-1. Power Supply Decoupling
14
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11 Layout
11.1 Layout Guidelines
Figure 11-1 shows a conceptual layout detailing recommended placement of power-supply bypass capacitors.
For component side mounting, use 0402 body size capacitors to facilitate signal routing. Keep the connections
between the bypass capacitors and the power supply on the device as short as possible. Ground the other side
of the capacitor using a low-impedance connection to the ground plane.
11.2 Layout Example
Ground bypass capacitor with low impedance
connection to ground plane
0402 or smaller body size capacitors are
recommended
Place bypass power supply capacitors as short
as possible to device pin
Figure 11-1. PCB Conceptual Layout
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12 Device and Documentation Support
TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device,
generate code, and develop solutions are listed below.
12.1 Documentation Support
12.1.1 Related Documentation
12.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
12.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
12.6 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
Samples
(4/5)
(6)
CDCVF25081D
ACTIVE
SOIC
D
16
40
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
CKV25081
Samples
CDCVF25081DR
ACTIVE
SOIC
D
16
2500
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
CKV25081
Samples
CDCVF25081PW
ACTIVE
TSSOP
PW
16
90
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
CK081
Samples
CDCVF25081PWG4
ACTIVE
TSSOP
PW
16
90
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
CK081
Samples
CDCVF25081PWR
ACTIVE
TSSOP
PW
16
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
CK081
Samples
CDCVF25081PWRG4
ACTIVE
TSSOP
PW
16
2000
RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 85
CK081
Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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