CGS2535TVX

OBSOLETE CGS2535TV, CGS2535V www.ti.com SNOS708C – JANUARY 2003 – REVISED APRIL 2013 CGS2535V/CGS2535TV Commercial Quad 1 to 4 Clock Drivers/Industrial Quad 1 to 4 Clock Drivers Check for Samples: CGS2535TV, CGS2535V FEATURES DESCRIPTION • These Clock Generation and Support clock drivers are specifically designed for driving memory arrays requiring large fanouts while operating at high speeds. 1 2 • • • • • • • • • • Ensured: – 1.0 ns Rise and Fall Times While Driving 12 Inches of 50Ω Microstrip Terminated with 25 pF – 350 ps Pin-to-Pin Skew (tOSLH and tOSHL) 650 ps Part-to-Part Variation on Positive or Negative Transition @ 5V VCC Operates with Either 3.3V or 5.0V Supply Inputs 5V Tolerant with VCC in 3.3V Range Symmetric Output Current Drive: 24 mA IOH/IOL Industrial Temperature Range −40°C to +85°C Symmetric Package Orientation Large Fanout for Memory Driving Applications Ensured 2 kV ESD Protection Implemented on TI's ABT Family Process 28-pin PLCC for Optimum Skew Performance The CGS2535 is a non-inverting 4 to 16 driver with CMOS I/O structures. The CGS2535 specification ensured part-to-part skew variation. Connection Diagrams Figure 1. Pin Assignment for 28-Pin PLCC Figure 2. CGS2535 Truth Table Input Output In (0–3) ABCD Out (0–3) 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2003–2013, Texas Instruments Incorporated OBSOLETE CGS2535TV, CGS2535V SNOS708C – JANUARY 2003 – REVISED APRIL 2013 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. Absolute Maximum Ratings (1) Supply Voltage (VCC) 7.0V Input Voltage (VI) 7.0V −30 mA Input Current Current Applied to Output (High/Low) Twice the Rated IOH/IOL Operating Temp. Comm. grade Storage Temperature Range (−65°C to +150°C) (1) −40°C to +85°C Industrial grade 0°C to +70°C Airflow Typical θJA 0 LFM 62°C/W 225 LFM 43°C/W 500 LFM 34°C/W 900 LFM 27°C/W The Absolute Maximum Ratings are those values beyond which the safety of the device cannot be ensured. The device should not be operated at these limits. The parametric values defined in the DC and AC Electrical Characteristics tables are not ensured at the absolute maximum ratings. The Recommended Operating Conditions will define the conditions for actual device operation. Recommended Operating Conditions VCC 4.75V to 5.25V Supply Voltage Maximum Input Rise/Fall Time Free Air Operating Temperature 2 Submit Documentation Feedback VCC 3.0V to 3.6V (0.8V to 2.0V) 5 ns Commercial 0°C to + 70°C −40°C to + 85°C Industrial Copyright © 2003–2013, Texas Instruments Incorporated Product Folder Links: CGS2535TV CGS2535V OBSOLETE CGS2535TV, CGS2535V www.ti.com SNOS708C – JANUARY 2003 – REVISED APRIL 2013 DC Electrical Characteristics Over recommended operating free air temperature range. All typical values are measured at VCC = 5V, TA = 25°C. Symbol VIH Parameter Conditions Input High Level Voltage VIL Input Low Level Voltage VCC (V) Min 3.0 2.1 4.5 3.15 5.5 3.85 4.5 1.35 5.5 1.65 −1.2 II = −18 mA 4.5 VOH High Level Output Voltage IOH = −50 μA 3.0 2.9 4.5 4.4 5.5 5.4 3.0 2.46 4.5 3.76 5.5 4.76 IOL = 50 μA Low Level Output Voltage V V V V 3.0 0.1 4.5 0.1 5.5 0.1 3.0 0.44 4.5 0.44 5.5 0.44 VIH = 7V 5.5 7 1 IOL = 24 mA Units V 0.9 Input Clamp Voltage VOL Max 3.0 VIK IOH = −24 mA Typ V V μA II Input Current @ Max Input Voltage VIH = VCC 3.6 IIH High Level Input Current VIH = VCC 5.5 IIL Low Level Input Current VIL = 0V 5.5 −5 μA IOLD Minimum Dynamic Output Current (1) VOLD = 1.65V (max) 5.5 75 mA VOLD = 0.9V (max) 3.0 (2) 36 IOHD (1) VOHD = 3.85V (min) 5.5 −75 VOHD = 2.1V (min) 3.0 (2) −25 ICC CIN (1) (2) Minimum Dynamic Output Current Supply Current Input Capacitance 5 mA 3.6 75 5.5 235 5.0 μA 5 μA pF Maximum test duration 2.0 ms, one output loaded at a time. At VCC = 3.3V, IOLD = 55 mA min; @ VCC = 3.6V, IOLD = 64 mA min At VCC = 3.3V, IOHD = −58 mA min; @ VCC = 3.6V, IOHD = −66 mA min Copyright © 2003–2013, Texas Instruments Incorporated Product Folder Links: CGS2535TV CGS2535V Submit Documentation Feedback 3 OBSOLETE CGS2535TV, CGS2535V SNOS708C – JANUARY 2003 – REVISED APRIL 2013 www.ti.com AC Electrical Characteristics (1) (2) (3) Over recommended operating free air temperature specified. All typical values are measured at VCC = 5V, TA = 25°C. CGS2535 Symbol VCC (V) (4) Parameter TA = −40°C to +85°C (5) TA = +25°C CL = 50 pF, RL = 500Ω Min Typ Max CL = 50 pF, RL = 500Ω Min 3.0 Typ Max fmax Frequency Maximum 100 tPLH Low-to-High Propagation Delay 3.3 4.5 2.5 4.5 CK to On @ 1 MHz (6) 5.0 3.5 2.0 3.5 High-to-Low Propagation Delay 3.3 4.5 2.5 4.5 CK to On @ 1 MHz (6) 5.0 3.5 2.0 3.5 3.3 5.0 2.5 5.0 5.0 tPHL tPLH Low-to-High Propagation Delay CK to On @ 66.67 MHz tPHL tOSLH (6) (7) MHz 125 5.0 4.5 2.0 4.5 High-to-Low Propagation Delay 3.3 5.0 2.5 5.0 CK to On @ 66.67 MHz (6) (7) 5.0 4.5 2.0 4.5 Maximum Skew Common Edge 3.3 150 350 300 350 Output-to-Output Variation (1) (3) 5.0 150 350 300 350 Maximum Skew Common Edge 3.3 150 350 300 350 Output-to-Output Variation (1) (3) 5.0 150 350 300 350 trise, Rise/Fall Time 3.3 3.5 3.5 tfall (from 0.8V/2.0V to 2.0V/0.8V) (8) 5.0 3.0 3.0 trise, Rise/Fall Time 3.3 0.8 1.0 tOSHL (7) (9) tfall (from 0.8V/2.0V to 2.0V/0.8V) 5.0 0.4 0.6 trise, Rise/Fall Time 3.3 1.0 1.0 tfall (from 0.8V/2.0V to 2.0V/0.8V) (7) (10) 5.0 0.7 0.9 tHigh Pulse Width Duration High (2) (3) (7) 3.3 4.0 4.0 5.0 4.0 4.0 tLow Pulse Width Duration Low (2) (3) (7) 3.3 4.0 4.0 5.0 4.0 4.0 tPVLH Units ns ns ns ns ps ps ns ns ns ns Part-to-Part Variation of Low-to-High Transitions @ 1 MHz (6) 3.3 650 1.0 ns 5.0 650 650 ps tPVHL Part-to-Part Variation of High-to-Low Transitions @ 1 MHz (6) 3.3 650 1.0 ns 5.0 650 650 ps tPVLH Part-to-Part Variation of Low-to-High Transitions @ 66.67 MHz (6) (7) 3.3 1.0 1.0 5.0 1.0 1.0 tPVHL Part-to-Part Variation of High-to-Low Transitions @ 66.67 MHz (6) (7) 3.3 1.0 1.0 5.0 1.0 1.0 ns (1) Output-to-Output Skew is defined as the absolute value of the difference between the actual propagation delay for any outputs within the same packaged device and output bank. The specifications apply to any outputs switching in the same direction either LOW to HIGH (tOSLH) or HIGH to LOW (tOSHL). (2) Time high is measured with outputs at 2.0V or above. Time low is measured with outputs at 0.8V or below. Input waveform characteristics for tHigh, tLow measurement: f = 66.67 MHz, duty cycle = 50%. (3) The input waveform has a rise and fall time transition time of 2.5 ns (10% to 90%). (4) Voltage Range 5.0 is 5.0V ± 0.25V, 3.3 is 3.3V ± 0.3V. (5) Industrial range (−40°C to +85°C) limits apply to the commercial temperature range (0°C to +70°C). (6) All 16 outputs switching simultaneously. (7) Ensured by design. (8) These Rise and Fall times are measured with CL = 50 pF, RL = 500Ω (see Figure 4). (9) These Rise and Fall times are measured with CL = 25 pF, RL = 500Ω (see Figure 4), and are ensured by design. (10) These Rise and Fall times are measured driving 12 inches of 50Ω microstrip terminated with equivalent CL = 25 pF (see Figure 5), and are ensured by design. 4 Submit Documentation Feedback Copyright © 2003–2013, Texas Instruments Incorporated Product Folder Links: CGS2535TV CGS2535V OBSOLETE CGS2535TV, CGS2535V www.ti.com SNOS708C – JANUARY 2003 – REVISED APRIL 2013 Timing Information Figure 3. These Rise and Fall times are measured with CL = 50 pF, RL = 500Ω (see Figure 4). These Rise and Fall times are measured with CL = 25 pF, RL = 500Ω (see Figure 4), and are ensured by design. Figure 4. A.C. Load CL = Total Load Including Probes These Rise and Fall times are measured driving 12 inches of 50Ω microstrip terminated with equivalent CL = 25 pF (see Figure 5), and are ensured by design. Figure 5. A.C. Load CL = Total Load Including Probes Copyright © 2003–2013, Texas Instruments Incorporated Product Folder Links: CGS2535TV CGS2535V Submit Documentation Feedback 5 OBSOLETE CGS2535TV, CGS2535V SNOS708C – JANUARY 2003 – REVISED APRIL 2013 www.ti.com CGS2534/35/36/37 MEMORY ARRAY DRIVING In order to minimize the total load on the address bus, quite often memory arrays are driven by buffers while having the inputs of the buffers tied together. Although this practice was feasible in the conventional memory designs, in today's high speed, large buswidth designs which require address fetching at higher speeds, this technique produces many undesired results such as cross-talk and over/undershoot. CGS2534/35/36/37 Quad 1 to 4 clock drivers were designed specifically to address these application issues on high speed, large memory arrays systems. These drivers are optimized to drive large loads, with 3.5 ns propagation delays. These drivers produce less noise while reducing the total capacitive loading on the address bus by having only four inputs tied together (see Figure 6, point A). This helps to minimize the overshoot and undershoot by having only four outputs being switched simultaneously. Also this larger fan-out helps to save board space since for every one of these drivers, two conventional buffers were typically being used. Another feature associated with these clock drivers is a 350 ps pin-to-pin skew specification. The minimum skew specification allows high speed memory system designers to optimize the performance of their memory subsystem by operating at higher frequencies without having concerns about output-to-output (bank-to-bank) synchronization problems which are associated with driving high capacitive loads (Point B). The diagram below depicts a “2534/35/36/37” a memory subsystem operating at high speed with large memory capacity. The address bus is common to both the memory and the CPU and I/Os. These drivers can operate beyond 125 MHz, and are also available in 3V–5V TTL/CMOS versions with large current drive . Figure 6. “2534/35/36/37" 6 Submit Documentation Feedback Copyright © 2003–2013, Texas Instruments Incorporated Product Folder Links: CGS2535TV CGS2535V OBSOLETE CGS2535TV, CGS2535V www.ti.com SNOS708C – JANUARY 2003 – REVISED APRIL 2013 Device VCC I/O 2534 5 TTL Output Configuration 2535 3 or 5 CMOS Non-inverting quad 1–4 2536 3 or 5 CMOS Inverting, Non-inverting, ÷2 2537 5 TTL Inverting quad 1–4 Inverting quad 1–4 with series 8Ω output resistors Part Numbering Information Copyright © 2003–2013, Texas Instruments Incorporated Product Folder Links: CGS2535TV CGS2535V Submit Documentation Feedback 7 OBSOLETE CGS2535TV, CGS2535V SNOS708C – JANUARY 2003 – REVISED APRIL 2013 www.ti.com REVISION HISTORY Changes from Revision B (April 2013) to Revision C • 8 Page Changed layout of National Data Sheet to TI format ............................................................................................................ 7 Submit Documentation Feedback Copyright © 2003–2013, Texas Instruments Incorporated Product Folder Links: CGS2535TV CGS2535V IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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