CLC007AJE/NOPB

CLC007 www.ti.com SNLS016E – JULY 1998 – REVISED APRIL 2013 CLC007 Serial Digital Cable Driver with Dual Complementary Outputs Check for Samples: CLC007 FEATURES DESCRIPTION • • • • • The Texas Instruments Comlinear CLC007 is a monolithic, high-speed cable driver designed for the SMPTE 259M serial digital video data transmission standard. The CLC007 drives 75Ω transmission lines (Belden 8281 or equivalent) at data rates up to 400 Mbps. Controlled output rise and fall times (750 ps typical) minimize transition-induced jitter. The output voltage swing, typically 1.65V, set by an accurate, low-drift internal bandgap reference, delivers an 800 mV swing to back-matched and terminated 75Ω cable. 1 2 No External Pull-Down Resistors Differential Input and Output Low Power Dissipation Single +5V or −5.2V Supply Replaces GS9007 in Most Applications APPLICATIONS • • • • • • Digital Routers and Distribution Amplifiers Coaxial Cable Driver for Digital Transmission Line Twisted Pair Driver Digital Distribution Amplifiers SMPTE, Sonet/SDH, and ATM Compatible Driver Buffer Applications KEY SPECIFICATION • • • • • The CLC007 is powered from a single +5V or −5.2V supply and comes in an 8-pin SOIC package. 650 ps Rise and Fall Times Data Rates to 400 Mbps 2 Sets of Complimentary Outputs 200 mV Differential Input Low Residual Jitter (25 pspp) 270 Mbps Eye Pattern 0 1 2 The CLC007’s class AB output stage consumes less power than other designs, 195 mW with all outputs terminated, and requires no external bias resistors. The differential inputs accept a wide range of digital signals from 200 mVP-P to ECL levels within the specified common-mode limits. All this make the CLC007 an excellent general purpose high speed driver for digital applications. Connection Diagram 3 4 5 TIME (1 ns/Div) Figure 1. Q0 1 8 VCC Q0 2 7 VIN+ Q1 3 6 VIN- Q1 4 5 VEE 6 Figure 2. 8-Pin SOIC See D Package 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 1998–2013, Texas Instruments Incorporated CLC007 SNLS016E – JULY 1998 – REVISED APRIL 2013 www.ti.com Typical Application VCC 75: 80.6: 80.6: 75: Coax 75: 8 7 1 + VIN+ 0.1 PF 2 75: 0.1 PF 75: Coax CLC007 6 VIN- 75: 3 4 75: 0.1 PF 75: Coax 5 133: 133: 75: 75: 0.1 PF 75: Coax VEE 75: These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ABSOLUTE MAXIMUM RATINGS (1) (2) Supply Voltage 6V Output Current 30 mA Maximum Junction Temperature +125°C −65°C to +150°C Storage Temperature Range Lead Temperature (Soldering 10 Second) +300°C ESD Rating (Human body Model) Package Thermal Resistance Reliability Information (1) (2) 1000V θJA 8–pin SOIC +160°C θJC 8–pin SOIC +105°C/W MTTF 254 Mhr Absolute Maximum Ratings are those values beyond which the safety of the device cannot be ensured. They are not meant to imply that the devices should be operated at these limits. The table of ELECTRICAL CHARACTERISTICS specifies conditions of device operation. If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and specifications. RECOMMENDED OPERATING CONDITIONS Supply Voltage (VCC – VEE) 2 +4.5V to +5.5V Submit Documentation Feedback Copyright © 1998–2013, Texas Instruments Incorporated Product Folder Links: CLC007 CLC007 www.ti.com SNLS016E – JULY 1998 – REVISED APRIL 2013 ELECTRICAL CHARACTERISTICS (VCC = 0V, VEE = −5V; unless otherwise specified). Parameter Conditions Typ +25°C Min/Max +25°C Min/Max 0°C to+70°C Min/Max −40°C to +85°C Units 39 — — — mA STATIC PERFORMANCE See (1) Supply Current, Unloaded See (2) 34 28/45 26/47 26/47 mA Output HIGH Voltage (VOH) See (2) −1.7 −2.0/1.4 −2.0/1.4 −2.0/1.4 V Output Low Voltage (VOL) See (2) −3.3 −3.6/3.0 −3.6/3.0 −3.6/3.0 V 10 30 50 50 μA See (2) 1.65 1.55/1.75 1.53/1.77 1.51/1.79 V Common Mode Input Range Upper Limit −0.7 −0.8 −0.8 −0.8 V Common Mode Input Range Lower Limit −2.6 −2.5 −2.5 −2.5 V Minimum Differential Input Swing 200 200 200 200 mV 26 20 20 20 dB 650 425/955 400/1100 400/1100 ps Supply Current, Loaded Input Bias Current Output Swing Power Supply Rejection Ratio (2) AC PERFORMANCE Output Rise and Fall Time See (1) (2) (3) Overshoot 5 % Propagation Delay 1.0 ns Duty Cycle Distortion 50 Residual Jitter 25 ps — — — pspp MISCELLANEOUS PERFORMANCE Input Capacitance 1.0 Output Resistance 10 Ω Output Inductance 6 nH (1) (2) (3) pF Measured with both outputs driving 150Ω, AC coupled at 270 Mbps. Spec is 100% tested at +25°C Measured between the 20% and 80% levels of the waveform. Submit Documentation Feedback Copyright © 1998–2013, Texas Instruments Incorporated Product Folder Links: CLC007 3 CLC007 SNLS016E – JULY 1998 – REVISED APRIL 2013 www.ti.com OPERATION Input Interfacing The CLC007 has high impedance, emitter-follower buffered, differential inputs. Single-ended signals may also be input. Transmission lines supplying input signals must be properly terminated close to the CLC007. Either A.C. or D.C. coupling as in Figure 4 or Figure 5 may be used. Figure 4, Figure 6, and Figure 7 show how Theveninequivalent resistor networks are used to provide input termination and biasing. The input D.C. common-mode voltage range is 0.8V to 2.5V below the positive power supply (VCC). Input signals plus bias should be kept within the specified common-mode range. For an 800 mVP-P input signal, typical input bias levels range from 1.2V to 2.1V below the positive supply. Resistor to VCC (R1) Resistor to VEE (R2) ECL, 50Ω, 5V, VT=2V Load Type 82.5Ω 124Ω ECL, 50Ω, 5.2V, VT=2V 80.6Ω 133Ω ECL, 75Ω, 5V, VT=2V 124Ω 187Ω ECL, 75Ω, 5.2V, VT=2V 121Ω 196Ω 800 mVP-P, 50Ω, 5V, VT=1.6V 75.0Ω 154Ω 800 mVP-P, 75Ω, 5V, VT=1.6V 110Ω 232Ω 800 mVP-P, 2.2 KΩ, 5V, VT=1.6V 3240Ω 6810Ω VCC VIN+ VIN- To next stage VEE Figure 3. Input Stage VCC VCC ECL Output Z0 R1 R1 0.1 PF 8 7 1 + 2 CLC007 6 VTT Z0 3 4 0.1 PF 5 R2 R2 VTT VEE VEE Figure 4. AC Coupled Input 4 Submit Documentation Feedback Copyright © 1998–2013, Texas Instruments Incorporated Product Folder Links: CLC007 CLC007 www.ti.com SNLS016E – JULY 1998 – REVISED APRIL 2013 VCC ECL Output Z0 8 7 1 + 2 CLC007 6 3 4 Z0 = Z0 5 = Z0 VTT VEE Figure 5. DC Coupled Input VCC R5 75: R4 75: R6 75: C1 0.1 PF J3 R7 75: C2 0.1 PF J4 R8 75: C3 0.1 PF J5 R9 75: C4 0.1 PF J6 8 7 4 + 3 CLC007 6 J2 VIN+ 2 1 R3 154: R1 154: 5 VEE Figure 6. Single Ended 50Ω ECL Input Submit Documentation Feedback Copyright © 1998–2013, Texas Instruments Incorporated Product Folder Links: CLC007 5 CLC007 SNLS016E – JULY 1998 – REVISED APRIL 2013 www.ti.com VCC R5 75: R4 75: C1 0.1 PF J3 R7 75: C2 0.1 PF J4 R8 75: C3 0.1 PF J5 R9 75: C4 0.1 PF J6 8 7 J1 VIN- R6 75: 4 + 3 CLC007 6 J2 VIN+ 2 1 R3 154: R1 154: 5 VEE Figure 7. Differential 50Ω ECL Input Output Interfacing The CLC007’s class AB output stage, Figure 8, requires no standing current in the output transistors and therefore requires no biasing or pull-down resistors. Advantages of this arrangement are lower power dissipation and fewer external components. The output may be either D.C. or A.C. coupled to the load. A bandgap voltage reference sets output voltage levels which are compatible with F100K and 10K ECL when correctly terminated. The outputs do not have the same output voltage temperature coefficient as 10K. Therefore, noise margins will be reduced over the full temperature range when driving 10K ECL. Noise margins will not be affected when interfacing to F100K since F100K is fully voltage and temperature compensated. VCC VEE VCC VEE Figure 8. Output Stage 6 Submit Documentation Feedback Copyright © 1998–2013, Texas Instruments Incorporated Product Folder Links: CLC007 CLC007 www.ti.com SNLS016E – JULY 1998 – REVISED APRIL 2013 VCC for 75: input: R1 = R3 = 232: R4 = R5 = 110: R6 75: R5 75: R4 75: 75: Coax J3 75: 8 J1 VIN+ 7 J2 VIN- 6 1 + 2 R7 75: 75: Coax J4 CLC007 4 R3 154: R1 154: 75: 3 R8 75: 5 75: R9 75: RIN = 50: VBIAS = VCC - 1.62V 75: Coax J5 75: Coax J6 VEE 75: VCC - VEE = +5V Figure 9. Differential Input DC Coupled Output Submit Documentation Feedback Copyright © 1998–2013, Texas Instruments Incorporated Product Folder Links: CLC007 7 CLC007 SNLS016E – JULY 1998 – REVISED APRIL 2013 www.ti.com Output Rise And Fall Times Output load capacitance can significantly affect output rise and fall times. The effect of load capacitance, stray or otherwise, may be reduced by placing the output back-match resistor close to the output pin and by minimizing all interconnecting trace lengths. Figure 10 shows the effect on risetime of parallel load capacitance across a 150Ω load. OUTPUT CAPACITANCE (pFd) 50 40 30 20 10 0 500 1000 1500 2000 2500 3000 RISE TIME (ps) Figure 10. Rise Time vs CL PCB Layout Recommendations Printed circuit board layout affects the performance of the CLC007. The following guidelines will aid in achieving satisfactory device performance. • Use a ground plane or power/ground plane sandwich design for optimum performance. • Bypass device power with a 0.01 µF monolithic ceramic capacitor in parallel with a 6.8 µF tantalum electrolytic capacitor located no more than 0.1” (2.5 mm) from the device power pins. • Provide short, symmetrical ground return paths for: – Inputs, – Supply bypass capacitors and – The output load. • Provide short, grounded guard traces located – Under the centerline of the package, – 0.1” (2.5 mm) from the package pins – On both top and bottom of the board with connecting vias. 8 Submit Documentation Feedback Copyright © 1998–2013, Texas Instruments Incorporated Product Folder Links: CLC007 CLC007 www.ti.com SNLS016E – JULY 1998 – REVISED APRIL 2013 REVISION HISTORY Changes from Revision D (April 2013) to Revision E • Page Changed layout of National Data Sheet to TI format ............................................................................................................ 8 Submit Documentation Feedback Copyright © 1998–2013, Texas Instruments Incorporated Product Folder Links: CLC007 9 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) CLC007BM/NOPB ACTIVE SOIC D 8 95 RoHS & Green SN Level-1-260C-UNLIM -40 to 85 CLC00 7BM>D CLC007BMX/NOPB ACTIVE SOIC D 8 2500 RoHS & Green SN Level-1-260C-UNLIM -40 to 85 CLC00 7BM>D (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of