CLC401
Fast Settling, Wideband High Gain Monolithic Op Amp
General Description
The CLC401 is a wideband, fast settling op amp designed
for applications requiring gains greater than ± 7. Constructed
using an advanced complementary bipolar process and a
proprietary design, the CLC401 features dynamic performance far beyond that of typical high speed monolithic op
amps. For example, at a gain of +20, the −3dB bandwidth is
150MHz and the rise/fall time is only 2.5ns.
The wide bandwidth and linear phase (0.2˚ deviation from
linear at 50MHz) and a very flat gain response makes the
CLC401 ideal for many digital communication system applications. For example, demodulators need both DC coupling
and high frequency amplification-requirements that are ordinarily difficult to meet.
The very fast 10ns settling to 0.1% and the ability to drive
capacitive loads lend themselves well to flash A/D applications. Systems employing D/A converters also benefit from
the settling time and also by the fact that current-to-voltage
transimpedance amplification is easily accomplished.
The CLC401 provides a quick, effective design solution. Its
stable operation over the entire ± 7 to ± 50 gain range precludes the need for external compensation. And, unlike
many other high speed-op amps, the CLC401’s power dissipation of 150mW is compatible with designs which must
limit total power dissipation or power supply requirements.
The CLC401 is based on National’s proprietary op amp
topology that uses current feedback instead of the usual
voltage feedback. This unique design has many advantages
over conventional designs (such as settling time that is
relatively independent of gain), yet it is used in basically the
same way (see the gain equations in Figure 1 and Figure 2).
However, an understanding of the topology will aid in achieving the best performance. The discussion below will proceed
for the non-inverting gain configuration with the inverting
mode analysis being very similar.
Enhanced Solutions (Military/Aerospace)
SMD Number: 5962-89973
Space level versions also available.
For more information, visit http://www.national.com/mil
Features
n
n
n
n
n
n
−3dB bandwidth of 150MHz
0.1% settling in 10ns
Low power, 150mW
Overload and short circuit protected
Stable without compensation
Recommended gain range, ± 7 to ± 50
Applications
n
n
n
n
n
n
n
Flash, precision A/D conversion
Photodiode, CCD preamps
IF processors
High speed modems, radios
Line drivers
DC coupled log amplifiers
High speed communications
Pulse Response
DS012744-18
Connection Diagram
DS012744-17
Pinout
DIP & SOIC
© 2001 National Semiconductor Corporation
DS012744
www.national.com
CLC401 Fast Settling, Wideband High Gain Monolithic Op Amp
February 2001
CLC401
Connection Diagram
(Continued)
DS012744-1
Non-Inverting
Frequency Response
Ordering Information
Package
Temperature Range
Industrial
Part Number
Package
Marking
NSC
Drawing
8-pin plastic DIP
−40˚C to +85˚C
CLC401AJP
CLC401AJP
N08E
8-pin plastic SOIC
−40˚C to +85˚C
CLC401AJE
CLC401AJE
M08A
www.national.com
2
Junction Temperature Range
Operating Temperature Range
Storage Temperature Range
Lead Solder Duration (+300˚C)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
± 7V
Supply Voltage (VCC)
IOUT
Output is short circuit protected to
ground, but maximum reliability will
be maintained if IOUT does not
exceed...
Common Mode Input Voltage
Differential Input Voltage
+150˚C
−40˚C to +85˚C
−65˚C to +150˚C
10 sec
Operating Ratings
Thermal Resistance
Package
(θJC)
MDIP
70˚C/W
SOIC
65˚C/W
60mA
± VCC
5V
(θJA)
125˚C/W
145˚C/W
Electrical Characteristics
(AV = +20, VCC = ± 5V, RL = 100Ω, Rf =1.5kΩ; unless specified).
Symbol
Parameter
Ambient Temperature
Conditions
CLC401AJ
Typ
Max/Min Ratings
(Note 2)
Units
+25˚C
−40˚C
+25˚C
+85˚C
VOUT < 2VPP
150
100
> 100
> 65
> 70
> 55
MHz
VOUTt < 5VPP
> 100
> 65
< 0.1
< 0.2
< 1.0
< 1.0
< 0.1
< 0.2
< 1.0
< 1.0
< 0.1
< 0.2
< 1.3
< 1.5
dB
< 3.5
< 7.0
< 15
< 10
> 800
< 3.5
< 7.0
< 15
< 10
> 800
< 5.0
< 8.0
< 15
< 10
> 700
Frequency Domain Response
SSBW
−3dB Bandwidth
LSBW
Gain Flatness
GFPL
Peaking
GFPH
Peaking
GFR
Rolloff
LPD
Linear Phase Deviation
MHz
VOUT < 2VPP
< 25MHz
> 25MHz
< 50MHz
0.2
DC to 50MHz
0.2
0
0
dB
dB
deg
Time Domain Response
TRS
Rise and Fall Time
TRL
2V Step
2.5
5V Step
5
10
TS
Settling Time to ± 0.1%
2V Step
OS
Overshoot
2V Step
SR
Slew Rate
0
1200
ns
ns
ns
%
V/µs
Distortion And Noise Response
HD2
2nd Harmonic Distortion
2VPP, 20MHz
−45
3rd Harmonic Distortion
2VPP, 20MHz
−60
< −35
< −50
< −35
< −50
< −35
< −45
dBc
HD3
−158
< −155
< −155
< −154
dBm
(1Hz)
35
< 50
< 50
< 55
µV
3
± 6.0
100
± 10.0
± 50
± 36
± 200
–
± 11.0
± 50
± 20
± 100
nA/˚C
10
46
30
40
µA
dBc
Equivalent Input Noise
SNF
Noise Floor
> 1MHz
INV
Integrated Noise
1MHz to 150MHz
Static, DC Performance
VIO
DVIO
IBN
DIBN
IBI
Input Offset Voltage (Note 3)
Average Temperature Coefficient
Input Bias Current (Note 3)
20
Non-Inverting
10
Average Temperature Coefficient
Input Bias Current (Note 3)
Inverting
–
± 20
mV
µV/˚C
µA
100
± 200
–
± 100
nA/˚C
PSRR
Power Supply Rejection Ratio
55
50
50
50
dB
CMRR
Common Mode Rejection Ratio
55
50
50
50
dB
ICC
Supply Current (Note 3)
No Load
15
21
21
21
mA
> 50
< 2.5
< 0.3
> 3.0
> 100
< 2.5
< 0.3
> 3.2
> 100
< 2.5
< 0.3
> 3.2
kΩ
DIBI
Average Temperature Coefficient
Miscellaneous Performance
RIN
Non-Inverting Input
CIN
Resistance
200
Capacitance
0.5
RO
Output Impedance
at DC
0.2
VO
Output Voltage Range
No Load
3.5
3
pF
Ω
V
www.national.com
CLC401
Absolute Maximum Ratings (Note 1)
CLC401
Electrical Characteristics
(Continued)
(AV = +20, VCC = ± 5V, RL = 100Ω, Rf =1.5kΩ; unless specified).
Symbol
Parameter
Conditions
Typ
Max/Min Ratings
(Note 2)
Units
Miscellaneous Performance
CMIR
Common Mode Input Range
IO
Output Current
For Rated Performance
2.8
60
> 2.0
> 35
> 2.5
> 50
> 2.5
> 50
V
mA
Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices
should be operated at these limits. The table of “Electrical Characteristics” specifies conditions of device operation.
Note 2: Max/min ratings are based on product characterization and simulation. Individual parameters are tested as noted. Outgoing quality levels are determined
from tested parameters.
Note 3: AJ-level: spec. is 100% tested at +25˚C.
Typical Performance Characteristics
(TA = 25˚, AV = +20, VCC = ± 5V, RL = 100Ω: Unless
Specified).
Non-Inverting Frequency Response
Inverting Frequency Response
DS012744-1
Frequency Response for Various RLs
DS012744-2
Open-Loop Transimpedance Gain, Z(s)
DS012744-3
DS012744-4
www.national.com
4
(TA = 25˚, AV = +20, VCC = ± 5V, RL = 100Ω: Unless
Specified).. (Continued)
2nd and 3rd Harmonic Distortion
2-Tone,3rd Order, Intermodulation Intercept
DS012744-6
DS012744-5
Equivalent Input Noise
CMRR and PSRR
DS012744-8
DS012744-7
Pulse Response
Settling Time
DS012744-19
DS012744-18
5
www.national.com
CLC401
Typical Performance Characteristics
CLC401
Typical Performance Characteristics
(TA = 25˚, AV = +20, VCC = ± 5V, RL = 100Ω: Unless
Specified).. (Continued)
Long-Term Settling Time
Settling Time vs. Load Capacitance
DS012744-9
DS012744-20
Recommended RS vs. Load Capacitance
Low Gain & Transimpedance Applications
DS012744-21
DS012744-13
Frequency Response, AV = −1, Rf = 2.25kΩ
DS012744-14
www.national.com
6
CLC401
Equation 1
Application Division
where LG is the loop gain defined by,
Equation 2
Equation 1 has a form identical to that for a voltage feedback
amplifier with the differences occurring in the LG expression.
For an idealized treatment, set Zi =0 which results in a very
simple LG = Z(s)/Rf(Derivation of the transfer function for the
case where Zi = 0 is given in Application Note AN300-1).
Using the Z(s) (open-loop transimpedance gain) plot shown
on the previous page and dividing by the recommended Rf =
1.5kΩ, yields a large loop gain at DC. As a result, Equation
1 shows that the closed-loop gain at DC is very close to
(1+Rf/Rg).
At higher frequencies, the roll-off of Z(s) determines the
closed-loop frequency response which, ideally, is dependent
only on Rf. The specifications reported on the previous
pages are therefore valid only for the specified R =
1.5kΩ. Increasing R from 1.5kΩ will decrease the loop gain
and band width, while decreasing it will increase the loop
gain possibly leading to inadequate phase margin and
closed-loop peaking. Conversely, fixing Rf will hold the frequency response constant while the closed-loop gain can be
adjusted using Rg.
The CLC401 departs from this idealized analysis to the
extent that the inverting input impedance is finite. With the
low quiescent power of the CLC401, Z = 50Ω leading to drop
in loop gain and bandwidth at high gain settlings, as given by
Equation 2. The second term is Equation 2 accounts for the
division in feedback current that occurs between Zi and
Rf\Rg at the inverting node of the CLC400. This decrease in
bandwidth can be circumvented as described in “Increasing
Bandwidth at High Gains.”
DC Accuracy and Noise
Since the two inputs for the CLC401 are quite dissimilar, the
noise and offset error performance differs somewhat from
that of a standard differential input amplifier. Specifically, the
inverting input current noise is much larger than the
non-inverting current noise. Also the two input bias currents
are physically unrelated rendering bias current cancellation
through matching of the inverting and non-inverting pin resistors ineffective.
In Equation 3, the output offset is the algebraic sum of the
equivalent input voltage and current sources that influence
DC operation. Output noise is determined similarly except
that a root-sum-of-squares replaces the algebraic sum. Rs is
the non-inverting pin resistance.
Equation 3
Output Offset VO = ± IBN x RS (1+ Rf/Rg) ±
VIO (1+ Rf/Rg) ± IBI x Rf
DS012744-15
FIGURE 1. Recommended Non-Inverting Gain Circuit
DS012744-16
FIGURE 2. Recommended Inverting Gain Circuit
Understanding the Loop Gain
Referring to the equivalent circuit of Figure 3, any current
flowing in the inverting input is amplified to a voltage at the
output through the transimpedance gain shown on the plots
on page 3. This Z(s) is analogous to the open-loop gain of a
voltage feedback amplifier.
DS012744-22
FIGURE 3. Current feedback topology
Developing the non-inverting frequency response for the
topology of Figure 3 yields:
An important observation is that for fixed Rf, offsets as
referred to the input improve as the gain is increased (divide
all terms by 1+Rf/Rg). A similar result is obtained for noise
where noise figure improves as gain increases.
Selecting Between the CLC400 or CLC401
7
www.national.com
CLC401
Application Division
Capacitive Feedback
(Continued)
Capacitive feedback should not be used with the CLC401
because of the potential for loop instability. See Application
Note OA-7 for active filter realizations with the CLC401.
The CLC400 is intended for gains of ± 1 to ± 8 while the
CLC401 is designed for gains of ± 7 to ± 50. Optimum performance is achieved with a feedback resistor of 250Ω with the
CLC400 and 1.5Ω with the CLC401- this distinction may be
important in transimpedance applications such as D/A buffering. Although the CLC400 can be used at higher gains, the
CLC401 will provide a wider bandwidth because loop gain
losses due to finite Zi are lower with the larger CLC401
feedback resistor as explained above. On the other hand,
the lower recommended feedback resistance of the CLC400
minimizes the output errors due to inverting input noise and
bias currents.
Increasing Bandwidth At High Gains
Bandwidth may be increased at high closed-loop gains by
adjusting Rf and Rgto make up for the losses in loop gain that
occur at these high gain settlings due to current division at
the inverting input. An approximate relationship my be obtained by holding the LG expression constant as the gain is
changed from the design point used in the specifications
(that is, Rf = 1.5kΩ and Rg = 79Ω). For the CLC401 this
gives,
Equation 4
Printed Circuit Layout
As with any high frequency device, a good PCB layout will
enhance performance. Ground plane construction and good
power supply bypassing close to the package are critical to
achieving full performance. In the non-inverting configuration, the amplifier is sensitive to stray capacitance to ground
at the inverting input. Hence, the inverting node connections
should be small with minimal coupling to the ground plane.
Shunt capacitance across the feedback resistor should not
be used to compensate for this effect.
Parasitic or load capacitance directly on the output will introduce additional phase shift in the loop degrading the loop
phase margin and leading to frequency response peaking. A
small series resistor before the capacitance effectively decouples this effect. The graphs on the preceding page illustrate the required resistor value and resulting performance
vs. capacitance.
Precision buffed resistors (PRP8351 series from Precision
Resistive Products) with low parasitic reactances were used
to develop the data sheet specifications. Precision carbon
composition resistors will also yield excellent results. Standard spirally-trimmed RN55D metal film resistors will work
with the slight decrease in bandwidth due to their reactive
nature at high frequencies.
Evaluation PC boards (part no. CLC730013 for through-hole
and CLC730027 for SOIC) for the CLC401 are available.
where AVis the desired non-inverting gain. Note that with AV
= +20 we get the specified Rf = 1.5kΩ, while at higher gains,
a lower value gives stable performance with improved bandwidth.
www.national.com
8
CLC401
Physical Dimensions
inches (millimeters) unless otherwise noted
NS Product Number M08A
NS Product Number N08E
9
www.national.com
CLC401 Fast Settling, Wideband High Gain Monolithic Op Amp
Notes
LIFE SUPPORT POLICY
NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL
COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant
into the body, or (b) support or sustain life, and
whose failure to perform when properly used in
accordance with instructions for use provided in the
labeling, can be reasonably expected to result in a
significant injury to the user.
National Semiconductor
Corporation
Americas
Tel: 1-800-272-9959
Fax: 1-800-737-7018
Email: support@nsc.com
www.national.com
National Semiconductor
Europe
Fax: +49 (0) 180-530 85 86
Email: europe.support@nsc.com
Deutsch Tel: +49 (0) 69 9508 6208
English Tel: +44 (0) 870 24 0 2171
Français Tel: +33 (0) 1 41 91 8790
2. A critical component is any component of a life
support device or system whose failure to perform
can be reasonably expected to cause the failure of
the life support device or system, or to affect its
safety or effectiveness.
National Semiconductor
Asia Pacific Customer
Response Group
Tel: 65-2544466
Fax: 65-2504466
Email: ap.support@nsc.com
National Semiconductor
Japan Ltd.
Tel: 81-3-5639-7560
Fax: 81-3-5639-7507
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.
National P/N CLC401 - Fast Settling, Wideband High Gain Monolithic Op Amp
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CLC401
Fast Settling, Wideband High Gain Monolithic Op Amp
Generic P/N 401
Contents
Parametric Table
Channels (Channels)
1
●
General Description
Input Output Type
Not Rail to Rail
●
Features
Bandwidth, typ (MHz)
179
●
Applications
Slew Rate, typ (Volts/usec)
1200
●
Datasheet
Supply Current per Channel, typ (mA) 15
●
Package Availability, Models, Samples &
Pricing
Minimum Supply Voltage (Volt)
10
Maximum Supply Voltage (Volt)
14
●
Design Tools
Offset Voltage, Max (mV)
6
●
Application Notes
Input Bias Current, Temp Max (nA)
36000
Output Current, typ (mA)
70
Voltage Noise, typ (nV/Hz)
2.40
Shut down
No
Feedback Type
Current
BW at Av+5 (MHz)
179
BW at Av+10 (MHz)
167
BW at Av+20 (MHz)
150
HD 2nd, typ (dB)
-45
HD 3rd, typ (dB)
-60
Settling Time
10nS to 0.1%
Special Features
AvCl>7
General Description
file:///F|/cpl_new_images/CLC401.html (1 of 4) [7/18/2001 5:50:26 PM]
National P/N CLC401 - Fast Settling, Wideband High Gain Monolithic Op Amp
The CLC401 is a wideband, fast settling op amp designed for applications requiring gains greater than ±7.
Constructed using an advanced complementary bipolar process and a proprietary design, the CLC401
features dynamic performance far beyond that of typical high speed monolithic op amps. For example, at
a gain of +20, the -3dB bandwidth is 150MHz and the rise/fall time is only 2.5ns.
The wide bandwidth and linear phase (0.2° deviation from linear at 50MHz) and a very flat gain response
makes the CLC401 ideal for many digital communication system applications. For example,
demodulators need both DC coupling and high frequency amplification-requirements that are ordinarily
difficult to meet.
The very fast 10ns settling to 0.1% and the ability to drive capacitive loads lend themselves well to flash
A/D applications. Systems employing D/A converters also benefit from the settling time and also by the
fact that current-to-voltage transimpedance amplification is easily accomplished.
The CLC401 provides a quick, effective design solution. Its stable operation over the entire ±7 to ±50
gain range precludes the need for external compensation. And, unlike many other high speed-op amps, the
CLC401's power dissipation of 150mW is compatible with designs which must limit total power
dissipation or power supply requirements.
The CLC401 is based on National's proprietary op amp topology that uses current feedback instead of the
usual voltage feedback. This unique design has many advantages over conventional designs (such as
settling time that is relatively independent of gain), yet it is used in basically the same way (see the gain
equations in and ). However, an understanding of the topology will aid in achieving the best performance.
The discussion below will proceed for the non-inverting gain configuration with the inverting mode
analysis being very similar.
Enhanced Solutions (Military/Aerospace)
SMD Number: 5962-89973
Space level versions also available.
For more information, visit http://www.national.com/mil
Features
●
●
●
●
●
●
-3dB bandwidth of 150MHz
0.1% settling in 10ns
Low power, 150mW
Overload and short circuit protected
Stable without compensation
Recommended gain range, ±7 to ±50
Applications
●
●
●
●
●
●
●
Flash, precision A/D conversion
Photodiode, CCD preamps
IF processors
High speed modems, radios
Line drivers
DC coupled log amplifiers
High speed communications
file:///F|/cpl_new_images/CLC401.html (2 of 4) [7/18/2001 5:50:26 PM]
National P/N CLC401 - Fast Settling, Wideband High Gain Monolithic Op Amp
Datasheet
Size
(in
Kbytes)
Title
CLC401 Fast Settling, Wideband High Gain Monolithic Op
Amp
CLC401 Fast Settling, Wideband High Gain Monolithic Op
Amp (JAPANESE)
CLC401 Mil-Aero Datasheet MNCLC401A-X
Date
View Online
279
14-Nov-00 View Online
Kbytes
339
Kbytes
View Online
59
Kbytes
View Online
Download
Download
Download
Download
Receive via
Email
Receive via
Email
Receive via Email
Receive via
Email
Please use Adobe Acrobat to view PDF file(s).
If you have trouble printing, see Printing Problems.
Package Availability, Models, Samples & Pricing
Package
Part Number
CLC401AJE
Type
SOIC
NARROW
SOIC
CLC401AJE-TR13
NARROW
CLC401AJP
MDIP
Models
#
pins
8
Status
SPICE IBIS
Full
clc401.cir N/A
production
8
Full
clc401.cir N/A
production
8
Full
clc401.cir N/A
production
5962-8997301PA
Cerdip
8
Full
clc401.cir N/A
production
CLC401AJ
Cerdip
8
Full
clc401.cir N/A
production
CLC401AD-MLS
SB Cerdip
8
Full
clc401.cir N/A
production
CLC401AJ-MLS
Cerdip
8
Full
clc401.cir N/A
production
file:///F|/cpl_new_images/CLC401.html (3 of 4) [7/18/2001 5:50:26 PM]
Samples
&
Electronic
Orders
Budgetary Pricing Std
Pack
Quantity $US each Size
1K+
$3.6500
tube
of
95
[logo]¢2¢T
CLC40
1AJE
1K+
reel
$3.6800 of
2500
[logo]¢2¢T
CLC40
1AJE
1K+
$3.6500
Samples
Buy Now
Buy Now
Samples
Buy Now
Buy Now
Package
Marking
25+
500+
50+
tube
of
40
[logo]¢U¢Z¢2¢T
CLC401AJP
[logo]¢Z¢S¢4¢A$E
tube
CLC401AJ-QML
$29.1000 of
5962-8997301
40
PA
tube
[logo]¢U¢Z¢2¢T¢P
$17.8000 of
CLC401AJ
40
tube [logo]¢Z¢S¢4¢A
of
CLC401AD
N/A
-MLS $E
tube
[logo]¢Z¢S¢4¢A$E
$220.0000 of
CLC401AJ-MLS
40
National P/N CLC401 - Fast Settling, Wideband High Gain Monolithic Op Amp
Design Tools
Size
(in Kbytes)
Title
Amplifiers Selection Guide software for Windows 9 Kbytes
Date
View Online Download Receive via Email
View
19-Mar-2001
CLC730013EB 8-pin Op Amp Evaluation Board 130 Kbytes 2-Jan-2001
View Online Download Receive via Email
CLC730027EB 8-pin Op Amp Evaluation Board 130 Kbytes 2-Jan-2001
View Online Download Receive via Email
Please use Adobe Acrobat to view PDF file(s).
If you have trouble printing, see Printing Problems.
Application Notes
Size
(in Kbytes)
Title
OA-07: OA-07 Current- Feedback Op Amp Applications
Circuit Guide
OA-11: OA-11 A Tutorial on Applying Op Amps to RF
Applications
Date
View Online Download Receive via Email
308 Kbytes 28-Oct-96 View Online Download Receive via Email
769 Kbytes 2-Apr-99
View Online Download Receive via Email
OA-12: OA-12 Noise Analysis for Comlinear's Op Amps
108 Kbytes 24-Feb-99 View Online Download Receive via Email
OA-13: OA-13 Current- Feedback Loop Gain Analysis
527 Kbytes 28-Oct-96 View Online Download Receive via Email
OA-14: OA-14 Improving Amplifier Noise Figure for High
92 Kbytes 15-Dec-00 View Online Download
3rd Intercept Amplifiers
OA-15: OA-15 Frequent Faux Pas in Applying Wideband
527 Kbytes 28-Jan-99 View Online Download
Current Feedback Amplifiers
OA-18: OA-18 Simulation SPICE Models for Comlinear's Op
337 Kbytes 23-May-00 View Online Download
Amps
OA-20: OA-20 Current Feedback Myths Debunked
139 Kbytes 10-Jul-97 View Online Download
Receive via Email
Receive via Email
Receive via Email
Receive via Email
OA-25: OA-25 Stability Analysis of Current Feedback
Amplifier
262 Kbytes 10-Oct-96 View Online Download Receive via Email
OA-30: OA-30 Current vs. Voltage Feedback Amplifiers
56 Kbytes
5-Jun-98
View Online Download Receive via Email
Please use Adobe Acrobat to view PDF file(s).
If you have trouble printing, see Printing Problems.
[Information as of 25-Apr-2001]
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