CLC5526MSA/NOPB

CLC5526 www.ti.com SNOS914E – JUNE 1999 – REVISED MARCH 2013 CLC5526 Digital Variable Gain Amplifier (DVGA) Check for Samples: CLC5526 FEATURES DESCRIPTION • • • • • The CLC5526 is a high performance, digitally controlled, variable-gain amplifier (DVGA). It has been designed for use in a broad range of mixed signal and digital communication applications such as mobile radio, cellular base stations and back-channel modems where automatic-gain-control (AGC) is required to increase system dynamic range. 1 2 350 MHz Bandwidth Differential Input and Output Gain Control: Parallel w/data Latching Supply Voltage: +5V Supply Current: 48 mA KEY SPECIFICATIONS • • • • Low Two Tone Intermod: – Distortion: −64 dBc @ 1 VPP, 150 MHz – 24.5 dBm IP3, 150 MHz Low Noise: 2.5 nV/√Hz (Max Gain), 9.3 dB Noise Figure (Max Gain) Wide Gain Range: +30 dB to −12 dB Gain Step Size: 6 dB APPLICATIONS • • • • • • • • Cellular/PCS Base Stations IF Sampling Receivers Infrared/CCD Imaging Back-channel Modems Electro-optics Instrumentation Medical Imaging High Definition Video The CLC5526 has differential input and output, allowing large signal swings on a single 5V rail. The input impedance is 200Ω. The differential output impedance is 600Ω and is designed to drive a 1 kΩ differential load. The output amplifier has excellent intermodulation performance. The CLC5526 is designed to accept signals from RF elements and maintain a terminated impedance environment. The CLC5526 maintains a 350 MHz bandwidth over its entire gain and attenuation range from +30 dB to −12 dB. Internal clamping ensures very fast overdrive recovery. Two tone intermodulation distortion is excellent: at 150 MHz, 1 Vpp it is −64 dBc. Input signals to the CLC5526 are scaled by an accurate, differential R-2R resistive ladder with an input impedance of 200Ω. A scaled version of the input is selected under digital control and passed to the internal amplifier. The input common mode level is set at 2.4V via a bandgap referenced bias generator which can be overridden by an external input. Following the resistive ladder is a fixed, 30 dB gain amplifier. The output stage common mode voltage of the CLC5526 is set to 3V, by internal, positive supply connected resistors. Digital control of the CLC5526 is accomplished by a 3-bit parallel gain control input and a data valid pin to latch the data. If the data is not latched, the DVGA is transparent to gain control updates. All digital inputs are TTL/CMOS compatible. A shutdown input reduces the CLC5526 supply currrent to a few mA. During shutdown, the input termination is maintained and current attenuation settings are held. The CLC5526 operates over the industrial temperature range of −40°C to +85°C. The part is available in a 20-pin SSOP package. 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 1999–2013, Texas Instruments Incorporated CLC5526 SNOS914E – JUNE 1999 – REVISED MARCH 2013 www.ti.com Block Diagram Pin Configuration Pin Descriptions Pin Name GND Pin No. 1, 5, 8, 10, 11, 13, 20 Description Circuit ground. Gain MSB 2 Gain Selection Most Significant Bit Gain ISB 3 Gain Selection Data Bit Gain LSB 4 Gain Selection Least Significant Bit In+ 6 Positive Differential Input In− 7 Negative Differential Input Ref Comp 9 Reference Compensation VCC 16, 19 Positive Supply Voltage Shutdown 18 Low Power Standby Control (Active High) Latch Data 17 Data Latch Control (Active High) Out+ 15 Positive Differential Output Out− 14 Negative Differential Output Ref In 12 External Reference Input These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 2 Submit Documentation Feedback Copyright © 1999–2013, Texas Instruments Incorporated Product Folder Links: CLC5526 CLC5526 www.ti.com SNOS914E – JUNE 1999 – REVISED MARCH 2013 Absolute Maximum Ratings (1) (2) −0.5V to +6V Positive Supply Voltage (VCC) Differential Voltage between any two Grounds