CLC5955MTD

CLC5955 11-bit, 55MSPS Broadband Monolithic A/D Converter April 2002 N CLC5955 11-bit, 55MSPS Broadband Monolithic A/D Converter General Description Features The CLC5955 is a monolithic 11-bit, 55MSPS analog-to-digital converter. The device has been optimized for use in IF-sampled digital receivers and other applications where high resolution, high sampling rate, wide dynamic range, low power dissipation, and compact size are required. The CLC5955 features differential analog inputs, low jitter differential universal clock inputs, a low distortion track-and-hold with 0-300MHz input bandwidth, a bandgap voltage reference, data valid clock output, TTL compatible CMOS (3.3V or 2.5V) programmable output logic, and a proprietary multistage quantizer. The CLC5955 is fabricated on the ABIC-V 0.8 micron BiCMOS process. • 55MSPS • Wide dynamic range SFDR: 74dBc SFDR w/dither: 85dBFS SNR: 64dB • IF sampling capability • Input bandwidth = 0-300MHz • Low power dissipation: 640mW • Very small package: 48-pin TSSOP • Single +5V supply • Data valid clock output • Programmable output levels: 3.3V or 2.5V The CLC5955 features a 74dBc spurious free dynamic range (SFDR) and a 64dB signal to noise ratio (SNR). The wideband track-and-hold allows sampling of IF signals to greater than 250MHz. The part produces two-tone, dithered, SFDR of 83dBFS at 75MHz input frequency. The differential analog input provides excellent common mode rejection, while the differential universal clock inputs minimize jitter. The 48-pin TSSOP package provides an extremely small footprint for applications where space is a critical consideration. The CLC5955 operates from a single +5V power supply. Operation over the industrial temperature range of -40°C to +85°C is guaranteed. National Semiconductor tests each part to verify compliance with the guaranteed specifications. Applications • • • • • • • • Cellular base-stations Digital communications Infrared/CCD imaging IF sampling Electro-optics Instrumentation Medical imaging High definition video N ME79TG CLC5955 CLC5957 N MTD ADC Block Diagram Actual Size First IF Receiver DAV Clock In IF Input AIn Q T/H Q Q IF Saw CLC5955 11-bit 55MSPS ADC ~ ~ BPF (150MHz typ.) Q CLC5903 DVGA (∆G = 42dB) Noise BPF 11 Dig. Tuner/ Filter AGC 20 DAV 3-bit (Gain Control) 11 Bit Align/Error Correct Decimation/filter = 190/0.8 Output BW = 50M/190 X 0.8 = 210KHz ADC Out Receiver SINAD vs. Input Amplitude Single Tone Output Spectrum w/Dither 90 0 Output Level (dBFS) SINAD dBc (BW = 216KHz) Fin = 25.3MHZ Fsample = 66MHz -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 60 50 40 30 20 10 0 0 4 8 12 16 20 24 Frequency (MHz) © 2002 National Semiconductor Corporation Printed in the U.S.A. 80 70 28 32 -125 -100 -75 -50 -25 0 Input (dBFS) http://www.national.com CLC5955 Electrical Characteristics (Vcc= +5V, 55MSPS; unless specified) (Tmin = -40°C, Tmax = +85°C) PARAMETERS RESOLUTION DIFF. INPUT VOLTAGE RANGE MAXIMUM CONVERSION RATE SNR SFDR CONDITIONS TEMP fin = 25MHz, Ain = -1dBFS fin = 25MHz, Ain = -1dBFS DYNAMIC PERFORMANCE large-signal bandwidth overvoltage recovery time effective aperture delay (Ta) aperture jitter Ain = -3dBFS Ain = 1.5FS (0.01%) 55 60 65 11 2.048 75 64 74 Bits V MSPS dBFS dBc 300 12 -0.41 0.3 MHz ns ns ps(rms) 65 64 63 64 64 dBFS dBFS dBFS dBFS dBFS 74 74 72 69 65 dBc dBc dBc dBc dBc +25°C +25°C 68 58 dBFS dBFS +25°C 85 dBFS +25°C 83 dBFS Full Full Full Full +25°C ±0.8 ±2.0 0 1.2 2.37 LSB LSB mV %FS V Full Full Full +25°C +25°C Full Full Full Full Full ANALOG INPUTS analog differential input voltage range analog input resistance (single ended) analog input resistance (differential) analog input capacitance (single-ended) 57 59 -30 2.2 Full Full Full Full ENCODE INPUTS (Universal) VIH VIL differential input swing DIGITAL OUTPUTS output voltage OUTLEV = 1 (open) OUTLEV = 0 (GND) TYP Full Full Full Full Full fin = 5MHz, Ain = -1dBFS fin = 5MHz, Ain = -1dBFS logic LOW logic HIGH logic HIGH POWER REQUIREMENTS +5V supply current Power dissipation VCC power supply rejection ratio UNITS MIN +25°C +25°C +25°C +25°C NOISE AND DISTORTION signal-to-noise ratio (w/o 50 harmonics) fin = 5.0MHz Ain = -1dBFS Ain = -1dBFS fin = 25MHz fin = 75MHz Ain = -3dBFS fin = 150MHz Ain = -15dBFS fin = 250MHz Ain = -15dBFS spurious-free dynamic range fin = 5.0MHz Ain = -1dBFS Ain = -1dBFS fin = 25MHz fin = 75MHz Ain = -3dBFS fin = 150MHz Ain = -15dBFS fin = 250MHz Ain = -15dBFS intermodulation distortion fin1 = 149.84MHz, fin2 = 149.7MHz Ain = -10dBFS fin1 = 249.86MHz, fin2 = 249.69MHz Ain = -10dBFS dithered performance spurious-free dynamic range Ain = -6dBFS fin = 19MHz intermodulation distortion Ain = -12dBFS fin1 = 74MHz, fin2 = 75MHz DC ACCURACY AND PERFORMANCE differential non-linearity integral non-linearity offset error gain error Vref RATINGS 0 0.2 +25°C +25°C +25°C 3.2 2.4 Full Full +25°C MAX 30 2.6 2.048 500 1000 2 +25°C +25°C +25°C NOTES 2 1 1 1 1 1 1 1 1 Vpp Ω Ω pF 5 V V V 3, 4 3, 4 3, 4 0.01 3.5 2.7 0.4 3.8 3.0 V V V 1 1 1 128 640 64 150 750 mA mW dB 1 1 Min/max ratings are based on product characterization and simulation. Individual parameters are tested as noted. Outgoing quality levels are determined from tested parameters. http://www.national.com 2 CLC5955 CLC5955 Electrical Characteristics (Vcc= +5V, 55MSPS; unless specified) (Tmin = -40°C, Tmax = +85°C) PARAMETERS CONDITIONS TIMING (CL =7pF DATA; 10pF DAV) max conversion rate (ENCODE) min conversion rate (ENCODE) pulse width high (ENCODE) 50% threshold pulse width low (ENCODE) 50% threshold ENCODE falling edge to DATA not valid ENCODE falling edge to DATA guaranteed valid rising ENCODE to rising DAV delay 50% threshold DATA setup time before rising DAV DATA hold time after rising DAV pipeline latency SYMB TEMP Full +25°C Full Full Full Full Full Full Full Full tP tM tDNV tDGV tDAV tS tH RATINGS MIN TYP 55 75 10 UNITS 9.1 9.1 8.3 8.3 tM-2.4 tP-1.6 NOTES MAX 17.8 12.6 3.0 2 MSPS MSPS ns ns ns ns ns ns ns clk cycle 1 3 3 3 3 3 3 3 Min/max ratings are based on product characterization and simulation. Individual parameters are tested as noted. Outgoing quality levels are determined from tested parameters. Notes 1) These parameters guaranteed by test. 2) Typical specifications are based on the mean test values of deliverable converters from the first three diffusion lots. 3) Values guaranteed based on characterization and simulation. 4) See page 8, Figure 3 for ENCODE Inputs circuit. Absolute Maximum Ratings positive supply voltage (Vcc) differential voltage between any two grounds analog input voltage range digital input voltage range output short circuit duration (one-pin to ground) junction temperature storage temperature range lead solder duration (+300°C) ESD tolerance human body model machine model Recommended Operating Conditions -0.5V to +6V 200mV). The clock input is internally biased to VCC/2 with a termination impedance of 2.5kΩ. D0-D10 (Pins 31-34, 39-45) Digital data outputs are CMOS and TTL compatible. D0 is the LSB and D10 is the MSB. MSB is inverted. Output coding is two’s complement. Current limited to source/sink 2.5mA typical. DAV (Pin 27) Data Valid Clock. Data is valid on rising edge. Current limited to source/sink 5mA typical. OUTLEV (Pin 28) Output Logic 3.3V or 2.5V option. Open = 3.3V, GND = 2.5V. VCM (Pin 21) Internal common mode voltage reference. Nominally +2.4V. Can be used for the input common mode voltage. This voltage is derived from an internal bandgap reference. VCM should be buffered when driving any external load. Failure to buffer this signal can cause errors in the internal bias currents. GND (Pins 1-4, 8, 11, 12, 15, 19, 20, 23-26, 35, 36, 47, 48) circuit ground. +AVCC (Pins 5-7, 16-18, 22,) +5V power supply for the analog section. Bypass to ground with a 0.1µF capacitor. +DVCC (Pins 37, 38, 46) +5V power supply for the digital section. Bypass to ground with a 0.1µF capacitor. NC (Pin 29) No connect. May be left open or grounded. OGND (Pin 30) Option ground. May be tied to GND or left floating. 7 http://www.national.com CLC5955 Applications Analog Inputs and Bias Figure 1 depicts the analog input and bias scheme. Each of the differential analog inputs are internally biased to a nominal voltage of 2.40 volts DC through a 500Ω resistor to a low impedance buffer. This enables a simple interface to a broadband RF transformer with a centertapped output winding that is decoupled to the analog ground. If the application requires the inputs to be DC coupled, the Vcm output can be used to establish the proper common -mode input voltage for the ADC. The Vcm voltage reference is generated from an internal bandgap source that is very accurate and stable. ENCODE Clock Inputs The CLC5955’s differential input clock scheme is compatible with all commonly used clock sources. Although small differential and single-ended signals are adequate, for best aperture jitter performance a low noise differential clock with a high slew rate is preferred. As depicted in Figure 3, both ENCODE clock inputs are internally biased to VCC/2 though a pair of 5KΩ resistors. The clock input buffer operates with any common-mode voltage between the supply and ground. VCCA ADC Bias Mirror Ain 5kΩ 5kΩ 5kΩ To T/H and ADC 500µΑ Ain 500Ω ENC 500Ω + 1.23V Bandgap Reference 5kΩ ENC 2KΩ 2.4V – Vcm BJT Current Mirror GNDA Figure 1: CLC5955 Bias Scheme Figure 3: CLC5955 ENCODE Clock Inputs The Vcm output may also be used to power down the ADC. When the Vcm pin is pulled above 3.5V, the internal bias mirror is disabled and the total current is reduced to less than 10mA. Figure 2 depicts how this function can be used. The diode is necessary to prevent the logic gate from altering the ADC bias value. The internal bias resistors simplify the clock interface to another center-tapped transformer as depicted in Figure 4. A low phase noise, RF synthesizer of moderate amplitude (1 - 4Vpp) can drive the ADC through this interface. ENC ~ ENC CLC5955 CLC5955 5V CMOS "1" = on "0" = off Vref Figure 4: Transformer Coupled Clock Scheme Figure 2: Power Shutdown Scheme http://www.national.com 8 CLC5955 Figures 5 shows the clock interface scheme for square wave clock sources. To ease user interface to subsequent digital circuitry, the CLC5955 has a data valid clock output (DAV). In order to match delays over IC processing variables, this digital output also uses the same output buffer as the data bits. The DAV clock output is simply a delayed version of the ENCODE input clock. Since the ADC output data change is slaved to the falling edge of the ENCODE clock, the rising DAV clock edge occurs near the center of the data valid window (or eye) regardless of the sampling frequency. ENC 0.01µF ENC 0.01µF CLC5955 Minimum Conversion Rate This ADC is optimized for high-speed operation. The internal bipolar track and hold circuits will cause droop errors at low sample rates. The point at which these errors cause a degradation of performance is listed on the specifications page as the minimum conversion rate. If a lower sample rate is desired, the ADC should be clocked at a higher rate, and the output data should be decimated. For example, to obtain a 10MSPS output, the ADC should be clocked at 20MHz, and every other output sample should be used. No significant power savings occurs at lower sample rates, since most of the power is used in analog circuits rather than digital circuits. Figure 5: TTL, 3V or 5V CMOS Clock Scheme VCCD .4Vref + - Controlled Current Output Buffer CML to CMOS Digital Signal + - 50Ω Digital Output 10kΩ Output Level GNDD Open = 3.3Vhi GND = 2.5Vhi Figure 6: CLC5955 Digital Outputs Digital Outputs and Level Select Figure 6 depicts the digital output buffer and bias used in the CLC5955. Although each of the eleven output bits uses a controlled current buffer to limit supply transients, it is recommended that parasitic loading of the outputs is minimized. Because these output transients are harmonically related to the analog input signal, excessive loading will degrade ADC performance at some frequencies. The logic high level is slaved to the internal 2.4 voltage reference. The OUTLEV control pin selects either a 3.3V or 2.5V logic high level. An internal pullup resistor selects the 3.3 volt level as the default when the OUTLEV pin is left open. Grounding the OUTLEV pin selects the 2.5V logic high level. CLC5955 9 http://www.national.com CLC5955 11-bit, 55MSPS Broadband Monolithic A/D Converter This is to make the last page rotate correctly! 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