OBSOLETE
CLC5957
www.ti.com
SNWS004C – JUNE 2000 – REVISED APRIL 2013
CLC5957 12-Bit, 70 MSPS Broadband Monolithic A/D Converter
Check for Samples: CLC5957
FEATURES
DESCRIPTION
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The CLC5957 is a monolithic 12-bit, 70MSPS analogto-digital converter. The device has been optimized
for use in IF-sampled digital receivers and other
applications where high resolution, high sampling
rate, wide dynamic range, low power dissipation, and
compact size are required. The CLC5957 features
differential analog inputs, low jitter differential
universal clock inputs, a low distortion track-and-hold
with 0-300MHz input bandwidth, a bandgap voltage
reference, data valid clock output, TTL compatible
CMOS (3.3V or 2.5V) programmable output logic, and
a proprietary 12-bit multi-stage quantizer. The
CLC5957 is fabricated on the ABIC-V 0.8 micron
BiCMOS process.
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70MSPS
Wide Dynamic Range:
– SFDR: 74dBc
– SFDR with Wither: 85dBFS
– SNR: 67dB
IF Sampling Capability
Input Bandwidth = 0-300MHz
Low Power Dissipation: 640mW
Very Small Package: 48-pin TSSOP
Single +5V Supply
Data Valid Clock Output
Programmable Output Levels: 3.3V or 2.5V
APPLICATIONS
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Cellular Base Stations
Digital Communications
Infrared/CCD Imaging
IF Sampling
Electro-optics
Instrumentation
Medical Imaging
High Definition Video
The CLC5957 features a 74dBc spurious free
dynamic range (SFDR) and a 67dB signal to noise
ratio (SNR). The wideband track-and-hold allows
sampling of IF signals to greater than 250MHz. The
part produces two-tone, dithered, SFDR of 83dBFS at
75MHz input frequency. The differential analog input
provides excellent common mode rejection, while the
differential universal clock inputs minimize jitter. The
48-pin TSSOP package provides an extremely small
footprint for applications where space is a critical
consideration. The CLC5957 operates from a single
+5V power supply. Operation over the industrial
temperature range of -40°C to +85°C is specified.
Each part is tested to verify compliance with the
ensured specifications.
Block Diagram
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PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
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necessarily include testing of all parameters.
Copyright © 2000–2013, Texas Instruments Incorporated
OBSOLETE
CLC5957
SNWS004C – JUNE 2000 – REVISED APRIL 2013
www.ti.com
Pin Configuration
Figure 1. 48 Pin TSSOP
See Package Number DGG
PIN DESCRIPTIONS
Pin
Name
AIN
AIN
ENCODE
ENCODE
VCM
D0–D11
Pin
No.
Description
13, 14
Differential input with a common mode voltage of +2.4V. The ADC full
scale input is 1.024 VPP on each of the complimentary input signals.
9, 10
Differential clock where ENCODE initiates a new data conversion cycle on
each rising edge. Logic for these inputs are a 50% duty cycle universal
differential signal (>200mV). The clock input is internally biased to VCC/2
with a termination impedance of 2.5kΩ.
21
Internal common mode voltage reference. Nominally +2.4V. Can be used
for the input common mode voltage. This voltage is derived from an
internal bandgap reference. VCM should be buffered when driving any
external load. Failure to buffer this signal can cause errors in the internal
bias currents.
Digital data outputs are CMOS and TTL compatible. D0 is the LSB and
D11 is the MSB. MSB is inverted. Output coding is two's complement.
Current limited to source/sink 2.5mA typical.
30–34,
39–45
1–4, 8, 11, 12, 15, 19, 20, 23–26, 35, 36,
47, 48
GND
Circuit ground.
+AVCC
5–7, 16–18, 22
+5V power supply for the analog section. Bypass to ground with a 0.1 µF
capacitor.
+DVCC
37, 38, 46
+5V power supply for the digital section. Bypass to ground with a 0.1 µF
capacitor.
NC
29
No connect. May be left open or grounded.
DAV
27
Data Valid Clock. Data is valid on rising edge. Current limited to
source/sink 5mA typical.
OUTLEV
28
Output Logic 3.3V or 2.5V option. Open = 3.3V, GND = 2.5V.
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
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OBSOLETE
CLC5957
www.ti.com
SNWS004C – JUNE 2000 – REVISED APRIL 2013
Absolute Maximum Ratings (1) (2)
−0.5V to +6V
Positive Supply Voltage (VCC)
Differential Voltage between any two Grounds
200mVPP and < 4 VPP with a 50% duty cycle. The duty cycle can vary from 50% if the
minimum clock pulse width times are observed. A low jitter source will be required for IF-sampled analog input
signals to maintain best performance.
CLC5957 Clock Option
The CLC5957 evaluation board is configured for use with an optional crystal clock oscillator source. The
component Y1 may be loaded with a "Full-sized", HCMOS type, crystal oscillator.
Analog Input (AIN)
The analog input is an SMA connector with a 50Ω termination. The signal is converted from single to differential
by a transformer with a 5 to 260MHz bandwidth and approximately one dB loss. Full scale is approximately
11dBm or 2.2VPP. It is recommended that the source for the analog input signal be low jitter, low noise and low
distortion to allow for proper test and evaluation of the CLC5957.
Supply voltages (J1 pins 31 A&B and 32 A&B)
The CLC5957PCASM is powered from a single 5V supply connected from the referenced pins on the Eurocard
connector. The recommended supplies are low noise linear supplies.
Digital Outputs (J1 pins 7B (MSB, D11) through 18B (LSB) and 20B (Data Valid))
The digital outputs are provided on the Eurocard connector. The outputs are buffered by 5V CMOS latches with
50Ω series output resistors. The rising edge of Data Valid may be used to clock the output data into data
collection cards or logic analyzers. The board has a location for the HP 01650-63203 termination adapter for HP
16500 logic analyzers to simplify connection to the analyzer.
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OBSOLETE
CLC5957
SNWS004C – JUNE 2000 – REVISED APRIL 2013
www.ti.com
REVISION HISTORY
Changes from Revision B (April 2013) to Revision C
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Changed layout of National Data Sheet to TI format .......................................................................................................... 19
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