CLINK3V48BT-112

Channel Link Demonstration Kit N Channel Link Demonstration Kit User Manual P/N CLINK3V48BT-112 Rev 2.2 Interface Products Information contained in this document is subject to change National Semiconductor Corporation Interface Products LIT# CLINK3V48BT-112-UM Date 07/15/08 Page 1 of 28 Channel Link Demonstration Kit Table of Contents: INTRODUCTION ....................................................................................................................... 3 CONTENTS OF DEMO KIT ....................................................................................................... 4 APPLICATIONS ........................................................................................................................ 5 APPLICATIONS ........................................................................................................................ 5 TX FEATURES AND EXPLANATIONS..................................................................................... 6 RX FEATURES AND EXPLANATIONS .................................................................................... 7 HOW TO HOOK UP THE DEMO BOARDS (OVERVIEW) ........................................................ 8 POWER CONNECTIONS .......................................................................................................... 8 TRANSMITTER BOARD ........................................................................................................... 9 SELECTABLE JUMPER SETTINGS FOR THE TX BOARD .................................................................. 9 SELECTABLE JUMPER SETTINGS FOR THE TX BOARD .................................................................10 TX JUMPER DEFAULT SETTINGS ..............................................................................................11 LVDS MAPPING BY IDC CONNECTOR ......................................................................................12 TX OPTIONAL: PARALLEL TERMINATION FOR TXIN ...................................................................12 TX OPTIONAL: PARALLEL TERMINATION FOR TXIN ...................................................................13 BOM (BILL OF MATERIALS) .....................................................................................................14 RECEIVER BOARD..................................................................................................................15 SELECTABLE JUMPER SETTINGS FOR THE RX BOARD .................................................................15 SELECTABLE JUMPER SETTINGS FOR THE RX BOARD .................................................................16 RX JUMPER DEFAULT SETTINGS ..............................................................................................16 LVDS MAPPING BY IDC CONNECTOR ......................................................................................17 RX OPTIONAL: SERIES TERMINATION FOR RXOUT ...................................................................17 RX OPTIONAL: SERIES TERMINATION FOR RXOUT ...................................................................18 BOM (BILL OF MATERIALS) .....................................................................................................19 TROUBLESHOOTING..............................................................................................................20 ADDITIONAL INFORMATION..................................................................................................21 APPLICATION NOTES ...............................................................................................................21 3M 26-MINI D RIBBON CABLE AND CONNECTOR ........................................................................22 TRANSMITTER AND RECEIVER SCHEMATICS ..............................................................................29 National Semiconductor Corporation Interface Products LIT# CLINK3V48BT-112-UM Date 07/15/08 Page 2 of 28 Channel Link Demonstration Kit Introduction National Semiconductor’s Interface Products Group Channel Link demo kit contains a Transmitter (Tx) demo board and a Receiver (Rx) demo board along with an interface cable. This kit will demonstrate the chipsets transmitting data streams using Low Voltage Differential Signaling (LVDS) through a cable at seven times the input clock rate. The Transmitter board accepts 3V TTL/CMOS data signals from an incoming data source along with the clock signal. The LVDS Transmitter converts the TTL/CMOS parallel lines into serialized LVDS pairs. The serial data streams toggle at 7 times the clock speed. The Receiver board accepts the LVDS serialized data (and clock) and converts them back into parallel 3V TTL/CMOS data out signals. The user needs to provide the proper data inputs to the Transmitter and also to provide a proper interface from the Receiver output to the receiver devices. A cable harness scramble may be necessary depending on type of cable/connector interface used. Warnings: The maximum voltage that should ever be applied to the Channel Link Transmitter or Receiver Vcc is 4V. The Transmitter and Receiver power supply pins (Vccs) are NOT 5V tolerant. The Transmitter can however accept a 3.3V or 5V TTL/CMOS level on the inputs (TxIN). The Transmitter inputs are 5V tolerant. The maximum voltage that can be applied to any input pin is 5.0V. National Semiconductor Corporation Interface Products LIT# CLINK3V48BT-112-UM Date 07/15/08 Page 3 of 28 Channel Link Demonstration Kit Contents of Demo Kit 1) One Transmitter board* with IDC connectors on Tx input DS90CR483AVJD - 48 bit Transmitter 2) One Receiver board* with IDC connectors on Rx output DS90CR484AVJD - 48 bit Receiver 3) One 2-meter 3M MDR LVDS Cable interface to connect TxOUT to RxIN. Note: The MDR footprint has been set to accept a D26-1 pinout. 4) Demonstration Kit Documentation 5) DS90CR483A/484A Datasheet *Note: The demo board trace layout is designed for minimum skew between channels. It is not absolutely required in most applications but be aware that the skew margins will be reduced if your board layout is not optimized. National Semiconductor Corporation Interface Products LIT# CLINK3V48BT-112-UM Date 07/15/08 Page 4 of 28 Channel Link Demonstration Kit Applications 8 / 8 / 8 / 8 DC BALANCE / TTL PARALLEL - TO - LVDS CMOS/TTL Inputs 8 5.38Gbps / CLOCK IN (33 - 112MHz) PLL LVDS CLOCK (33 to 112MHz) POWERDOWN 8 / CMOS/TTL Outputs / DS90CR484A 8 LVDS - TO - TTL PARALLEL 8 LVDS DATA 198 - 672 Mbps per channel DC BALANCE DECODE & DESKEW DS90CR483A / 8 / 8 / 8 / 8 / PLL CLOCK OUT (33 - 112MHz) POWERDOWN Channel Link Application The diagram above illustrates the use of the Chipset (Tx/Rx). This chipset is able to transmit 48 bits of TTL/CMOS data using eight LVDS channels at the speed of 5.38Gbps. Refer to the proper datasheet information on Chipsets (Tx/Rx) provided on each board for more detailed information. National Semiconductor Corporation Interface Products LIT# CLINK3V48BT-112-UM Date 07/15/08 Page 5 of 28 Channel Link Demonstration Kit Tx Features and Explanations Pre-emphasis (PRE - pin 14/JP1): 1. This feature enables you to overcome cable capacitance through the LVDS interface. This function provides additional instantaneous current during switching transitions. NOTE: This function does NOT affect Rx output drive. 2. It affects Tx A0-A7 and CLKs LVDS outputs only. 3. To disable this function, pin 14 must be tied “low”. LVDS output drive will then be at its standard value of 3.5mA. 4. The input will be pulled low (0.7V) if no jumper is used. To adjust the level of preemphasis, place a jumper on JP1 to Vcc. R48 will now be connected. R48 is a 2K potentiometer. Use a number 1.4mm jewelers screwdriver to adjust R48. Turning clockwise will increase the pre-emphasis value. Turning counterclockwise will decrease the pre-emphasis value. R48 should be adjusted to reduce overshoot. Too much pre-emphasis can create an overshoot condition at the rising edge and an undershoot condition on the falling edge. Icc will increase but allows you to drive longer cables. Too little pre-emphasis will not allow you to drive longer cables. Monitor any one of the LVDS lines (A0-A7) or CLK1 for a visual confirmation of its effect. It is recommended that you monitor the LVDS signals with a differential probe. If a differential probe is not used, a single ended probe can be used for a quick check. PLL range select (PLLSEL - pin 15/JP5): 1. High-range is selected by tying pin 15 “high”. 2. Low-range is selected by tying pin 15 “low”. This feature provides lower noise in the lower range of the PLL. NOTE: Refer to the “Application Notes” on the back of the data sheet for complete description of each feature. National Semiconductor Corporation Interface Products LIT# CLINK3V48BT-112-UM Date 07/15/08 Page 6 of 28 Channel Link Demonstration Kit Rx Features and Explanations PLL range select (PLLSEL - pin 5/JP5): 1. High-range is selected by tying pin 5 HIGH. 2. Low-range is selected by tying pin 5 LOW. This feature provides lower noise in the lower range of the PLL. NOTE: Refer to the “Application Notes” section on the back of the data sheet for complete description of each feature. National Semiconductor Corporation Interface Products LIT# CLINK3V48BT-112-UM Date 07/15/08 Page 7 of 28 Channel Link Demonstration Kit How to hook up the demo boards (overview) The Tx demo board TxIN has been laid out to accept two 50 pin IDC connectors from the incoming data. The TxOUT/RxIN interface uses the 3M MDR connector and 3M MDR cable with a D26-1 pin out. This combination provides minimal skew between LVDS channels. 1) Connect one end of the D26-1 MDR cable to the transmitter board and the other end to the receiver board. This is a standard pinout cable, longer lengths are available for purchase from 3M - see http://www.mmm.com 2) Jumpers have been configured from the factory (Refer to Tx and Rx "Jumper Default Settings" on pages 11 and 16) to run in normal mode with pre-emphasis ON. Jumpers are also provided on both boards so make sure that they are positioned correctly. See pages 8 and 16 for different configurations. 3) From the incoming data, connect the appropriate IDC cable to the transmitter board and connect two (2) 50-pin IDC cables from the receiver boards to the receiver load. Note that pin 1 on the connector should be connected to pin 1 of the cable. 4) Power for the Tx and Rx boards are supplied externally through Test Pad (TP) TP1. Grounds for both boards are connected through TP2. Power Connections The Transmitter and Receiver boards can only be powered by supplying power externally through TP1 (Vcc) and TP2 (GND). The maximum voltage that should ever be applied to the Channel Link Transmitter or Receiver Vcc is 4V. For the transmitter and the receiver to be operational, /PD must be tied to Vcc which is labeled as “JP3” and "JP1", respectively. Note: J4 on Tx and J1 on the Rx provide the interface for LVDS signals. National Semiconductor Corporation Interface Products LIT# CLINK3V48BT-112-UM Date 07/15/08 Page 8 of 28 Channel Link Demonstration Kit Transmitter Board J1 gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd TxIN47 TxIN46 TxIN45 TxIN44 TxIN43 TxIN42 TxIN41 TxIN40 TxIN39 TxIN38 TxIN37 TxIN36 TxIN35 TxIN34 TxIN33 TxIN32 TxIN31 TxIN30 TxIN29 TxIN28 TxIN27 TxIN26 TxIN25 TxIN24 gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd NC NC DS_ OPT TxIN23 TxIN22 TxIN21 TxIN20 TxIN19 TxIN18 TxIN17 TxIN16 TxIN15 TxIN14 TxIN13 TxIN12 TxIN11 TxIN10 TxIN9 TxIN8 TxIN7 TxIN6 TxIN5 TxIN4 TxIN3 TxIN2 TxIN1 TxIN0 CLKIN Vcc and Gnd MUST be applied externally here TxOUT LVDS signals 3M MDR connector PIN # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 NAME NC GND A0+ A1+ A2+ CLK+ GND GND A3+ A4+ A5+ A6+ A7+ NC A0A1A2CLKGND GND A3A4A5A6A7GND J4 /PD PRE DS_OPT PLLSEL J2 National Semiconductor Corporation Interface Products LIT# CLINK3V48BT-112-UM Date 07/15/08 Page 9 of 28 Channel Link Demonstration Kit Selectable jumper settings for the Tx board Jumper Purpose PRE (JP1) PRE-emphasis /PD (JP3) PowerDown Settings = NONE = ON GND Vcc GND Vcc (NONE: NO pre-emphasis; ON: pre-emphasis is adjusted through R48) When NO jumper is used, pre-emphasis is at 0.7V value. = = OFF GND Vcc (OFF: Tx powers down; PLLSEL PLL SELect (High-range) (JP5) = LOW GND Vcc (LOW: High-range OFF; National Semiconductor Corporation Interface Products ON GND Vcc ON: Tx is operational) = HIGH GND Vcc HIGH: High-range ON) LIT# CLINK3V48BT-112-UM Date 07/15/08 Page 10 of 28 Channel Link Demonstration Kit Tx Jumper Default Settings Jumper Name Purpose PRE PRE-Emphasis1 /PD PowerDown PLLSEL PLL SELelect (High-range) 1 Settings GND Vcc GND Vcc GND Vcc Jumper Number JP1 JP3 JP5 An adjustable potentiometer (2K ohm) is mounted at location R48. This allows preemphasis to be adjusted (only if JP1 has a jumper to VCC). Use a number 1.4mm jewelers screwdriver to adjust R48. Turning clockwise will increase the pre-emphasis value. Turning counterclockwise will decrease the pre-emphasis value. R48 should be adjusted to reduce overshoot. If no jumper is used, the pre-emphasis value will be 0.7V. See Tx Features and Explanations (Page 6) - Pre-Emphasis for description of feature. National Semiconductor Corporation Interface Products LIT# CLINK3V48BT-112-UM Date 07/15/08 Page 11 of 28 Channel Link Demonstration Kit LVDS Mapping by IDC Connector The following two figures show how the Tx inputs are mapped to the IDC connector and to each of the eight LVDS channels. IDC Connector IDC Connector Pin 1 gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd TxIN47 TxIN46 TxIN45 TxIN44 TxIN43 TxIN42 TxIN41 TxIN40 TxIN39 TxIN38 TxIN37 TxIN36 TxIN35 TxIN34 TxIN33 TxIN32 TxIN31 TxIN30 TxIN29 TxIN28 TxIN27 TxIN26 TxIN25 TxIN24 gnd Pin 1 TxOUT6 TxOUT7 TxOUT5 TxOUT4 J1 gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd NC NC DS_ OPT TxIN23 TxIN22 TxIN21 TxIN20 TxIN19 TxIN18 TxIN17 TxIN16 TxIN15 TxIN14 TxIN13 TxIN12 TxIN11 TxIN10 TxIN9 TxIN8 TxIN7 TxIN6 TxIN5 TxIN4 TxIN3 TxIN2 TxIN1 TxIN0 CLKIN TxOUT2 TxOUT3 TxOUT1 TxOUT0 J2 Transmitter Board National Semiconductor Corporation Interface Products LIT# CLINK3V48BT-112-UM Date 07/15/08 Page 12 of 28 Channel Link Demonstration Kit Tx Optional: Parallel Termination for TxIN On the Tx demo board, there are 50 inputs that have an 0402 pad on one side and the other side tied to ground. These pads are unpopulated from the factory but are provided if the user needs to adjust the input termination to match the impedance of the input signal. PAD1 TO PAD48 are associated with the Tx data input lines. PAD49 is associated with CLKIN. Mapping for Transmitter Inputs for the Optional Parallel Termination Resistors: Tx Pin Names Tx Pin Number TxIN0 TxIN1 TxIN2 TxIN3 TxIN4 TxIN5 TxIN6 TxIN7 TxIN8 TxIN9 TxIN10 TxIN11 TxIN12 TxIN13 TxIN14 TxIN15 TxIN16 TxIN17 TxIN18 TxIN19 TxIN20 TxIN21 TxIN22 TxIN23 TxIN24 10 9 8 7 6 5 4 3 2 1 100 99 96 95 94 93 92 91 90 89 88 87 86 85 84 Parallel Termination Resistor PAD48 PAD47 PAD46 PAD45 PAD44 PAD43 PAD42 PAD41 PAD40 PAD39 PAD38 PAD37 PAD36 PAD35 PAD34 PAD33 PAD32 PAD31 PAD30 PAD29 PAD28 PAD27 PAD26 PAD25 PAD24 Tx Pin Names Tx Pin Number TxIN25 TxIN26 TxIN27 TxIN28 TxIN29 TxIN30 TxIN31 TxIN32 TxIN33 TxIN34 TxIN35 TxIN36 TxIN37 TxIN38 TxIN39 TxIN40 TxIN41 TxIN42 TxIN43 TxIN44 TxIN45 TxIN46 TxIN47 81 80 79 78 77 76 75 74 73 72 71 70 69 66 65 64 63 62 61 60 59 58 57 Parallel Termination Resistor PAD23 PAD22 PAD21 PAD20 PAD19 PAD18 PAD17 PAD16 PAD15 PAD14 PAD13 PAD12 PAD11 PAD10 PAD9 PAD8 PAD7 PAD6 PAD5 PAD4 PAD3 PAD2 PAD1 CLKIN 11 PAD49 National Semiconductor Corporation Interface Products LIT# CLINK3V48BT-112-UM Date 07/15/08 Page 13 of 28 Channel Link Demonstration Kit BOM (Bill of Materials) Bill of Materials CLINK_112_MHz_Tx_RevC_Bom ======================================================================== Type Pattern Value Designators -----------------------------------------------------------------------------------------------------------------------------3M_MDR_D26-1 Qty = 1 3_PIN_HEADER Qty = 10 J4 .1" spacing JP1 JP2 JP3 JP4 JP5 JP6 JP7 JP8 JP9 JP10 25X2_IDC_CONN Qty = 2 J1 J2 PAD Qty = 52 0402 PAD1 PAD2 PAD3 PAD4 PAD5 PAD6 PAD7 PAD8 PAD9 PAD10 PAD11 PAD12 PAD13 PAD14 PAD15 PAD16 PAD17 PAD18 PAD19 PAD20 PAD21 PAD22 PAD23 PAD24 PAD25 PAD26 PAD27 PAD28 PAD29 PAD30 PAD31 PAD32 PAD33 PAD34 PAD35 PAD36 PAD37 PAD38 PAD39 PAD40 PAD41 PAD42 PAD43 PAD44 PAD45 PAD46 PAD47 PAD48 PAD49 PAD50 PAD51 PAD52 CAP Qty = 2 CC0805 .001uF C4 C10 CAP Qty = 4 CC0805 .01uF C5 C6 C8 C11 CAP Qty = 5 CC0805 .1uF C1 C3 C7 C9 C12 DS90CR483A Qty = 1 U1 POT Qty = 1 10Kohm R48 RES Qty = 7 10ohm R49 R50 R51 R52 R53 R54 R55 TESTPAD_.2"X.2" Qty = 2 CAP100P Qty = 4 TP1 TP2 CAP100P 10uF C2 C13 C14 C15 National Semiconductor Corporation Interface Products LIT# CLINK3V48BT-112-UM Date 07/15/08 Page 14 of 28 Channel Link Demonstration Kit Receiver Board Vcc and Gnd MUST be applied externally here PowerDown (bar) Jumper RxIN LVDS signals 3M MDR connector PIN # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 NAME NC GND A0+ A1+ A2+ CLK+ GND GND A3+ A4+ A5+ A6+ A7+ NC A0A1A2CLKGND GND A3A4A5A6A7GND J2 DESKEW Jumper PLLSEL Jumper J3 RxOUT47 RxOUT46 RxOUT45 RxOUT44 RxOUT43 RxOUT42 RxOUT41 RxOUT40 RxOUT39 RxOUT38 RxOUT37 RxOUT36 RxOUT35 RxOUT34 RxOUT33 RxOUT32 RxOUT31 RxOUT30 RxOUT29 RxOUT28 RxOUT27 RxOUT26 RxOUT25 RxOUT24 gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd RxOUT23 RxOUT22 RxOUT21 RxOUT20 RxOUT19 RxOUT18 RxOUT17 RxOUT16 RxOUT15 RxOUT14 RxOUT13 RxOUT12 RxOUT11 RxOUT10 RxOUT9 RxOUT8 RxOUT7 RxOUT6 RxOUT5 RxOUT4 RxOUT3 RxOUT2 RxOUT1 RxOUT0 CLKOut gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd NC NC NC NC NC NC J4 National Semiconductor Corporation Interface Products LIT# CLINK3V48BT-112-UM Date 07/15/08 Page 15 of 28 Channel Link Demonstration Kit Selectable jumper settings for the Rx board Jumper Purpose /PD (JP1) PowerDown Settings = = OFF ON GND Vcc GND Vcc (OFF Tx powers down; ON Tx is operational) PLLSEL PLL SELect (High range) (JP5) = GND = OFF Vcc GND ON Vcc Rx Jumper Default Settings Jumper Name Purpose /PD PowerDown – ON (Part PLLSEL PLL SELect (High-range) Settings is enabled) GND Vcc GND Vcc National Semiconductor Corporation Interface Products Jumper Number JP1 JP5 LIT# CLINK3V48BT-112-UM Date 07/15/08 Page 16 of 28 Channel Link Demonstration Kit LVDS Mapping by IDC Connector The following two figures show how the Rx outputs are mapped to the IDC connector and to each of the eight LVDS channels. TxOUT6 TxOUT7 TxOUT5 TxOUT4 RxOUT47 RxOUT46 RxOUT45 RxOUT44 RxOUT43 RxOUT42 RxOUT41 RxOUT40 RxOUT39 RxOUT38 RxOUT37 RxOUT36 RxOUT35 RxOUT34 RxOUT33 RxOUT32 RxOUT31 RxOUT30 RxOUT29 RxOUT28 RxOUT27 RxOUT26 RxOUT25 RxOUT24 gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd TxOUT2 TxOUT3 TxOUT1 TxOUT0 Pin 1 J3 RxOUT23 RxOUT22 RxOUT21 RxOUT20 RxOUT19 RxOUT18 RxOUT17 RxOUT16 RxOUT15 RxOUT14 RxOUT13 RxOUT12 RxOUT11 RxOUT10 RxOUT9 RxOUT8 RxOUT7 RxOUT6 RxOUT5 RxOUT4 RxOUT3 RxOUT2 RxOUT1 RxOUT0 CLKOut gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd NC NC NC NC NC NC Pin 1 J4 Receiver Board National Semiconductor Corporation Interface Products LIT# CLINK3V48BT-112-UM Date 04/04/01 Page 17 of 28 Channel Link Demonstration Kit Selectable jumper settings for the Rx board Jumper Purpose /PD (JP1) PowerDown Settings = = OFF ON GND Vcc GND Vcc (OFF Tx powers down; ON Tx is operational) PLLSEL PLL SELect (High range) (JP5) = GND = OFF Vcc GND ON Vcc Rx Jumper Default Settings Jumper Name Purpose /PD PowerDown – ON (Part PLLSEL PLL SELect (High-range) Settings is enabled) GND Vcc GND Vcc National Semiconductor Corporation Interface Products Jumper Number JP1 JP5 LIT# CLINK3V48BT-112-UM Date 07/15/08 Page 16 of 28 Channel Link Demonstration Kit BOM (Bill of Materials) Bill of Materials CLINK_112_MHz_Rx_RevC_bom ======================================================================== Type Pattern Value Designators -----------------------------------------------------------------------------------------------------------------------------2_PIN_HEADER .1" spacing JP3 Qty = 1 3M_MDR_D26--1 Qty = 1 3_PIN_HEADER Qty = 5 J2 .1" spacing JP1 JP2 JP4 JP5 JP6 25X2_IDC_R Qty = 2 J3 J4 PAD Qty = 6 0402 PAD1 PAD2 PAD3 PAD4 PAD5 PAD6 CAP Qty = 2 CAP Qty = 4 CAP Qty = 5 CC0805 .001uF C4 C10 CC0805 .01uF C5 C6 C8 C11 CC0805 .1uF C2 C3 C7 C9 C12 DS90CR484A Qty = 1 U1 R0402 Qty = 55 0ohm R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R23 R24 R25 R26 R27 R28 R29 R30 R31 R32 R33 R34 R35 R36 R37 R41 R42 R43 R44 R45 R46 R47 R48 R49 R50 R51 R52 R53 R54 R55 R56 R57 R58 R59 R60 R61 R62 R63 R64 R65 R66 R67 R68 R69 R70 100ohm R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 10ohm R1 R2 R38 R39 R40 Qty = 10 RES Qty = 5 TESTPAD_.2"X.2" Qty = 2 CAP100P Qty = 4 TP1 TP2 CAP100P 10uF C1 C13 C14 C15 National Semiconductor Corporation Interface Products LIT# CLINK3V48BT-112-UM Date 07/15/08 Page 19 of 28 Channel Link Demonstration Kit Troubleshooting If the demo boards are not performing properly, use the following as a guide for quick solutions to common problems. If the problem persists, contact the hotline number listed under Additional Information section of this document. Check the following: 1. Power and Ground are connected to both Tx AND Rx boards. 2. Supply voltage (typical 3.3V) and current (It's around 200mA with clock and one data bit at 66MHz.) are correct. 3. Input clock and input data (It's best to start with one data bit.) to the Tx board. 4. Jumpers are set correctly or to default settings. 5. The 2 meter cable is connecting the Tx and Rx boards. 6. Make sure all of the connections are good. 7. Start with a low clock frequency (40 or 66 MHz) and work from there. Trouble shooting chart: Problem… There is only the output clock. There is no output data. Solution… Make sure the data scramble/mapping is correct. No output data and clock. Make sure Power is on. Input data and clock are active and connected correctly. Make sure there is data input. Power, ground, input data and input clock are connected correctly, but no outputs. Make sure that the 2 meter cable is secured to both demo boards. Check the Power Down pins of both boards and make sure the devices are enabled (/PD=ON) for operation. The devices are pulling more than 1A of current. Check for shorts on the demo boards. After powering up the demo boards, the power supply reads less than 3V when it is set to 3.3V. Use a larger power supply that will provide enough current for the demo boards. National Semiconductor Corporation Interface Products LIT# CLINK3V48BT-112-UM Date 07/15/08 Page 20 of 28 Channel Link Demonstration Kit Additional Information For more information on Channel-Link Transmitters/Receivers, refer to the National Semiconductor URL: http://www.national.com/pf/DS/DS90CR483A.html Application Notes • • • • • AN-1041 CHANNEL LINK Application Note AN-971 An Overview of LVDS technology AN-1035 PCB design guidelines using LVDS technology AN-977 LVDS Signal Quality: Jitter measurement using Eye pattern AN-1059 High Speed Transmission with LVDS Devices Information available on the Internet: http://www.national.com/apnotes/ChannelLink.html Interface Hotline: The Interface Hotline number is: (408) 721-8500 National Semiconductor Corporation Interface Products LIT# CLINK3V48BT-112-UM Date 07/15/08 Page 21 of 28 Channel Link Demonstration Kit 3M 26-Mini D Ribbon cable and connector The next few pages provide a full description of the cable and connector. For product request please contact 3M. 3M Cable and Connector Data is available at: http://www.mmm.com/Interconnects National Semiconductor Corporation Interface Products LIT# CLINK3V48BT-112-UM Date 07/15/08 Page 22 of 28 Channel Link Demonstration Kit .050″ Mini D Ribbon (MDR) Connectors Surface Mount Right Angle Receptacle — Shielded 102XX-1210VE Series
Surface mount right angle shielded I/O receptacle
MDR digital LCD interface — 20 and 26 position
Ultra-low signal skew design for high data rate transmission
Ribbon type contact — industry preferred
Reliable repetitive plugging/unplugging
Latch design for easy use
Positions: 14,20, 26, 40 and 50 Date Modified: August 2, 1999 TS-0755-06 Sheet 1 of 3 8 Physical Insulation Material: Flammability: Color: Contact Material: Plating Underplate: Wiping Area: Shroud and Latch Hook Material: Plating: Screw Lock Material: Plating: Marking: Glass Reinforced Polyester (PCT) UL 94V-0 Beige Copper Alloy (C521) 80 µ″ [2.0 µm] Nickel — QQ-N-290, Class 2 20 µ″ [0.50 µm] Min Gold — MIL-G-45204, Type II, Grade C Steel Nickel Copper Alloy (C521) Tin 3M Logo and Part Number Electrical Current Rating: 1 A Insulation Resistance: > 5 × 108Ω at 500 VDC Withstanding Voltage: 500 Vrms for 1 Minute 3M Interconnect Solutions Division 6801 River Place Blvd. Austin, TX 78726-9000 For technical, sales or ordering information call 800-225-5373 National Semiconductor Corporation Interface Products LIT# CLINK3V48BT-112-UM Date 07/15/08 Page 23 of 28 Channel Link Demonstration Kit .050″ Mini D Ribbon (MDR) Connectors Surface Mount Right Angle Receptacle — Shielded tact Con Contact Quantity Part 3M Part Number 14 10214-1210 VE 10220-1210 VE 10226-1210 VE 10240-1210 VE 10250-1210 VE 20 26 40 50 102XX-1210VE Series Dimensions A
.008 B
.006 C
.006 D
.006 E
.006 1.16 [ 29.5 ] .93 [ 23.64 ] .47 [ 12.70 ] .33 [ 8.26 ] .50 [ 12.6 ] 1.32 [ 33.4 ] 1.081 [ 27.45 ] .650 [ 16.51 ] .475 [ 12.07 ] .646 [ 16.4 ] 1.50 [ 38.2 ] 1.231 [ 31.26 ] .800 [ 20.32 ] .625 [ 15.88 ] .795 [ 20.2 ] 1.85 [ 47.1 ] 1.581 [ 40.15 ] 1.150 [ 29.21 ] .975 [ 24.77 ] 1.150 [ 29.2 ] 2.06 [ 52.4 ] 1.831 [ 46.50 ] 1.400 [ 35.56 ] 1.225 [ 31.12 ] 1.40 [ 35.5 ]   A position above last position last position 2X M2.5 Thread position below pos. 1 D .025 [ 0.635 ] position 2 .368 [ 9.35 ] position 1 .047 [ 1.20 ] .010 nom. [ 0.25 ] .394 [ 10.00 ] .187 [ 4.75 ] .19 [ 4.8 ] .203 [ 5.15 ] .138 [ 3.5 ] E B 2X M2.5 Thread (see note in ordering info) Position 1 .248 [ 6.30 ] .189 [ 4.80 ] Inch Position [mm] last position C Positioning Boss (2x) Tolerance Unless Noted .0 Inch ± .1 .00 .000 ± .01 ± .005 [ ] Dimensions for Reference only Ordering Information 102XX-1210VE Contact Quantity (See Table) Note: Use (M2.5x8mm) screws to mount to panel with max. thickness of 2.0 mm. TS-0755-06 Sheet 2 of 3 3M Interconnect Solutions Division 6801 River Place Blvd. Austin, TX 78726-9000 For technical, sales or ordering information call 800-225-5373 National Semiconductor Corporation Interface Products LIT# CLINK3V48BT-112-UM Date 07/15/08 Page 24 of 28 Channel Link Demonstration Kit .050″ Mini D Ribbon (MDR) Connectors Surface Mount Right Angle Receptacle — Shielded Dimensions A ± .002 B ± .002 Contact Quantity 102XX-1210VE Series C ± .002 Recommended Board Layout 14 .930 [ 23.64 ] .500 [ 12.70 ] .325 [ 8.26 ] 20 1.081 [ 27.45 ] .650 [ 16.51 ] .475 [ 12.07 ] (viewed from connector side) 26 1.230 [ 31.26 ] .800 [ 20.32 ] .625 [ 15.88 ] 40 1.581 [ 40.15 ] 1.150 [ 29.21 ] .975 [ 24.77 ] 50 1.831 [ 46.50 ] 1.400 [ 35.56 ] 1.225 [ 31.12 ] Solder Pads for Solder Tail (See below for more detail) center spacing C .165 [ 4.2 ] center spacing .025 ± .0008 .016 ± .0004 .093 ± .0004 .118 [ 3.0 ] .110 ± .004 (2X) Screw Lock (see notes below) Lockstand Solder Pad Outline .122 [ 3.1 ] .138 [ 3.5 ] .256 [ 6.5 ] .187 max. [ 4.75 ] .088 [ 2.223 ] PCB Ref. Edge B A Solder Tail Layout Detail .079 + .004 (2X) – .000 Positioning Hole (#’s Correspond to Connector Contact # Shown on Previous Page) 7 14 Pos. Last Pos. 20 Pos. Last Pos. 6 14 13 Last Pos. 40 Pos. 12 4 11 3 10 2 1 9 Connector Position (Top Row) Position (Bottom Row) 8 PCB Ref. Edge 9 10 8 19 18 20 7 6 17 16 5 15 4 14 3 13 2 12 1 Connector Position (Top Row) Position (Bottom Row) 11 PCB Ref. Edge 13 26 Pos. 5 12 11 10 26 25 24 9 8 23 22 21 7 6 5 4 3 2 Connector Position (Top Row) 1 20 19 18 17 16 15 14 Position (Bottom Row) PCB Ref. Edge 20 19 18 17 16 15 14 13 12 Last 40 39 38 Pos. 11 10 9 8 7 6 5 4 3 2 1 Connector Position 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 Position (Bottom Row) PCB Ref. Edge 50 Pos. Last Pos. 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 Connector Position Position (Bottom Row) PCB Ref. Edge Recommended Panel Cut-out Contact Quantity D E 14 1.10 [ 19.9 ] .931 [ 23.64 ] 20 .94 [ 23.8 ] 1.081 [ 27.45 ] 26 1.09 [ 27.6 ] 1.231 [ 31.26 ] 40 1.44 [ 36.5 ] 1.581 [ 40.15 ] 50 1.69 [ 42.8 ] 1.830 [ 46.50 ] **Notes: 1. Plated through holes for .062″ board thickness. 2. Use mounting screws ( M2.5 ) to fasten to board. Note: Panel thickness .079 [ 2.00 ] Max. .319 ± .004 [ 8.1 ] R .060 [ 1.50 ] D ± .004 E ± .004 TS-0755-06 Sheet 3 of 3 3M Interconnect Solutions Division 6801 River Place Blvd. Austin, TX 78726-9000 For technical, sales or ordering information call 800-225-5373 National Semiconductor Corporation Interface Products LIT# CLINK3V48BT-112-UM Date 07/15/08 Page 25 of 28 Channel Link Demonstration Kit .050″ Mini D Ribbon (MDR) Cable Assembly High Speed Digital Data Transmission System — 26 Position 14526-EZHB-XXX-0QC
10 shielded pairs plus 4 individual wires
The solution for high speed datacom and telecom applications
Each differential pair is shielded with foil; entire cable bundle is shielded with foil and braid
Rugged MDR ribbon type contact
Quick release latches Date Modified: February 23, 2000 TS-0891-05 Sheet 1 of 3 91 Physical Connector Contact Plating Wiping Area: Shell Color: Material: Cable Color: Jacket Material: Flammability: 30µ″ [ 0.76µm ] Min. Gold Parchment/Beige Acrylonitrile Butadiene Styrene (ABS) Parchment/Beige Polyvinyl Chloride (PVC) AWM VW-1 Electrical Voltage Rating: 30 V Current Rating: 1 A Insulation Resistance: > 1 × 108Ω at @100 Vdc Withstanding Voltage: 350 Vrms for 1 minute Individually Shielded Twisted Pairs Characteristic Impedance: 100 ± 10Ω (USB 90Ω) Conductor Size: 28 AWG Stranded Propogation Velocity: 1.25 ns/ft [4.1 ns/m ] Environmental Temperature Rating: –20°C to +75°C UL File No.: E86982 3M Interconnect Solutions Division 6801 River Place Blvd. Austin, TX 78726-9000 For technical, sales or ordering information call 800-225-5373 National Semiconductor Corporation Interface Products LIT# CLINK3V48BT-112-UM Date 07/15/08 Page 26 of 28 Channel Link Demonstration Kit .050″ Mini D Ribbon (MDR) Cable Assembly High Speed Digital Data Transmission System — 26 Position 14526-EZHB-XXX-0QC 26 Position High Density Mini D Ribbon (MDR) Male Plug 26 Position High Density Mini D Ribbon (MDR) Male Plug Cable ( See wiring diagram for cable construction ) 2X Squeeze Release Latches 2X Squeeze Release Latches Length (See ordering information)
1 14 2 3 4 15 16 17 5 18 6 7 8 9 10 19 20 21 22 23 11 24 12 13 25 26 MDR 26 Position Plug ( Both Ends )   Ordering Information 14526-EZHB-XXX-0QC Length 100 = 1 meter 200 = 2 meter 500 = 5 meter A00 = 10 meter TS-0891-05 Sheet 2 of 3 3M Interconnect Solutions Division 6801 River Place Blvd. Austin, TX 78726-9000 For technical, sales or ordering information call 800-225-5373 National Semiconductor Corporation Interface Products LIT# CLINK3V48BT-112-UM Date 07/15/08 Page 27 of 28 Channel Link Demonstration Kit 3M - Preliminary Channel Link Cable Rev A 3/3/99 Assembly Specification Cable: v24.0 Connector: Plug type 10126-6000 D26-1 wiring diagram for cable assembly and board layout MDR 26 position right angle surface mount receptacle 10226-1210 VE Note: "pad" column represents actual position of solder pad on board layout. "pin #" column specifies corresponding receptacle contact #. ** Note: Temporary pinout for Channel Link testing purposes only.** Tx-483A pin # Transmitter receptacle pad pin # signal type 1 Cable Assembly Receiver receptacle signal type pin # pad Extra 1 LVDS gnd 26 Rx-484A pin # 14 Extra 2 A7P 13 79 2 Extra 3 A7M 25 80 50 15 A0M A6P 12 82 49 3 A0P A6M 24 83 47 16 A1M A5P 11 84 46 4 A1P A5M 23 85 45 17 A2M A4P 10 86 44 5 A2P A4M 22 87 42 18 CLK1M A3P 9 89 41 6 CLK1P A3M 21 90 19 Control 1 Control 4 8 7 Control 2 Control 3 20 20 Control 3 Control 2 7 8 Control 4 Control 1 19 39 21 A3M CLK1P 6 91 38 9 A3P CLK1M 18 92 37 22 A4M A2P 5 94 36 10 A4P A2M 17 95 34 23 A5M A1P 4 96 33 11 A5P A1M 16 97 32 24 A6M A0P 3 98 31 12 A6P A0M 15 99 29 25 A7M Extra 3 2 28 13 A7P Extra 2 14 26 LVDS gnd Extra 1 1 National Semiconductor Corporation Interface Products LIT# CLINK3V48BT-112-UM Date 07/15/08 Page 28 of 28 1 2 3 4 GND LVDS_GND PLL_GND A GND LVDS_GND PLL_GND TXIN11 TXIN10 TXIN24 TXIN23 TXIN22 TXIN21 TXIN20 TXIN19 TXIN18 TXIN17 TXIN16 TXIN15 TXIN14 TXIN13 TXIN12 TXIN30 TXIN29 TXIN28 TXIN27 TXIN26 TXIN25 TXIN30 TXIN29 TXIN28 TXIN27 TXIN26 TXIN25 VCC GND TXIN24 TXIN23 TXIN22 TXIN21 TXIN20 TXIN19 TXIN18 TXIN17 TXIN16 TXIN15 TXIN14 TXIN13 TXIN12 VCC GND TXIN11 TXIN10 B TXIN30 TXIN29 TXIN28 TXIN27 TXIN26 TXIN25 VCC GND TXIN24 TXIN23 TXIN22 TXIN21 TXIN20 TXIN19 TXIN18 TXIN17 TXIN16 TXIN15 TXIN14 TXIN13 TXIN12 VCC GND TXIN11 TXIN10 DS90CR483A 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 U1 TXIN31 TXIN32 TXIN33 TXIN34 TXIN35 TXIN36 TXIN37 DS90CR483A TXIN9 TXIN8 TXIN7 TXIN6 TXIN5 TXIN4 TXIN3 TXIN2 TXIN1 TXIN0 CLKIN VCC LVDS_VCC PLL_VCC C PRE PLLSEL VCC LVDS_VCC PLL_VCC C TXIN38 TXIN39 TXIN40 TXIN41 TXIN42 TXIN43 TXIN44 TXIN45 TXIN46 TXIN47 TXIN31 TXIN32 TXIN33 TXIN34 TXIN35 TXIN36 TXIN37 GND VCC TXIN38 TXIN39 TXIN40 TXIN41 TXIN42 TXIN43 TXIN44 TXIN45 TXIN46 TXIN47 VCC VCC VCC /PD B VCC GND LVDS_GND 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 TXIN31 TXIN32 TXIN33 TXIN34 TXIN35 TXIN36 TXIN37 GND VCC TXIN38 TXIN39 TXIN40 TXIN41 TXIN42 TXIN43 TXIN44 TXIN45 TXIN46 TXIN47 DS_OPT NC NC VCC GND LVDSGND TXIN9 TXIN8 TXIN7 TXIN6 TXIN5 TXIN4 TXIN3 TXIN2 TXIN1 TXIN0 TXCLKIN PLLVCC GND PRE PLLSEL PLLGND PLLGND PLLVCC PLLGND VCC VCC /PD VCC VCC LVDSGND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 TXIN9 TXIN8 TXIN7 TXIN6 TXIN5 TXIN4 TXIN3 TXIN2 TXIN1 TXIN0 CLKIN PLL_VCC GND PRE PLLSEL PLL_GND PLL_GND PLL_VCC PLL_GND R50 10ohm R51 10ohm /PD VCC R55 10ohm LVDS_GND VCC A 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 Date: Size Title TXOUTM0 TXOUTP0 LVDSVCC TXOUTM1 TXOUTP1 TXOUTM2 TXOUTP2 LVDSGND TXCLKM TXCLKP LVDSVCC TXOUTM3 TXOUTP3 TXOUTM4 TXOUTP4 LVDSGND TXOUTM5 TXOUTP5 TXOUTM6 TXOUTP6 LVDSVCC TXOUTM7 TXOUTP7 NC NC LVDS_GND A3M A3P A4M A4P A5M A5P A6M A6P A7M A7P A0M A0P A1M A1P A2M A2P CLK1M CLK1P NC1 NC2 26 position 27 28 1 14 2 15 3 16 4 17 5 18 6 19 7 20 8 21 9 22 10 23 11 24 12 25 13 26 J4 E D Thursday, July 19, 2001 Document Number CLINK3V48BT-112 Tx schematic Sheet E 1 of Demo Board schematic: CLINK3V48BT-112 - TRANSMITTER A0M A0P LVDS_VCC A1M A1P A2M A2P LVDS_GND CLK1M CLK1P LVDS_VCC A3M A3P A4M A4P LVDS_GND A5M A5P A6M A6P LVDS_VCC A7M A7P NC1 NC2 D NOTE: - Pins 27 and 28 ties the Screw Lock to ground 3 Rev 3 1 2 3 4 1 2 3 4 PRE /PD PLLSEL VCC GND A PRE /PD PLLSEL VCC GND GND GND 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 IDC2X25_Shrouded 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 J2 IDC2X25_Shrouded 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 J1 B TXIN23 TXIN22 TXIN21 TXIN20 TXIN19 TXIN18 TXIN17 TXIN16 TXIN15 TXIN14 TXIN13 TXIN12 TXIN11 TXIN10 TXIN9 TXIN8 TXIN7 TXIN6 TXIN5 TXIN4 TXIN3 TXIN2 TXIN1 TXIN0 CLKIN TXIN47 TXIN46 TXIN45 TXIN44 TXIN43 TXIN42 TXIN41 TXIN40 TXIN39 TXIN38 TXIN37 TXIN36 TXIN35 TXIN34 TXIN33 TXIN32 TXIN31 TXIN30 TXIN29 TXIN28 TXIN27 TXIN26 TXIN25 TXIN24 GND B TXIN23 TXIN22 TXIN21 TXIN20 TXIN19 TXIN18 TXIN17 TXIN16 TXIN15 TXIN14 TXIN13 TXIN12 TXIN11 TXIN10 TXIN9 TXIN8 TXIN7 TXIN6 TXIN5 TXIN4 TXIN3 TXIN2 TXIN1 TXIN0 CLKIN TXIN47 TXIN46 TXIN45 TXIN44 TXIN43 TXIN42 TXIN41 TXIN40 TXIN39 TXIN38 TXIN37 TXIN36 TXIN35 TXIN34 TXIN33 TXIN32 TXIN31 TXIN30 TXIN29 TXIN28 TXIN27 TXIN26 TXIN25 TXIN24 TXIN47 TXIN46 TXIN45 TXIN44 TXIN43 TXIN42 TXIN41 TXIN40 TXIN39 TXIN38 TXIN37 TXIN36 TXIN35 TXIN34 TXIN33 TXIN32 TXIN31 TXIN30 TXIN29 TXIN28 TXIN27 TXIN26 TXIN25 TXIN24 TXIN23 TXIN22 TXIN21 TXIN20 TXIN19 TXIN18 TXIN17 TXIN16 TXIN15 TXIN14 TXIN13 TXIN12 TXIN11 TXIN10 TXIN9 TXIN8 TXIN7 TXIN6 TXIN5 TXIN4 TXIN3 TXIN2 TXIN1 TXIN0 CLKIN C PAD1 PAD2 PAD3 PAD4 PAD5 PAD6 PAD7 PAD8 PAD9 PAD10 PAD11 PAD12 PAD13 PAD14 PAD15 PAD16 PAD17 PAD18 PAD19 PAD20 PAD21 PAD22 PAD23 PAD24 PAD25 PAD26 PAD27 PAD28 PAD29 PAD30 PAD31 PAD32 PAD33 PAD34 PAD35 PAD36 PAD37 PAD38 PAD39 PAD40 PAD41 PAD42 PAD43 PAD44 PAD45 PAD46 PAD47 PAD48 PAD49 0ohm 0ohm 0ohm 0ohm 0ohm 0ohm 0ohm 0ohm 0ohm 0ohm 0ohm 0ohm 0ohm 0ohm 0ohm 0ohm 0ohm 0ohm 0ohm 0ohm 0ohm 0ohm 0ohm 0ohm 0ohm 0ohm 0ohm 0ohm 0ohm 0ohm 0ohm 0ohm 0ohm 0ohm 0ohm 0ohm 0ohm 0ohm 0ohm 0ohm 0ohm 0ohm 0ohm 0ohm 0ohm 0ohm 0ohm 0ohm 0ohm NOTE: OPEN C GND VCC R52 10ohm Date: Size A Title D 3-PIN_HEADER 1 2 3 JP5 3-PIN_HEADER 1 2 3 JP3 3-PIN_HEADER 1 2 3 JP1 D Thursday, July 19, 2001 Document Number CLINK3V48BT-112 Tx schematic Sheet 2 Demo Board schematic: CLINK3V48BT-112 - INPUTS GND VCC GND VCC GND PRE PLLSEL R49 10ohm /PD GND R48 10Kohm A CW CCW E E of 3 Rev 3 1 2 3 4 0.001uF 0.01uF 0.1uF B C10 C9 C11 0.001uF 0.01uF 0.1uF C8 0.1uF C7 GND C2 10uF C4 0.01uF 0.01uF + C3 C6 C5 C1 0.1uF + + C15 10uF C14 10uF 0.1uF C12 + C13 10uF C Title Demo Board schematic: CLINK3V48BT-112 - POWER of 3 Rev 3 3 4 Date: Size D Thursday, July 19, 2001 Document Number CLINK3V48BT-112 Tx schematic Sheet E 3 1 PLL_GND PLL_VCC LVDS_GND LVDS_VCC GND VCC TESTPAD_.2"X.2" 1 TP2 TESTPAD_.2"X.2" VCC E 1 A GND LVDS_GND PLL_GND VCC PLL_VCC LVDS_VCC D 2 GND GND LVDS_GND PLL_GND VCC LVDS_VCC PLL_VCC TP1 1 C 2 3 4 VCC B 1 2 A 1 2 1 2 1 2 1 2 3 4 GND LVDS_GND PLL_GND VCC LVDS_VCC PLL_VCC 27 28 26 13 25 12 24 11 23 10 22 9 21 8 20 7 19 6 18 5 17 4 16 3 15 2 14 1 26 position J2 A7P A7M A6P A6M A5P A5M A4P A4M A3P A3M CLK1P CLK1M A2P A2M A1P A1M A0P A0M A LVDS_GND R22 100ohm CLK1P CLK1M A2P A2M A1P A1M A0P A0M A7P A7M A6P A6M A5P A5M A4P A4M A3P A3M R13 100ohm R14 100ohm R15 100ohm R16 100ohm R17 100ohm R18 100ohm R19 100ohm R20 100ohm R21 100ohm 2-PIN_HEADER 1 2 JP3 LVDS_GND VCC R2 10ohm /PD A7P A7M LVDS_VCC A6P A6M A5P A5M A4P A4M LVDS_GND A3P A3M CLK1P CLK1M LVDS_VCC A2P A2M A1P A1M A0P A0M LVDS_GND LVDSGND VCC /PD RXINP7 RXINM7 LVDSVCC RXINP6 RXINM6 RXINP5 RXINM5 RXINP4 RXINM4 LVDSGND RXINP3 RXINM3 RXCLKP RXCLKM LVDSVCC RXINP2 RXINM2 RXINP1 RXINM1 RXINP0 RXINM0 LVDSGND U1 B DS90CR484A 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 B C RXOUT43 RXOUT42 RXOUT41 RXOUT40 RXOUT39 RXOUT38 A NOTE: MOUNT TERMINATION RESISTORS NEXT TO DEVICE GND LVDS_GND PLL_GND VCC LVDS_VCC PLL_VCC NOTE: - Pins 27 and 28 ties the Screw Lock to ground RXOUT36 RXOUT35 RXOUT34 RXOUT37 RXOUT45 RXOUT44 RXOUT47 RXOUT46 RXOUT47 RXOUT46 VCC RXOUT45 RXOUT44 GND RXOUT43 RXOUT42 RXOUT41 RXOUT40 RXOUT39 RXOUT38 VCC RXOUT37 GND RXOUT36 RXOUT35 RXOUT34 GND 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 DS90CR484A NC NC NC GND NC NC NC RXOUT47 RXOUT46 VCC RXOUT45 RXOUT44 GND RXOUT43 RXOUT42 RXOUT41 RXOUT40 RXOUT39 RXOUT38 VCC RXOUT37 GND RXOUT36 RXOUT35 RXOUT34 PLLGND PLLVCC PLLGND DESKEW PLLSEL VCC GND RXOUT0 RXOUT1 RXOUT2 RXOUT3 RXOUT4 VCC RXOUT5 RXOUT6 GND RXOUT7 RXOUT8 RXOUT9 RXOUT10 RXOUT11 RXOUT12 VCC RXOUT13 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 C PLL_GND PLL_VCC PLL_GND DESKEW PLLSEL VCC R40 10ohm GND RXOUT0 RXOUT0 RXOUT1 RXOUT1 RXOUT2 RXOUT2 RXOUT3 RXOUT3 RXOUT4 RXOUT4 VCC RXOUT5 RXOUT5 RXOUT6 RXOUT6 GND RXOUT7 RXOUT7 RXOUT8 RXOUT8 RXOUT9 RXOUT9 RXOUT10 RXOUT10 RXOUT11 RXOUT11 RXOUT12 RXOUT12 VCC RXOUT13 GND RXOUT13 RXOUT33 RXOUT32 RXOUT31 RXOUT30 RXOUT29 VCC GND RXOUT28 RXCLKOUT RXOUT27 RXOUT26 RXOUT25 RXOUT24 RXOUT23 RXOUT22 GND RXOUT21 VCC RXOUT20 RXOUT19 RXOUT18 RXOUT17 RXOUT16 RXOUT15 RXOUT14 Date: Size Title 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 RXOUT33 RXOUT32 RXOUT31 RXOUT30 RXOUT29 VCC GND RXOUT28 CLKOUT RXOUT27 RXOUT26 RXOUT25 RXOUT24 RXOUT23 RXOUT22 GND RXOUT21 VCC RXOUT20 RXOUT19 RXOUT18 RXOUT17 RXOUT16 RXOUT15 RXOUT14 RXOUT20 RXOUT19 RXOUT18 RXOUT17 RXOUT16 RXOUT15 RXOUT14 RXOUT21 RXOUT28 CLKOUT RXOUT27 RXOUT26 RXOUT25 RXOUT24 RXOUT23 RXOUT22 RXOUT33 RXOUT32 RXOUT31 RXOUT30 RXOUT29 PLLSEL R39 10ohm GND VCC GND VCC GND R38 10ohm R1 10ohm DESKEW /PD VCC E D Thursday, July 19, 2001 Document Number CLINK3V48BT-112 Rx schematic Sheet E 1 Demo Board schematic: CLINK3V48BT-112 - RECEIVER D of 3 Rev 3 3-PIN_HEADER 1 2 3 JP5 3-PIN_HEADER 1 2 3 JP4 3-PIN_HEADER 1 2 3 JP1 1 2 3 4 1 2 3 4 VCC GND R6 R47 R7 R46 R8 R45 R9 R44 R10 R43 R11 R42 R12 R41 R51 R52 R53 R54 R55 R56 R24 R57 R25 R58 0ohm 0ohm 0ohm 0ohm 0ohm 0ohm 0ohm 0ohm 0ohm 0ohm 0ohm 0ohm 0ohm 0ohm 0ohm 0ohm 0ohm 0ohm 0ohm 0ohm 0ohm 0ohm 0ohm 0ohm RXOUT47 RXOUT46 RXOUT45 RXOUT44 RXOUT43 RXOUT42 RXOUT41 RXOUT40 RXOUT39 RXOUT38 RXOUT37 RXOUT36 RXOUT35 RXOUT34 RXOUT33 RXOUT32 RXOUT31 RXOUT30 RXOUT29 RXOUT28 RXOUT27 RXOUT26 RXOUT25 RXOUT24 GND RXOUT23 RXOUT22 RXOUT21 RXOUT20 RXOUT19 RXOUT18 RXOUT17 RXOUT16 RXOUT15 RXOUT14 RXOUT13 RXOUT12 RXOUT11 RXOUT10 RXOUT9 RXOUT8 RXOUT7 RXOUT6 RXOUT5 RXOUT4 RXOUT3 RXOUT2 RXOUT1 RXOUT0 CLKOUT A R59 R26 R60 R27 R61 R28 R62 R29 R63 R30 R37 R64 R36 R65 R35 R66 R34 R67 R33 R68 R32 R69 R31 R70 R23 0ohm 0ohm 0ohm 0ohm 0ohm 0ohm 0ohm 0ohm 0ohm 0ohm 0ohm 0ohm 0ohm 0ohm 0ohm 0ohm 0ohm 0ohm 0ohm 0ohm 0ohm 0ohm 0ohm 0ohm 0ohm RXOUT23 RXOUT22 RXOUT21 RXOUT20 RXOUT19 RXOUT18 RXOUT17 RXOUT16 RXOUT15 RXOUT14 RXOUT13 RXOUT12 RXOUT11 RXOUT10 RXOUT9 RXOUT8 RXOUT7 RXOUT6 RXOUT5 RXOUT4 RXOUT3 RXOUT2 RXOUT1 RXOUT0 CLKOUT NOTE: SHORTED INTENTIONALLY CUT TO SEPARATE RXOUT47 RXOUT46 RXOUT45 RXOUT44 RXOUT43 RXOUT42 RXOUT41 RXOUT40 RXOUT39 RXOUT38 RXOUT37 RXOUT36 RXOUT35 RXOUT34 RXOUT33 RXOUT32 RXOUT31 RXOUT30 RXOUT29 RXOUT28 RXOUT27 RXOUT26 RXOUT25 RXOUT24 VCC GND A 49 47 45 43 41 39 37 35 33 31 29 27 25 23 21 19 17 15 13 11 9 7 5 3 1 49 47 45 43 41 39 37 35 33 31 29 27 25 23 21 19 17 15 13 11 9 7 5 3 1 B IDC2X25_Shrouded 50 48 46 44 42 40 38 36 34 32 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2 J4 IDC2X25_Shrouded 50 48 46 44 42 40 38 36 34 32 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2 J3 B GND GND C C Date: Size A Title E D Tuesday, July 15, 2008 Document Number CLINK3V48BT-112 Rx schematic Sheet 2 E Demo Board schematic: CLINK3V48BT-112 - OUTPUTS D of 3 Rev 3A 1 2 3 4 0.001uF 0.01uF 0.1uF B C10 C9 C11 0.001uF 0.01uF 0.1uF C8 0.1uF C7 GND C1 10uF C4 0.01uF 0.01uF + C3 C6 C5 C2 0.1uF + + C15 10uF C14 10uF 0.1uF C12 + C13 10uF C Title Demo Board schematic: CLINK3V48BT-112 - POWER of 3 Rev 3A 3 4 Date: Size D Tuesday, July 15, 2008 Document Number CLINK3V48BT-112 Rx schematic Sheet E 3 1 PLL_GND PLL_VCC LVDS_GND LVDS_VCC GND VCC TESTPAD_.2"X.2" 1 TP2 TESTPAD_.2"X.2" VCC E 1 A GND LVDS_GND PLL_GND VCC PLL_VCC LVDS_VCC D 2 GND GND LVDS_GND PLL_GND VCC LVDS_VCC PLL_VCC TP1 1 C 2 3 4 VCC B 1 2 A 1 2 1 2 1 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. 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