CLVC2G126MDCUTEP

SN74LVC2G126-EP www.ti.com SCES856 – DECEMBER 2013 DUAL BUS BUFFER GATE WITH 3-STATE OUTPUTS Check for Samples: SN74LVC2G126-EP FEATURES 1 • • • • • • SUPPORTS DEFENSE, AEROSPACE, AND MEDICAL APPLICATIONS Supports 5-V VCC Operation Inputs Accept Voltages to 5.5 V Max tpd of 6.8 ns at 3.3 V Low Power Consumption, 10-μA Max ICC ±24-mA Output Drive at 3.3 V Typical VOLP (Output Ground Bounce) 2 V at VCC = 3.3 V, TA = 25°C Ioff Supports Partial-Power-Down Mode Operation Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A) – 200-V Machine Model (A115-A) – 1000-V Charged-Device Model (C101) • • • • • • • • • • • Controlled Baseline One Assembly and Test Site One Fabrication Site Available in Military (–55°C to 125°C) Temperature Range Extended Product Life Cycle Extended Product-Change Notification Product Traceability DCU PACKAGE (TOP VIEW) 1OE 1A 2Y GND 1 8 VCC 2 7 2OE 1Y 2A 3 6 4 5 DESCRIPTION This dual bus buffer gate is designed for 1.65-V to 5.5-V VCC operation. The SN74LVC2G126 is a dual bus driver/line driver with 3-state outputs. The outputs are disabled when the associated output-enable (OE) input is low. To ensure the high-impedance state during power up or power down, OE should be tied to GND through a pulldown resistor; the minimum value of the resistor is determined by the current-sourcing capability of the driver. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. ORDERING INFORMATION (1) TJ –55°C to 125°C (1) (2) PACKAGE VSSOP - DCU (2) Tape of 250 ORDERABLE PART NUMBER TOP-SIDE MARKING VID NUMBER CLVC2G126MDCUTEP CEPR V62/14604-01XE For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com. Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Function Table (Each Buffer) INPUTS OE A OUTPUT Y H H H H L L L X Z 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2013, Texas Instruments Incorporated SN74LVC2G126-EP SCES856 – DECEMBER 2013 www.ti.com Logic Diagram (Positive Logic) 1 1OE 1A 2 6 1Y 7 2OE 2A 5 3 2Y ABSOLUTE MAXIMUM RATINGs (1) over operating free-air temperature range (unless otherwise noted) MIN MAX VCC Supply voltage range –0.5 6.5 V VI Input voltage range (2) –0.5 6.5 V –0.5 6.5 V –0.5 VCC + 0.5 (2) UNIT VO Voltage range applied to any output in the high-impedance or power-off state VO Voltage range applied to any output in the high or low state (2) IIK Input clamp current VI < 0 –50 mA IOK Output clamp current VO < 0 –50 mA IO Continuous output current (3) Continuous current through VCC or GND V ±50 mA ±100 mA TJ Absolute maximum junction temperature range –55 150 °C Tstg Storage temperature range –65 150 °C (1) (2) (3) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. The input negative-voltage and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed. The value of VCC is provided in the recommended operating conditions table. THERMAL INFORMATION SN74LVC2G126-EP THERMAL METRIC (1) DCU UNITS 8 PINS θJA Junction-to-ambient thermal resistance (2) θJCtop Junction-to-case (top) thermal resistance (3) 78 θJB Junction-to-board thermal resistance (4) 83 204.3 (5) ψJT Junction-to-top characterization parameter ψJB Junction-to-board characterization parameter (6) 82.6 θJCbot Junction-to-case (bottom) thermal resistance (7) N/A (1) (2) (3) (4) (5) (6) (7) 2 7.6 °C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as specified in JESD51-7, in an environment described in JESD51-2a. The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDECstandard test exists, but a close description can be found in the ANSI SEMI standard G30-88. The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB temperature, as described in JESD51-8. The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7). The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining θJA , using a procedure described in JESD51-2a (sections 6 and 7). The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88. Spacer Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: SN74LVC2G126-EP SN74LVC2G126-EP www.ti.com SCES856 – DECEMBER 2013 RECOMMENDED OPERATING CONDITIONS (1) VCC Supply voltage Operating Data retention only High-level input voltage MAX 5.5 1.5 VCC = 1.65 V to 1.95 V VIH MIN 1.65 VCC = 2.3 V to 2.7 V 1.7 VCC = 3 V to 3.6 V VI Input voltage 0.7 × VCC 0.35 × VCC VCC = 2.3 V to 2.7 V 0.7 VCC = 3 V to 3.6 V 0.8 VCC = 4.5 V to 5.5 V VO Output voltage 5.5 High or low state 0 VCC 3-state 0 5.5 VCC = 3 V –32 4 VCC = 2.3 V Δt/Δv Input transition rise or fall rate 8 16 VCC = 3 V VCC = 4.5 V 32 VCC = 1.8 V ± 0.15 V, 2.5 V ± 0.2 V 20 VCC = 3.3 V ± 0.3 V 10 (1) Operating virtual junction temperature mA 24 VCC = 5 V ± 0.5 V TJ mA –24 VCC = 1.65 V Low-level output current V –8 –16 VCC = 4.5 V IOL V –4 VCC = 2.3 V High-level output current V 0.3 × VCC 0 VCC = 1.65 V IOH V 2 VCC = 1.65 V to 1.95 V Low-level input voltage V 0.65 × VCC VCC = 4.5 V to 5.5 V VIL UNIT ns/V 5 –55 125 °C All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: SN74LVC2G126-EP 3 SN74LVC2G126-EP SCES856 – DECEMBER 2013 www.ti.com ELECTRICAL CHARACTERISTICS These specifications apply for –55°C ≤ TJ ≤ 125°C (unless otherwise noted) PARAMETER TEST CONDITIONS VCC IOH = –100 μA VOH 1.65 V to 5.5 V 1.65 V 1.2 IOH = –8 mA 2.3 V 1.9 IOL = 100 μA 1.65 V to 5.5 V 0.1 IOL = 4 mA 1.65 V 0.45 IOL = 8 mA 2.3 V 0.3 3.8 0.4 3V IOL = 32 mA II 2.3 4.5 V IOL = 24 mA V 0.55 4.5 V VI = 5.5 V or GND UNIT V IOH = –32 mA IOL = 16 mA A or OE inputs MAX 2.4 3V IOH = –24 mA TYP (1) VCC – 0.1 IOH = –4 mA IOH = –16 mA VOL MIN 0.55 0 to 5.5 V ±5 μA Ioff VI or VO = 5.5 V 0 ±10 μA IOZ VO = 0 to 5.5 V 3.6 V 10 μA ICC VI = 5.5 V or GND, IO = 0 1.65 V to 5.5 V 10 μA ΔICC One input at VCC – 0.6 V, Other inputs at VCC or GND 3 V to 5.5 V 500 μA Data inputs CI Control inputs Co (1) 3.5 VI = VCC or GND 3.3 V VO = VCC or GND 3.3 V pF 4 6.5 pF All typical values are at VCC = 3.3 V, TJ = 25°C. SWITCHING CHARACTERISTICS These specifications apply for –55°C ≤ TJ ≤ 125°C (unless otherwise noted) (see Figure 2) FROM (INPUT) TO (OUTPUT) tpd A ten OE tdis OE PARAMETER VCC = 1.8 V ± 0.15 V VCC = 2.5 V ± 0.2 V VCC = 3.3 V ± 0.3 V VCC = 5 V ± 0.5 V UNIT MIN MAX MIN MAX MIN MAX MIN MAX Y 3.5 15.2 1.7 8.6 1.4 6.8 1 5.5 ns Y 3.5 15.2 1.7 8.6 1.5 6.8 1 5.5 ns Y 1.7 12.6 1 5.7 1 4.5 0.1 3.3 ns OPERATING CHARACTERISTICS TJ = 25° TEST CONDITIONS PARAMETER Cpd 4 Power dissipation capacitance Outputs enabled Outputs disabled f = 10 MHz VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V VCC = 5 V TYP TYP TYP TYP 19 19 20 22 2 2 2 3 Submit Documentation Feedback UNIT pF Copyright © 2013, Texas Instruments Incorporated Product Folder Links: SN74LVC2G126-EP SN74LVC2G126-EP www.ti.com SCES856 – DECEMBER 2013 1000000 Estimated Life (Hours) 100000 EM Voiding Fail Mode 10000 1000 80 90 100 110 120 130 140 150 Junction Temperature, TJ (°C) (1) See datasheet for absolute maximum and minimum recommended operating conditions. (2) Silicon operating life design goal is 10 years at 105°C junction temperature (does not include package interconnect life). (3) Enhanced plastic product disclaimer applies. Figure 1. SN74LVC2G126-EP Operating Life Derating Chart Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: SN74LVC2G126-EP 5 SN74LVC2G126-EP SCES856 – DECEMBER 2013 www.ti.com PARAMETER MEASUREMENT INFORMATION VLOAD S1 RL From Output Under Test Open TEST GND CL (see Note A) S1 Open VLOAD tPLH/tPHL tPLZ/tPZL tPHZ/tPZH RL GND LOAD CIRCUIT INPUTS VCC 1.8 V ± 0.15 V 2.5 V ± 0.2 V 3.3 V ± 0.3 V 5 V ± 0.5 V VI tr/tf VCC VCC 3V VCC £2 ns £2 ns £2.5 ns £2.5 ns VM VLOAD CL RL VD VCC/2 VCC/2 1.5 V VCC/2 2 × VCC 2 × VCC 6V 2 × VCC 30 pF 30 pF 50 pF 50 pF 1 kW 500 W 500 W 500 W 0.15 V 0.15 V 0.3 V 0.3 V VI Timing Input VM 0V tW tsu VI Input VM VM th VI Data Input VM VM 0V 0V VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VI VM Input VM 0V tPLH VOH Output VM VOL tPHL 0V VLOAD/2 VM tPZH VM VM VM tPLZ Output Waveform 1 S1 at VLOAD (see Note B) tPLH VOH Output VM tPZL tPHL VM VI Output Control VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS Output Waveform 2 S1 at GND (see Note B) VOL + VD VOL tPHZ VM VOH – VD VOH »0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR £ 10 MHz, ZO = 50 W. D. The outputs are measured one at a time, with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. H. All parameters and waveforms are not applicable to all devices. Figure 2. Load Circuit and Voltage Waveforms 6 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: SN74LVC2G126-EP PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) CLVC2G126MDCUTEP ACTIVE VSSOP DCU 8 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 CEPR V62/14604-01XE ACTIVE VSSOP DCU 8 250 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 CEPR (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of