CP3UB17
CP3UB17 Reprogrammable Connectivity Processor with USB Interface
Literature Number: SNOSA99C
CP3UB17 Reprogrammable Connectivity Processor
with USB Interface
1.0
General Description
The CP3UB17 connectivity processor combines a powerful
RISC core with on-chip SRAM and Flash memory for high
computing bandwidth, hardware communications peripherals for high I/O bandwidth, and an external bus for system
expandability.
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National Semiconductor offers a complete and industryproven application development environment for CP3UB17
applications, including the IAR Embedded Workbench,
iSYSTEM winIDEA and iC3000 Active Emulator, Development Board, and Application Software.
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e
On-chip communications peripherals include: USB controller, ACCESS.bus, Microwire/Plus, SPI, UART, and Advanced Audio Interface (AAI). Additional on-chip peripherals
include DMA controller, CVSD/PCM conversion module,
Timing and Watchdog Unit, Versatile Timer Unit, MultiFunction Timer, and Multi-Input Wakeup.
The CP3UB17 is backed up by the software resources designers need for rapid time-to-market, including an operating system, peripheral drivers, reference designs, and an
integrated development environment.
Block Diagram
bs
Clock Generator
12 MHz and 32 kHz
Oscillator
PLL and Clock
Generator
256K Bytes
Flash
Program
Memory
O
CR16C
CPU Core
Bus
Interface
Unit
Power-on-Reset
DMA
Controller
8K Bytes
Flash
Data
10K Bytes
Static
RAM
Serial
Debug
Interface
CPU Core Bus
Peripheral
Bus
Controller
Interrupt
Control
Unit
Power
Management
CVSD/PCM
Timing and
Watchdog
Unit
Peripheral Bus
USB
GPIO
Audio
Interface
Microwire/
SPI
UART
ACCESS
.bus
Versatile
Timer Unit
Muti-Function Timer
Multi-Input
Wake-Up
DS131
TRI-STATE is a registered trademark of National Semiconductor Corporation.
©2005 National Semiconductor Corporation
www.national.com
CP3UB17 Reprogrammable Connectivity Processor with USB Interface
FINAL
APRIL 2005
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . 1
CPU Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Device Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3.1
3.2
3.3
3.4
3.5
3.6
3.7
3.8
3.9
3.10
3.11
3.12
3.13
3.14
3.15
3.16
3.17
3.18
3.19
3.20
4.0
5.1
5.2
5.3
5.4
5.5
5.6
5.7
6.0
Operating Environment . . . . . . . . . . . . . . . . . . . . . . . . .
Bus Interface Unit (BIU) . . . . . . . . . . . . . . . . . . . . . . . .
Bus Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
BIU Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . .
Wait and Hold States . . . . . . . . . . . . . . . . . . . . . . . . . .
12.0
21.0
31
31
32
33
35
22.0
Channel Assignment. . . . . . . . . . . . . . . . . . . . . . . . . . .
Transfer Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operation Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Software DMA Request . . . . . . . . . . . . . . . . . . . . . . . .
Debug Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DMA Controller Register Set. . . . . . . . . . . . . . . . . . . . .
41
41
42
43
43
43
Non-Maskable Interrupts. . . . . . . . . . . . . . . . . . . . . . . .
Maskable Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interrupt Controller Registers . . . . . . . . . . . . . . . . . . . .
Maskable Interrupt Sources . . . . . . . . . . . . . . . . . . . . .
Nested Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
47
47
47
49
50
External Crystal Network . . . . . . . . . . . . . . . . . . . . . . .
Main Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Slow Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PLL Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
System Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Auxiliary Clocks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
External Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Clock and Reset Registers . . . . . . . . . . . . . . . . . . . . . .
23.0
Microwire Operation. . . . . . . . . . . . . . . . . . . . . . . . . . .
Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interrupt Generation. . . . . . . . . . . . . . . . . . . . . . . . . . .
Microwire Interface Registers . . . . . . . . . . . . . . . . . . .
Active Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power Save Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Idle Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Halt Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Clock Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power Management Registers . . . . . . . . . . . . . . . . . . .
Switching Between Power Modes. . . . . . . . . . . . . . . . .
57
57
57
57
58
58
59
Multi-Input Wake-Up Registers . . . . . . . . . . . . . . . . . . . 61
Programming Procedures . . . . . . . . . . . . . . . . . . . . . . . 63
Port Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Open-Drain Operation. . . . . . . . . . . . . . . . . . . . . . . . . . 67
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2
ACB Protocol Overview . . . . . . . . . . . . . . . . . . . . . . . .
ACB Functional Description . . . . . . . . . . . . . . . . . . . . .
ACCESS.bus Interface Registers . . . . . . . . . . . . . . . .
Usage Hints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
123
125
127
131
TWM Structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timer T0 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . .
Watchdog Operation . . . . . . . . . . . . . . . . . . . . . . . . . .
TWM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Watchdog Programming Procedure. . . . . . . . . . . . . . .
132
132
133
133
135
Timer Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timer Operating Modes . . . . . . . . . . . . . . . . . . . . . . . .
Timer Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timer I/O Functions . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timer Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
136
137
141
141
142
VTU Functional Description . . . . . . . . . . . . . . . . . . . . . 145
VTU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
Register Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
Register Bit Fields . . . . . . . . . . . . . . . . . . . . . . . . . . 163
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . 173
26.1
26.2
26.3
26.4
26.5
26.6
26.7
26.8
26.9
26.10
26.11
26.12
26.13
26.14
27.0
28.0
29.0
117
119
120
120
120
Versatile Timer Unit (VTU) . . . . . . . . . . . . . . . . . . . . 145
23.1
23.2
24.0
25.0
26.0
107
107
111
115
Multi-Function Timer . . . . . . . . . . . . . . . . . . . . . . . . 136
22.1
22.2
22.3
22.4
22.5
52
52
53
53
53
53
53
53
55
Input/Output Ports. . . . . . . . . . . . . . . . . . . . . . . . . . . 64
14.1
14.2
Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . . .
UART Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
UART Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Baud Rate Calculations . . . . . . . . . . . . . . . . . . . . . . . .
Timing and Watchdog Module . . . . . . . . . . . . . . . . 132
21.1
21.2
21.3
21.4
21.5
bs
Flash Memory Protection . . . . . . . . . . . . . . . . . . . . . . .
Flash Memory Organization . . . . . . . . . . . . . . . . . . . . .
Flash Memory Operations. . . . . . . . . . . . . . . . . . . . . . .
Information Block Words. . . . . . . . . . . . . . . . . . . . . . . .
Flash Memory Interface Registers . . . . . . . . . . . . . . . .
102
102
103
103
103
103
103
104
104
ACCESS.bus Interface . . . . . . . . . . . . . . . . . . . . . . . 123
20.1
20.2
20.3
20.4
Multi-Input Wake-Up . . . . . . . . . . . . . . . . . . . . . . . . . 61
13.1
13.2
14.0
20.0
Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . 57
12.1
12.2
12.3
12.4
12.5
12.6
12.7
13.0
25
26
26
26
29
Triple Clock and Reset . . . . . . . . . . . . . . . . . . . . . . . 51
11.1
11.2
11.3
11.4
11.5
11.6
11.7
11.8
11.9
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PCM Conversions . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CVSD Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PCM to CVSD Conversion. . . . . . . . . . . . . . . . . . . . . .
CVSD to PCM Conversion. . . . . . . . . . . . . . . . . . . . . .
Interrupt Generation. . . . . . . . . . . . . . . . . . . . . . . . . . .
DMA Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Freeze . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CVSD/PCM Converter Registers . . . . . . . . . . . . . . . . .
Microwire/SPI Interface . . . . . . . . . . . . . . . . . . . . . . 117
19.1
19.2
19.3
19.4
19.5
Module Configuration Register (MCFG) . . . . . . . . . . . . 30
Module Status Register (MSTAT) . . . . . . . . . . . . . . . . . 30
O
11.0
19.0
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
10.1
10.2
10.3
10.4
10.5
Audio Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . 87
Audio Interface Modes . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Bit Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Frame Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . 90
Audio Interface Operation . . . . . . . . . . . . . . . . . . . . . . . 90
Communication Options. . . . . . . . . . . . . . . . . . . . . . . . . 92
Audio Interface Registers. . . . . . . . . . . . . . . . . . . . . . . . 95
Usage Hints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
UART Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
18.1
18.2
18.3
18.4
DMA Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
9.1
9.2
9.3
9.4
9.5
9.6
10.0
18.0
68
69
71
86
CVSD/PCM Conversion Module . . . . . . . . . . . . . . . 102
17.1
17.2
17.3
17.4
17.5
17.6
17.7
17.8
17.9
Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
8.1
8.2
8.3
8.4
8.5
9.0
16
16
17
18
19
20
20
17.0
Functional States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Endpoint Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . .
USB Controller Registers. . . . . . . . . . . . . . . . . . . . . . . .
Transceiver Interface . . . . . . . . . . . . . . . . . . . . . . . . . . .
Advanced Audio Interface . . . . . . . . . . . . . . . . . . . . . 87
16.1
16.2
16.3
16.4
16.5
16.6
16.7
16.8
System Configuration Registers . . . . . . . . . . . . . . . 30
7.1
7.2
8.0
General-Purpose Registers . . . . . . . . . . . . . . . . . . . . .
Dedicated Address Registers . . . . . . . . . . . . . . . . . . . .
Processor Status Register (PSR) . . . . . . . . . . . . . . . . .
Configuration Register (CFG) . . . . . . . . . . . . . . . . . . . .
Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stacks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
16.0
Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
6.1
6.2
6.3
6.4
6.5
7.0
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
CPU Architecture. . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
USB Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
15.1
15.2
15.3
15.4
4
4
4
4
4
4
4
5
5
5
5
5
5
5
5
6
6
6
6
6
Device Pinouts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
4.1
5.0
CR16C CPU Core. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input/Output Ports. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Bus Interface Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interrupt Control Unit (ICU) . . . . . . . . . . . . . . . . . . . . . . .
USB. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Multi-Input Wake-up . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Triple Clock and Reset . . . . . . . . . . . . . . . . . . . . . . . . . .
Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Multi-Function Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Versatile Timer Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timing and Watchdog Module . . . . . . . . . . . . . . . . . . . .
UART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Microwire/SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ACCESS.bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . .
DMA Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Advanced Audio interface . . . . . . . . . . . . . . . . . . . . . . . .
CVSD/PCM Conversion Module . . . . . . . . . . . . . . . . . . .
Serial Debug Interface . . . . . . . . . . . . . . . . . . . . . . . . . .
Development Support . . . . . . . . . . . . . . . . . . . . . . . . . . .
15.0
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1.0
2.0
3.0
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CP3UB17
Table of Contents
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . .
DC Electrical Characteristics . . . . . . . . . . . . . . . . . . .
USB Transceiver Electrical Characteristics ) . . . . . . . .
Flash Memory On-Chip Programming . . . . . . . . . . . . .
Output Signal Levels . . . . . . . . . . . . . . . . . . . . . . . . . .
Clock and Reset Timing. . . . . . . . . . . . . . . . . . . . . . . .
I/O Port Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Advanced Audio Interface (AAI) Timing. . . . . . . . . . . .
Microwire/SPI Timing . . . . . . . . . . . . . . . . . . . . . . . . . .
ACCESS.bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . .
USB Port AC Characteristics . . . . . . . . . . . . . . . . . . . .
Multi-Function Timer (MFT) Timing . . . . . . . . . . . . . . .
Versatile Timing Unit (VTU) Timing . . . . . . . . . . . . . . .
External Bus Timing. . . . . . . . . . . . . . . . . . . . . . . . . . .
173
173
174
175
176
176
178
179
181
186
189
189
190
191
Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . 200
CPU Features
CPU Features
Flexible I/O
te
Fully static RISC processor core, capable of operating Up to 37 general-purpose I/O pins (shared with on-chip
from 0 to 24 MHz with zero wait/hold states
peripheral I/O pins)
Minimum 41.7 ns instruction cycle time with a 24-MHz in- Programmable I/O pin characteristics: TRI-STATE outternal clock frequency, based on a 12-MHz external input
put, push-pull output, weak pull-up input, high-imped 30 independently vectored peripheral interrupts
ance input
Schmitt triggers on general purpose inputs
On-Chip Memory
Multi-Input Wakeup
256K bytes reprogrammable Flash program memory
Extensive Power and Clock Management Support
8K bytes Flash data memory
10K bytes of static RAM data memory
On-chip Phase Locked Loop
Addresses up to 8 Mbytes of external memory
Support for multiple clock options
Broad Range of Hardware Communications Peripherals Dual clock and reset
Power-down modes
Full-speed USB node including seven Endpoint-FIFOs
Power Supply
conforming to USB 1.1 specification
2
ACCESS.bus serial bus (compatible with Philips I C bus) I/O port operation at 2.5V to 3.3V
8/16-bit SPI, Microwire/Plus serial interface
Core logic operation at 2.5V
Universal Asynchronous Receiver/Transmitter (UART)
On-chip power-on reset
Advanced Audio Interface (AAI) to connect to external 8/ Temperature Range
13-bit PCM Codecs as well as to ISDN-Controllers
-40°C to +85°C (Industrial)
through the IOM-2 interface (slave only)
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CVSD/PCM converter supporting one bidirectional audio Packages
connection
CSP-48, LQFP-100
General-Purpose Hardware Peripherals
Complete Development Environment
Dual 16-bit Multi-Function Timer
Pre-integrated hardware and software support for rapid
Versatile Timer Unit with four subsystems (VTU)
prototyping and production
Four channel DMA controller
Integrated environment
Timing and Watchdog Unit
Project manager
Multi-file C source editor
CP3UB17 Connectivity Processor Selection Guide
NSID
Speed
Temp. Range
(MHz)
Program
Flash
(kBytes)
Data
External
SRAM
Flash
Address
(kBytes)
(kBytes)
Lines
I/Os
Package
Type
Pack
Method
Tray
CP3UB17G38
24
-40° to +85°C
256
8
10
22
37
LQFP-100
CP3UB17G38X
24
-40° to +85°C
256
8
10
22
37
LQFP-100 1000-T&R
CP3UB17K38X
24
-40° to +85°C
256
8
10
0
21
CSP-48
2500-T&R
CP3UB17K38Y
24
-40° to +85°C
256
8
10
0
21
CSP-48
250-T&R
T&R = Tape and Reel
3
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CP3UB17
2.0
CP3UB17
3.0
Device Overview
The CP3UB17 connectivity processor is a complete microcomputers with all system timing, interrupt logic, program
memory, data memory, I/O ports included on-chip, making
them well-suited to a wide range of embedded applications.
The block diagram on page 1 shows the major on-chip components of the CP3UB17.
The I/O pin characteristics are fully programmable. Each pin
can be configured to operate as a TRI-STATE output, pushpull output, weak pull-up input, or high-impedance input.
For more information, please refer to the CR16C Programmer’s Reference Manual (document number 424521772101, which may be downloaded from National’s web site at
http://www.national.com).
possible memory access. To achieve fastest possible program execution, appropriate values must be programmed.
These settings vary with the clock frequency and the type of
off-chip device being accessed.
3.4
BUS INTERFACE UNIT
3.2
MEMORY
3.5
INTERRUPT CONTROL UNIT (ICU)
The ICU receives interrupt requests from internal and external sources and generates interrupts to the CPU. An interrupt is an event that temporarily stops the normal flow of
program execution and causes a separate interrupt handler
to be executed. After the interrupt is serviced, CPU execution continues with the next instruction in the program following the point of interruption.
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The CP3UB17 supports a uniform linear address space of
up to 16 megabytes. Three types of on-chip memory occupy
specific regions within this address space:
te
The Bus Interface Unit (BIU) controls access to internal/external memory and I/O. It determines the configured param3.1
CR16C CPU CORE
eters for bus access (such as the number of wait states for
The CP3UB17 implements the CR16C CPU core module. memory access) and issues the appropriate bus signals for
The high performance of the CPU core results from the im- each requested access.
plementation of a pipelined architecture with a two-bytes- The BIU uses a set of control registers to determine how
per-cycle pipelined system bus. As a result, the CPU can many wait states and hold states are used when accessing
support a peak execution rate of one instruction per clock Flash program memory, and the I/O area (Port B and Port
cycle.
C). At start-up, the configuration registers are set for slowest
256K bytes of Flash program memory
8K bytes of Flash data memory
10K bytes of static RAM
Up to 8M bytes of external memory (100-pin devices)
Interrupts from the timers, UART, Microwire/SPI interface,
and Multi-Input Wake-Up, are all maskable interrupts; they
can be enabled or disabled by software. There are 32 of
these maskable interrupts, assigned to 32 linear priority levels.
bs
The 256K bytes of Flash program memory are used to store
the application program and real-time operating system.
The Flash memory has security features to prevent unintentional programming and to prevent unauthorized access to
the program code. This memory can be programmed with
an external programming unit or with the device installed in
the application system (in-system programming).
The highest-priority interrupt is the Non-Maskable Interrupt
(NMI), which is generated by a signal received on the NMI
input pin.
O
The 8K bytes of Flash data memory are used for non-volatile storage of data entered by the end-user, such as config- 3.6
USB
uration settings.
The USB node is a Universal Serial Bus (USB) Node conThe 10K bytes of static RAM are used for temporary storage troller compatible with USB Specification, 1.0 and 1.1. It inof data and for the program stack and interrupt stack. Read tegrates the required USB transceiver, the Serial Interface
and write operations can be byte-wide or word-wide, de- Engine (SIE), and USB endpoint FIFOs. A total of seven
pending on the instruction executed by the CPU.
endpoint pipes are supported: one bidirectional pipe for the
Up to 8M bytes of external memory can be added on an ex- mandatory control EP0 and an additional six pipes for uniditernal bus. The external bus is only available on devices in rectional endpoints to support USB interrupt, bulk, and isochronous data transfers.
100-pin packages.
For Flash program and data memory, the device internally
generates the necessary voltages for programming. No additional power supply is required.
3.7
MULTI-INPUT WAKE-UP
The Multi-Input Wake-Up (MIWU) module can be used for
either of two purposes: to provide inputs for waking up (exiting) from the Halt, Idle, or Power Save mode; or to provide
3.3
INPUT/OUTPUT PORTS
general-purpose edge-triggered maskable interrupts from
The device has up to 37 software-configurable I/O pins, orexternal sources. This 16-channel module generates four
ganized into five ports called Port B, Port C, Port G, Port H,
programmable interrupts to the CPU based on the signals
and Port I. Each pin can be configured to operate as a genreceived on its 16 input channels. Channels can be individeral-purpose input or general-purpose output. In addition,
ually enabled or disabled, and programmed to respond to
many I/O pins can be configured to operate as inputs or outpositive or negative edges.
puts for on-chip peripheral modules such as the UART, timers, or Microwire/SPI interface.
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4
TRIPLE CLOCK AND RESET
This module generates a slow System Clock (32.768 kHz)
from an optional external crystal network. The Slow Clock is
used for operating the device in power-save mode. The
32.768 kHz external crystal network is optional, because
the low speed System Clock can be derived from the highspeed clock by a prescaler.
The Versatile Timer Unit (VTU) module contains four independent timer subsystems, each operating in either dual 8bit PWM configuration, as a single 16-bit PWM timer, or a
16-bit counter with two input capture channels. Each of the
four timer subsystems offer an 8-bit clock prescaler to accommodate a wide range of frequencies.
Also, two independent clocks divided down from the high
speed clock are available on output pins.
3.12
te
The Timing and Watchdog Module (TWM) contains a RealTime timer and a Watchdog unit. The Real-Time Clock Timing function can be used to generate periodic real-time
based system interrupts. The timer output is one of 16 inputs to the Multi-Input-Wake-Up module which can be used
to exit from a power-saving mode. The Watchdog unit is designed to detect the application program getting stuck in an
infinite loop resulting in loss of program control or “runaway”
programs. When the watchdog triggers, it resets the device.
The TWM is clocked by the low-speed System Clock.
3.13
UART
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e
The Triple Clock and Reset module provides the clock signals required for the operation of the various CP3UB17 onchip modules. From external crystal networks, it generates
the Main Clock, which can be scaled up to 24 MHz from an
external 12 MHz input clock, and a 32.768 kHz secondary
System Clock. The 12 MHz external clock is primarily used
as the reference frequency for the on-chip PLL. Also the
clock for modules which require a fixed clock rate (e.g. the
CVSD/PCM transcoder) is generated through prescalers
from the 12 MHz clock. The PLL generates the input clock
for the USB node and may be used to drive the high-speed
System Clock through a prescaler. Alternatively, the high
speed System Clock can be derived directly from the 12
MHz Main Clock.
TIMING AND WATCHDOG MODULE
The UART supports a wide range of programmable baud
rates and data formats, parity generation, and several error
detection schemes. The baud rate is generated on-chip, unIn addition, this module generates the device reset by using der software control.
reset input signals coming from an external reset and variThe UART offers a wake-up condition from the power-save
ous on-chip modules.
mode using the Multi-Input Wake-Up module.
3.9
POWER MANAGEMENT
3.14
bs
The Power Management Module (PMM) improves the efficiency of the device by changing the operating mode and
power consumption to match the required level of activity.
The device can operate in any of four power modes:
O
Active—The device operates at full speed using the highfrequency clock. All device functions are fully operational.
Power Save—The device operates at reduced speed using the Slow Clock. The CPU and some modules can
continue to operate at this low speed.
Idle—The device is inactive except for the Power Management Module and Timing and Watchdog Module,
which continue to operate using the Slow Clock.
Halt—The device is inactive but still retains its internal
state (RAM and register contents).
3.10
MICROWIRE/SPI
The Microwire/SPI (MWSPI) interface module supports synchronous serial communications with other devices that
conform to Microwire or Serial Peripheral Interface (SPI)
specifications. It supports 8-bit and 16-bit data transfers.
The Microwire interface allows several devices to communicate over a single system consisting of four wires: serial in,
serial out, shift clock, and slave enable. At any given time,
the Microwire interface operates as the master or a slave.
The Microwire interface supports the full set of slave select
for multi-slave implementation.
In master mode, the shift clock is generated on chip under
software control. In slave mode, a wake-up out of powersave mode is triggered using the Multi-Input Wake-Up module.
3.15
MULTI-FUNCTION TIMER
ACCESS.BUS INTERFACE
The ACCESS.bus interface module (ACB) is a two-wire seThe Multi-Function Timer (MFT) module contains a pair of
rial interface with the ACCESS.bus physical layer. It is also
16-bit timer/counter registers. Each timer/counter unit can
compatible with Intel’s System Management Bus (SMBus)
be configured to operate in any of the following modes:
and Philips’ I2C bus. The ACB module can be configured as
Processor-Independent Pulse Width Modulation (PWM) a bus master or slave, and can maintain bidirectional commode—Generates pulses of a specified width and duty munications with both multiple master and slave devices.
cycle and provides a general-purpose timer/counter.
The ACCESS.bus receiver can trigger a wake-up condition
Dual Input Capture mode—Measures the elapsed time
out of the low-power modes using the Multi-Input Wake-Up
between occurrences of external event and provides a
module.
general-purpose timer/counter.
5
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CP3UB17
Dual Independent Timer mode—Generates system timing signals or counts occurrences of external events.
The Triple Clock and Reset module generates a high-speed
Single Input Capture and Single Timer mode—Provides
main System Clock from an external crystal network. It also
one external event counter and one system timer.
provides the main system reset signal and a power-on reset
function.
3.11
VERSATILE TIMER UNIT
3.8
CP3UB17
3.16
DMA CONTROLLER
3.17
The Direct Memory Access Controller (DMAC) can speed
up data transfer between memory and I/O devices or between two memories, relative to data transfers performed directly by the CPU. A method called cycle-stealing allows the
CPU and the DMAC to use the core bus in parallel. The
DMAC implements four independent DMA channels. DMA
requests from a primary and a secondary source are recognized for each DMA channel, as well as a software DMA request issued directly by the CPU. Table 1 shows the DMA
channel assignment on the CP3UB17 architecture. The following on-chip modules can assert a DMA request to the
DMAC:
ADVANCED AUDIO INTERFACE
The audio interface provides a serial synchronous, full-duplex interface to codecs and similar serial devices. Transmit
and receive paths operate asynchronously with respect to
each other. Each path uses three signals for communication: shift clock, frame synchronization, and data.
In case receive and transmit use separate shift clocks and
frame sync signals, the interface operates in its asynchronous mode. Alternatively, the transmit and receive path can
share the same shift clock and frame sync signals for synchronous mode operation.
The interface can handle data words of either 8- or 16-bit
length and data frames can consist of up to four slots.
CR16C (Software DMA request)
USB
UART
Advanced Audio Interface
CVSD/PCM Converter
Table 1
Primary/
Secondary
Peripheral
Transaction
Primary
USB
Read/Write
UART
Read
UART
Write
Secondary
Unused
N/A
Primary
AAI
Read
Secondary
CVSD/PCM
Read
Primary
AAI
Write
Secondary
CVSD/PCM
Write
0
Secondary
Primary
1
O
3
3.19
bs
2
The CVSD/PCM module performs conversion between
CVSD and PCM data, in which the CVSD encoding is as defined in the Bluetooth specification 1.0 and the PCM data
can be 8-bit µ-Law, 8-bit A-Law, or 13-bit to 16-bit Linear.
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Channel
DMA Channel Assignment
te
In the normal mode of operation, the interface only transfers
one word at a periodic rate. In the network mode, the interface transfers multiple words at a periodic rate. The periodic
rate is also called a data frame and each word within one
frame is called a slot. The beginning of each new data frame
Table 1 shows how the four DMA channels are assigned is marked by the frame sync signal.
to the modules listed above.
3.18
CVSD/PCM CONVERSION MODULE
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SERIAL DEBUG INTERFACE
The Serial Debug Interface module (SDI module) provides
a JTAG-based serial link to an external debugger, for example running on a PC. In addition, the SDI module integrates
an on-chip debug module, which allows the user to set up to
four hardware breakpoints on instruction execution and data
transfer. The SDI module can act as a CPU bus master to
access all memory mapped resources, such as RAM and
peripherals. It also provides fast program download into the
on-chip Flash program memory using the JTAG interface.
Note: The SDI module may assert Freeze mode to gather
information, which may cause periodic fluctuations in response (bus availability, interrupt latency, etc.). Anomalous
behavior often may be traced to SDI activity.
3.20
DEVELOPMENT SUPPORT
The CP3UB17 is backed up by the software resources designers need for rapid time-to-market, including an operating system, peripheral drivers, reference designs, and an
integrated development environment.
National Semiconductor offers a complete and industryproven application development environment for CP3UB17
applications, including the IAR Embedded Workbench,
iSYSTEM winIDEA and iC3000 Active Emulator, Development Board, and Application Software. See your National
Semiconductor sales representative for current information
on availability and features of emulation equipment and
evaluation boards.
6
CP3UB17
4.0
Device Pinouts
X2CKI
X2CKO
32.768 kHz
Crystal
Power
Supply
PB[7:0]
PC[7:0]
A[21:0]
SEL0
SEL1
SEL2
SELIO
WR0
WR1
RD
X1CKI
X1CKO
12 MHz Crystal
or Ext. Clock
2
4
6
AVCC
AGND
VCC
IOVCC
GND
8
D+
X1CKI
12 MHz Crystal
or Ext. Clock
8
D-
X1CKO
USB
UVCC
22
UGND
External
Bus
Interface 32.768 kHz
Crystal/
X2CKI
PI0
X2CKO
PI1
Power
Supply
CP3UB17
(LQFP-100)
2
2
4
AVCC
PI3
AGND
PI4
VCC
IOVCC
GND
GPIO
PI5
CP3UB17
(CSP-48) PI6/WUI9
MIWU
PI7/TA
PI0
PI1
RESET
PI3
PI4
PI5
ACCESS.bus
PI6/WUI9
ENV0
ENV1
ENV2
PI7/TA
PG0/RXD/WUI10
PG1/TXD/WUI11
PG2/RTS/WUI12
PG3/CTS/WUI13
PH0/MSK/TIO1
PH1/MDIDO/TIO2
PH2/MDODI/TIO3
PH3/MWCS/TIO4
PH4/SCK/TIO5
PH5/SFS/TIO6
PH6/STD/TIO7
PH7/SRD/TIO8
Mode
Selection
PG5/SRFS/NMI
PI2/SRCLK
UART/
MIWU
PG2/RTS/WUI12
PG3/CTS/WUI13
PH0/MSK/TIO1
MIWU
PH2/MDODI/TIO3
TMS
JTAG I/F to
Debugger/
Programmer
MFT
UART/
MIWU
Mode
Selection
MICROWIRE/
SPI/
VTU
PH3/MWCS/TIO4
TDI
TDO
PH4/SCK/TIO5
TCK
PH5/SFS/TIO6
RDY
PH6/STD/TIO7
ENV0
AAI/
VTU
PH7/SRD/TIO8
PG5/SRFS/NMI
AAI/NMI
ENV1
PI2/SRCLK
AAI
MICROWIRE/
SPI/
VTU
AAI/
VTU
bs
USB
D+
DUVCC
UGND
PG1/TXD/WUI11
GPIO
PH1/MDIDO/TIO2
TCK
RDY
SDA
SCL
PG0/RXD/WUI10
RESET
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JTAG I/F to
Debugger/
Programmer
TMS
TDI
TDO
Chip Reset
te
Chip Reset
MFT
AAI/NMI
AAI
DS139
Table 2 Pin Assignments for 100-Pin Package
Alternate Function(s)
Pin Number
Type
A14
1
O
A13
2
O
A12
3
O
A11
4
O
A10
5
O
O
Pin Name
PH6
STD/TIO7
6
GPIO
PH7
SRD/TIO8
7
GPIO
ENV1
8
I/O
A9
9
O
A8
10
O
A7
11
O
A6
12
O
A5
13
O
7
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Pin Name
Alternate Function(s)
Pin Number
Type
A4
14
O
VCC
15
PWR
X2CKI
16
I
X2CKO
17
O
GND
18
PWR
AVCC
19
PWR
AGND
20
PWR
IOVCC
21
PWR
X1CKO
22
O
X1CKI
23
I
GND
24
PWR
A3
26
O
27
O
28
O
29
O
30
GPIO
31
GPIO
te
CP3UB17
Table 2 Pin Assignments for 100-Pin Package
A2
A1
A0
PI1
PI2
PB0
PB1
PB2
PB3
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PI0
SRCLK
32
GPIO
D0
33
GPIO
D1
34
GPIO
D2
35
GPIO
D3
36
GPIO
D4
37
GPIO
D5
38
GPIO
PB6
D6
39
GPIO
PB7
D7
PB4
bs
PB5
GPIO
41
PWR
IOVCC
42
PWR
PI3
43
GPIO
PI4
44
GPIO
PI5
45
GPIO
O
40
GND
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PI6
WUI9
46
GPIO
PI7
TA
47
GPIO
PG0
RXD/WUI10
48
GPIO
PG1
TXD/WUI11
49
GPIO
PC0
D8
50
GPIO
PG2
RTS/WUI12
51
GPIO
PG3
CTS/WUI13
52
GPIO
PC1
D9
53
GPIO
PC2
D10
54
GPIO
PC3
D11
55
GPIO
PC4
D12
56
GPIO
PC5
D13
57
GPIO
8
Pin Name
Alternate Function(s)
Pin Number
Type
D14
58
GPIO
D15
59
GPIO
PG5
SRFS/NMI
60
GPIO
TMS
61
I
TCK
62
I
TDI
63
I
GND
64
PWR
IOVCC
65
PWR
ENV2
66
I/O
SEL0
67
O
SCL
68
I/O
SDA
69
I/O
70
O
te
PC6
PC7
TDO
D-
71
I/O
72
I/O
73
PWR
74
PWR
75
O
76
O
77
O
78
O
79
O
80
O
MSK/TIO1
81
GPIO
PH1
MDIDO/TIO2
82
GPIO
PH2
MDODI/TIO3
83
GPIO
PH3
MWCS/TIO4
84
GPIO
ENV0
85
I/O
IOVCC
86
PWR
GND
87
PWR
VCC
88
PWR
GND
89
PWR
RESET
90
I
D+
UGND
RDY
SEL1
SEL2
SELIO
A21
A20
O
bs
PH0
ol
e
UVCC
RD
91
O
WR0
92
O
WR1
93
O
A19
94
O
A18
95
O
A17
96
O
A16
97
O
A15
98
O
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CP3UB17
Table 2 Pin Assignments for 100-Pin Package
CP3UB17
Table 2 Pin Assignments for 100-Pin Package
Pin Name
Alternate Function(s)
Pin Number
Type
PH4
SCK/TIO5
99
GPIO
PH5
SFS/TIO6
100
GPIO
Note 1: The ENV0, ENV1, ENV2, TCK, TDI, and TMS pins each have a weak pull-up to keep the input from floating.
Note 2: The RESET input has a weak pulldown.
Note 3: These functions are always enabled, due to the direct low-impedance path to these pins.
Table 3 Pin Assignments for 48-Pin Package
Pin Name
Alternate Function(s)
Pin Number
Type
PH6
STD/TIO7
1
GPIO
PH7
SRD/TIO8
GPIO
3
I/O
VCC
4
PWR
X2CKI
5
I
te
2
ENV1
X2CKO
6
O
7
PWR
8
PWR
9
PWR
10
PWR
11
O
12
I
13
PWR
15
GPIO
16
GPIO
17
GPIO
18
GPIO
PI4
19
GPIO
PI5
20
GPIO
GND
AVCC
IOVCC
X1CKO
X1CKI
GND
PI0
PI1
PI2
SRCLK
bs
PI3
ol
e
AGND
PI6
WUI9
21
GPIO
PI7
TA
22
GPIO
RXD/WUI10
23
GPIO
TXD/WUI11
24
GPIO
PG2
RTS/WUI12
25
GPIO
PG3
CTS/WUI13
26
GPIO
PG5
SRFS/NMI
O
PG0
PG1
27
GPIO
TMS
28
I
TCK
29
I
TDI
30
I
GND
31
PWR
IOVCC
32
PWR
TDO
33
O, GPIO
D-
34
O, GPIO
D+
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35
I/O
UVCC
36
PWR, I/O
UGND
37
PWR, O
10
Alternate Function(s)
Pin Number
Type
38
O
RDY
PH0
MSK/TIO1
39
GPIO
PH1
MDIDO/TIO2
40
GPIO
PH2
MDODI/TIO3
41
GPIO
PH3
MWCS/TIO4
42
GPIO
ENV0
43
I/O
VCC
44
PWR
GND
45
PWR
RESET
46
I
PH4
SCK/TIO5
47
GPIO
PH5
SFS/TIO6
48
GPIO
O
bs
ol
e
te
Note 1: The ENV0 and ENV1, TCK, TDI and TMS pins each have a weak pull-up to keep the input from floating.
Note 2: The RESET input has a weak pulldown.
Note 3: These functions are always enabled, due to the direct low-impedance path to these pins.
11
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CP3UB17
Pin Name
CP3UB17
4.1
PIN DESCRIPTION
Some pins may be enabled as general-purpose I/O-port
pins or as alternate functions associated with specific peripherals or interfaces. These pins may be individually con-
figured as port pins, even when the associated peripheral or
interface is enabled. Table 4 lists the device pins.
Table 4 CP3UB17 Pin Description for the 100-Pin LQFP Package
Name
Pins
I/O
Alternate
Name
Primary Function
Alternate Function
1
Input
12 MHz Oscillator Input
None
None
X1CKO
1
Output
12 MHz Oscillator Output
None
None
X2CKI
1
Input
32 kHz Oscillator Input
None
None
X2CKO
1
Output
32 kHz Oscillator Output
None
None
AVCC
1
Input
PLL Analog Power Supply
None
None
IOVCC
4
Input
2.5V - 3.3V I/O Power Supply
None
None
VCC
2
Input
2.5V Core Logic
Power Supply
GND
6
Input
Reference Ground
AGND
1
Input
PLL Analog Ground
RESET
1
Input
Chip general reset
TMS
1
Input
JTAG Test Mode Select
(with internal weak pull-up)
None
None
TDI
1
Input
JTAG Test Data Input
(with internal weak pull-up)
None
None
TDO
1
Output
JTAG Test Data Output
None
None
TCK
1
Input
JTAG Test Clock Input
(with internal weak pull-up)
None
None
RDY
1
Output
NEXUS Ready Output
None
None
RXD
UART Receive Data Input
1
I/O
Generic I/O
WUI10
Multi-Input Wake-Up Channel 10
TXD
UART Transmit Data Output
WUI11
Multi-Input Wake-Up Channel 11
RTS
UART Ready-To-Send Output
WUI12
Multi-Input Wake-Up Channel 12
CTS
UART Clear-To-Send Input
WUI13
Multi-Input Wake-Up Channel 13
SRFS
AAI Receive Frame Sync
NMI
Non-Maskable Interrupt Input
MSK
SPI Shift Clock
TIO1
Versatile Timer Channel 1
MDIDO
SPI Master In Slave Out
TIO2
Versatile Timer Channel 2
MDODI
SPI Master Out Slave In
TIO3
Versatile Timer Channel 3
PG1
1
1
I/O
I/O
PG3
PG5
PH0
PH1
PH2
1
1
1
1
1
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I/O
I/O
I/O
I/O
I/O
None
None
None
None
None
None
None
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e
None
Generic I/O
Generic I/O
O
PG2
bs
PG0
te
X1CKI
Generic I/O
Generic I/O
Generic I/O
Generic I/O
Generic I/O
12
PH4
PH5
PH6
PH7
1
1
1
1
1
I/O
I/O
I/O
I/O
I/O
I/O
Alternate
Name
Primary Function
Alternate Function
MWCS
SPI Slave Select Input
TIO4
Versatile Timer Channel 4
SCK
AAI Clock
TIO5
Versatile Timer Channel 5
SFS
AAI Frame Synchronization
TIO6
Versatile Timer Channel 6
STD
AAI Transmit Data Output
TIO7
Versatile Timer Channel 7
SRD
AAI Receive Data Input
TIO8
Versatile Timer Channel 8
Generic I/O
Generic I/O
Generic I/O
Generic I/O
Generic I/O
1
I/O
Generic I/O
None
None
PI1
1
I/O
Generic I/O
None
None
PI2
1
I/O
Generic I/O
SRCLK
AAI Receive Clock
PI3
1
I/O
Generic I/O
None
None
PI4
1
I/O
Generic I/O
None
None
PI5
1
I/O
Generic I/O
None
None
PI6
1
I/O
Generic I/O
WUI9
Multi-Input Wake-Up Channel 9
PI7
1
I/O
Generic I/O
TA
Multi Function Timer Port A
SDA
1
I/O
ACCESS.bus Serial Data
None
None
SCL
1
I/O
ACCESS.bus Clock
None
None
D+
1
I/O
USB D+ Upstream Port
None
None
UVCC
UGND
PB[7:0]
1
I/O
USB D- Upstream Port
None
None
1
Input
3.3V USB Transceiver Supply
None
None
1
Input
USB Transceiver Ground
None
None
8
I/O
Generic I/O
D[7:0]
External Data Bus Bit 0 to 7
8
I/O
Generic I/O
D[15:8]
External Data Bus Bit 8 to 15
O
PC[7:0]
bs
D-
ol
e
PI0
te
PH3
Pins
A[21:0]
22
Output
External Address Bus
Bit 0 to 21
None
None
SEL0
1
Output
Chip Select for Zone 0
None
None
SEL1
1
Output
Chip Select for Zone 1
None
None
SEL2
1
Output
Chip Select for Zone 2
None
None
SELIO
1
Output
Chip Select for Zone I/O Zone
None
None
WR0
1
Output
External Memory Write Low Byte
None
None
WR1
1
Output
External Memory Write High Byte
None
None
RD
1
Output
External Memory Read
None
None
ENV0
1
I/O
Special mode select input with internal pull-up during reset
PLLCLK
PLL Clock Output
13
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CP3UB17
Name
CP3UB17
Name
Pins
I/O
Alternate
Name
Primary Function
Alternate Function
ENV1
1
I/O
Special mode select input with internal pull-up during reset
CPUCLK
CPU Clock Output
ENV2
1
I/O
Special mode select input with internal pull-up during reset
SLOWCLK
Slow Clock Output
Table 5 CP3UB17 Pin Description for the 48-Pin CSP
Name
Pins
I/O
Alternate
Name
Primary Function
Alternate Function
1
Input
12 MHz Oscillator Input
None
None
X1CKO
1
Output
12 MHz Oscillator Output
None
None
X2CKI
1
Input
32 kHz Oscillator Input
None
None
X2CKO
1
Output
32 kHz Oscillator Output
None
None
AVCC
1
Input
PLL Analog Power Supply
None
None
IOVCC
2
Input
2.5V - 3.3V I/O Power Supply
None
None
VCC
2
Input
2.5V Core Logic
Power Supply
None
None
GND
4
Input
Reference Ground
None
None
AGND
1
Input
PLL Analog Ground
None
None
RESET
1
Input
Chip general reset
None
None
TMS
1
Input
JTAG Test Mode Select
(with internal weak pull-up)
None
None
TDI
1
Input
JTAG Test Data Input
(with internal weak pull-up)
None
None
TDO
1
Output
JTAG Test Data Output
None
None
1
Input
JTAG Test Clock Input
(with internal weak pull-up)
None
None
1
Output
NEXUS Ready Output
None
None
RXD
UART Receive Data Input
1
I/O
Generic I/O
WUI10
Multi-Input Wake-Up Channel 10
TXD
UART Transmit Data Output
WUI11
Multi-Input Wake-Up Channel 11
RTS
UART Ready-To-Send Output
WUI12
Multi-Input Wake-Up Channel 12
CTS
UART Clear-To-Send Input
WUI13
Multi-Input Wake-Up Channel 13
SRFS
AAI Receive Frame Sync
NMI
Non-Maskable Interrupt Input
MSK
SPI Shift Clock
TIO1
Versatile Timer Channel 1
MDIDO
SPI Master In Slave Out
TIO2
Versatile Timer Channel 2
RDY
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e
O
PG0
bs
TCK
te
X1CKI
PG1
PG2
PG3
PG5
PH0
PH1
1
1
1
1
1
1
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I/O
I/O
I/O
I/O
I/O
I/O
Generic I/O
Generic I/O
Generic I/O
Generic I/O
Generic I/O
Generic I/O
14
PH3
PH4
PH5
PH6
PH7
1
1
1
1
1
1
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Alternate
Name
Primary Function
Alternate Function
MDODI
SPI Master Out Slave In
TIO3
Versatile Timer Channel 3
MWCS
SPI Slave Select Input
TIO4
Versatile Timer Channel 4
SCK
AAI Clock
TIO5
Versatile Timer Channel 5
SFS
AAI Frame Synchronization
TIO6
Versatile Timer Channel 6
STD
AAI Transmit Data Output
TIO7
Versatile Timer Channel 7
Generic I/O
Generic I/O
Generic I/O
Generic I/O
Generic I/O
Generic I/O
te
PH2
Pins
SRD
AAI Receive Data Input
TIO8
Versatile Timer Channel 8
None
None
None
None
SRCLK
AAI Receive Clock
1
I/O
Generic I/O
PI1
1
I/O
Generic I/O
PI2
1
I/O
Generic I/O
PI3
1
I/O
Generic I/O
None
None
PI4
1
I/O
Generic I/O
None
None
PI5
1
I/O
Generic I/O
None
None
PI6
1
I/O
Generic I/O
WUI9
Multi-Input Wake-Up Channel 9
PI7
1
I/O
Generic I/O
TA
Multi Function Timer Port A
D+
1
I/O
USB D+ Upstream Port
None
None
UVCC
UGND
SDA
1
I/O
USB D- Upstream Port
None
None
1
Input
3.3V USB Transceiver Supply
None
None
1
Input
USB Transceiver Ground
None
None
1
I/O
ACCESS.bus Serial Data
None
None
1
I/O
ACCESS.bus Clock
None
None
O
SCL
bs
D-
ol
e
PI0
ENV0
1
I/O
Special mode select input with internal pull-up during reset
PLLCLK
PLL Clock Output
ENV1
1
I/O
Special mode select input with internal pull-up during reset
CPUCLK
CPU Clock Output
15
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CP3UB17
Name
CP3UB17
5.0
CPU Architecture
When the CFG.SR bit is clear, register pairs are grouped
in the manner used by native CR16C software: (R1,R0),
(R2,R1) ... (R11,R10), (R12_L, R11), R12, R13, RA, SP.
R12, R13, RA, and SP are 32-bit registers for holding addresses greater than 16 bits.
The CP3UB17 uses the CR16C third-generation 16-bit
CompactRISC processor core. The CPU implements a Reduced Instruction Set Computer (RISC) architecture that allows an effective execution rate of up to one instruction per
clock cycle. For a detailed description of the CPU16C architecture, see the CompactRISC CR16C Programmer’s Reference Manual which is available on the National
Semiconductor web site (http://www.nsc.com).
With the recommended calling convention for the architecture, some of these registers are assigned special hardware
and software functions. Registers R0 to R13 are for generalpurpose use, such as holding variables, addresses, or index
values. The SP register holds a pointer to the program runtime stack. The RA register holds a subroutine return address. The R12 and R13 registers are available to hold base
addresses used in the index addressing mode.
The CR16C CPU core includes these internal registers:
General-purpose registers (R0-R13, RA, and SP)
Dedicated address registers (PC, ISP, USP, and INTBASE)
Processor Status Register (PSR)
Configuration Register (CFG)
Processor Status Register
0
15
PSR
Configuration Register
0
15
CFG
5.2
General-Purpose Registers
15
0
The CR16C has four dedicated address registers to implement specific functions: the PC, ISP, USP, and INTBASE
registers.
R0
R1
R2
R3
R4
R5
R6
R7
R8
R9
R10
R11
R12
R13
31
5.2.1
bs
DS004
CPU Registers
O
Some register bits are designated as “reserved.” Software
must write a zero to these bit locations when it writes to the
register. Read operations from reserved bit locations return
undefined values.
5.1
GENERAL-PURPOSE REGISTERS
The CompactRISC CPU features 16 general-purpose registers. These registers are used individually as 16-bit operands or as register pairs for operations on addresses
greater than 16 bits.
General-purpose registers are defined as R0 through
R13, RA, and SP.
Registers are grouped into pairs based on the setting of
the Short Register bit in the Configuration Register
(CFG.SR). When the CFG.SR bit is set, the grouping of
register pairs is upward-compatible with the architecture
of the earlier CR16A/B CPU cores: (R1,R0), (R2,R1) ...
(R11,R10), (R12_L, R11), (R13_L, R12_L), (R14_L,
R13_L) and SP. (R14_L, R13_L) is the same as
(RA,ERA).
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Program Counter (PC) Register
The 24-bit value in the PC register points to the first byte of
the instruction currently being executed. CR16C instructions are aligned to even addresses, therefore the least significant bit of the PC is always 0. At reset, the PC is
initialized to 0 or an optional predetermined value. When a
warm reset occurs, value of the PC prior to reset is saved in
the (R1,R0) general-purpose register pair.
RA
SP
Figure 1.
DEDICATED ADDRESS REGISTERS
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e
Dedicated Address Registers
23
15
0
31
PC
ISPH
ISPL
USPH
USPL
INTBASEH
INTBASEL
te
If a general-purpose register is specified by an operation
The R0-R11, PSR, and CFG registers are 16 bits wide. The that is 8 bits long, only the lower byte of the register is used;
R12, R13, RA, SP, ISP and USP registers are 32 bits wide. the upper part is not referenced or modified. Similarly, for
The PC register is 24 bits wide. Figure 1 shows the CPU word operations on register pairs, only the lower word is
used. The upper word is not referenced or modified.
registers.
16
5.2.2
Interrupt Stack Pointer (ISP)
The 32-bit ISP register points to the top of the interrupt
stack. This stack is used by hardware to service exceptions
(interrupts and traps). The stack pointer may be accessed
as the ISP register for initialization. The interrupt stack can
be located anywhere in the CPU address space. The ISP
cannot be used for any purpose other than the interrupt
stack, which is used for automatic storage of the CPU registers when an exception occurs and restoration of these
registers when the exception handler returns. The interrupt
stack grows downward in memory. The least significant bit
and the 8 most significant bits of the ISP register are always
0.
5.2.3
User Stack Pointer (USP)
The USP register points to the top of the user-mode program stack. Separate stacks are available for user and supervisor modes, to support protection mechanisms for
multitasking software. The processor mode is controlled by
the U bit in the PSR register (which is called PSR.U in the
shorthand convention). Stack grow downward in memory. If
the USP register points to an illegal address (any address
greater than 0x00FF_FFFF) and the USP is used for stack
access, an IAD trap is taken.
Interrupt Base Register (INTBASE)
N
The INTBASE register holds the address of the dispatch table for exceptions. The dispatch table can be located anywhere in the CPU address space. When loading the
INTBASE register, bits 31 to 24 and bit 0 must written with 0.
5.3
PROCESSOR STATUS REGISTER (PSR)
E
The PSR provides state information and controls operating
modes for the CPU. The format of the PSR is shown below.
12 11 10 9
C
T
L
P E
6
5
4
3
2
0 N Z
F
0 U L
1
0
T C
The Carry bit indicates whether a carry or borrow occurred after addition or subtraction.
0 – No carry or borrow occurred.
1 – Carry or borrow occurred.
The Trace bit enables execution tracing, in
which a Trace trap (TRC) is taken after every
instruction. Tracing is automatically disabled
during the execution of an exception handler.
0 – Tracing disabled.
1 – Tracing enabled.
The Low bit indicates the result of the last
comparison operation, with the operands interpreted as unsigned integers.
0 – Second operand greater than or equal to
first operand.
1 – Second operand less than first operand.
The User Mode bit controls whether the CPU
is in user or supervisor mode. In supervisor
mode, the SP register is used for stack operations. In user mode, the USP register is used
instead. User mode is entered by executing
the Jump USR instruction. When an exception
is taken, the exception handler automatically
begins execution in supervisor mode. The
USP register is accessible using the Load
Processor Register (LPR/LPRD) instruction in
supervisor mode. In user mode, an attempt to
access the USP register generates a UND
trap.
0 – CPU is executing in supervisor mode.
1 – CPU is executing in user mode.
The Flag bit is a general condition flag for signalling exception conditions or distinguishing
the results of an instruction, among other
thing uses. For example, integer arithmetic instructions use the F bit to indicate an overflow
condition after an addition or subtraction operation.
The Zero bit is used by comparison operations. In a comparison of integers, the Z bit is
set if the two operands are equal. If the operands are unequal, the Z bit is cleared.
0 – Source and destination operands unequal.
1 – Source and destination operands equal.
P
O
bs
U
I
7
ol
e
Reserved
8
te
15
F
Z
The Negative bit indicates the result of the last
comparison operation, with the operands interpreted as signed integers.
0 – Second operand greater than or equal to
first operand.
1 – Second operand less than first operand.
The Local Maskable Interrupt Enable bit enables or disables maskable interrupts. If this
bit and the Global Maskable Interrupt Enable
(I) bit are both set, all interrupts are enabled.
If either of these bits is clear, only the nonmaskable interrupt is enabled. The E bit is set
by the Enable Interrupts (EI) instruction and
cleared by the Disable Interrupts (DI) instruction.
0 – Maskable interrupts disabled.
1 – Maskable interrupts enabled.
The Trace Trap Pending bit is used together
with the Trace (T) bit to prevent a Trace (TRC)
trap from occurring more than once for one instruction. At the beginning of the execution of
an instruction, the state of the T bit is copied
into the P bit. If the P bit remains set at the end
of the instruction execution, the TRC trap is
taken.
0 – No trace trap pending.
1 – Trace trap pending.
The Global Maskable Interrupt Enable bit is
used to enable or disable maskable interrupts.
If this bit and the Local Maskable Interrupt Enable (E) bit are both set, all maskable interrupts are taken. If either bit is clear, only the
non-maskable interrupt is taken. Unlike the E
bit, the I bit is automatically cleared when an
interrupt occurs and automatically set upon
completion of an interrupt handler.
0 – Maskable interrupts disabled.
1 – Maskable interrupts enabled.
I
Bits Z, C, L, N, and F of the PSR are referenced from assembly language by the condition code in conditional
branch instructions. A conditional branch instruction may
cause a branch in program execution, based on the value of
one or more of these PSR bits. For example, one of the
Bcond instructions, BEQ (Branch EQual), causes a branch
if the PSR.Z bit is set.
On reset, bits 0 through 11 of the PSR are cleared, except
for the PSR.E bit, which is set. On warm reset, the values of
each bit before reset are copied into the R2 general-purpose register. Bits 4 and 8 of the PSR have a constant value
of 0. Bits 12 through 15 are reserved. In general, status bits
are modified only by specific instructions. Otherwise, status
bits maintain their values throughout instructions which do
not implicitly affect them.
17
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CP3UB17
5.2.4
CONFIGURATION REGISTER (CFG)
The CFG register is used to enable or disable various operating modes and to control optional on-chip caches. Because the CP3UB17 does not have cache memory, the
cache control bits in the CFG register are reserved. All CFG
bits are cleared on reset.
15
10 9
Reserved
ED
7
6
SR ED 0
0
5
2
Reserved
1
0
0
0
The Extended Dispatch bit selects whether
the size of an entry in the interrupt dispatch table (IDT) is 16 or 32 bits. Each entry holds the
address of the appropriate exception handler.
When the IDT has 16-bit entries, and all exception handlers must reside in the first 128K
of the address space. The location of the IDT
is held in the INTBASE register, which is not
affected by the state of the ED bit.
0 – Interrupt dispatch table has 16-bit entries.
1 – Interrupt dispatch table has 32-bit entries.
The Short Register bit enables a compatibility
mode for the CR16B large model. In the
CR16C core, registers R12, R13, and RA are
extended to 32 bits. In the CR16B large model, only the lower 16 bits of these registers are
used, and these “short registers” are paired
together for 32-bit operations. In this mode,
the (RA, R13) register pair is used as the extended RA register, and address displacements relative to a single register are
supported with offsets of 0 and 14 bits in place
of the index addressing with these displacements.
0 – 32-bit registers are used.
1 – 16-bit registers are used (CR16B mode).
O
bs
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e
SR
8
te
CP3UB17
5.4
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18
ADDRESSING MODES
The CR16C CPU core implements a load/store architecture, in which arithmetic and logical instructions operate on
register operands. Memory operands are made accessible
in registers using load and store instructions. For efficient
implementation of I/O-intensive embedded applications, the
architecture also provides a set of bit operations that operate on memory operands.
The load and store instructions support these addressing
modes: register/pair, immediate, relative, absolute, and index addressing. When register pairs are used, the lower bits
are in the lower index register and the upper bits are in the
higher index register. When the CFG.SR bit is clear, the 32bit registers R12, R13, RA, and SP are also treated as register pairs.
jump (r5, r4)
load $4(r4,r3), (r6,r5)
load $5(r12), (r13)
In register/pair mode, the operand is held
in a general-purpose register, or in a general-purpose register pair. For example,
the following instruction adds the contents of the low byte of register r1 to the
contents of the low byte of r2, and places
the result in the low byte register r2. The
high byte of register r2 is not modified.
ADDB R1, R2
Immediate
In immediate mode, the operand is a conMode
stant value which is encoded in the instruction. For example, the following
instruction multiplies the value of r4 by 4
and places the result in r4.
MULW $4, R4
Relative Mode In relative mode, the operand is addressed using a relative value (displacement) encoded in the instruction. This
displacement is relative to the current
Program Counter (PC), a general-purpose register, or a register pair.
In the following example, the operand address is the sum of the displacement 4,
the contents of the register pair (r5,r4),
and the base address held in register r12.
The word at this address is loaded into
register r6.
LOADW [r12]4(r5, r4), r6
Absolute Mode In absolute mode, the operand is located
in memory, and its address is encoded in
the instruction (normally 20 or 24 bits).
For example, the following instruction
loads the byte at address 4000 into the
lower 8 bits of register r6.
LOADB 4000, r6
O
bs
Register/Pair
Mode
For relative mode operands, the memory address is calculated by adding
the value of a register pair and a displacement to the base address. The
displacement can be a 14 or 20-bit unsigned value, which is encoded in the
instruction.
For absolute mode operands, the
memory address is calculated by adding a 20-bit absolute address encoded
in the instruction to the base address.
ol
e
The instruction set supports the following addressing
modes:
Index Mode
te
References to register pairs in assembly language use parentheses. With a register pair, the lower numbered register
pair must be on the right. For example,
In another example, the operand resides
in memory. Its address is obtained by
adding a displacement encoded in the instruction to the contents of register r5.
The address calculation does not modify
the contents of register r5.
LOADW 12(R5), R6
The following example calculates the address of a source operand by adding a
displacement of 4 to the contents of a
register pair (r5, r4) and loads this operand into the register pair (r7, r6). r7 receives the high word of the operand, and
r6 receives the low word.
LOADD 4(r5, r4), (r7, r6)
In index mode, the operand address is
calculated with a base address held in either R12 or R13. The CFG.SR bit must
be clear to use this mode.
For additional information on the addressing modes, see the
CompactRISC CR16C Programmer's Reference Manual.
In branch instructions, the displacement
is always relative to the current value of
the PC Register. For example, the following instruction causes an unconditional
branch to an address 10 ahead of the
current PC.
BR *+10
19
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CP3UB17
5.5
CP3UB17
5.6
STACKS
5.7
A stack is a last-in, first-out data structure for dynamic storage of data and addresses. A stack consists of a block of
memory used to hold the data and a pointer to the top of the
stack. As more data is pushed onto a stack, the stack grows
downward in memory. The CR16C supports two types of
stacks: the interrupt stack and program stacks.
INSTRUCTION SET
Table 6 lists the operand specifiers for the instruction set,
and Table 7 is a summary of all instructions. For each instruction, the table shows the mnemonic and a brief description of the operation performed.
User and Supervisor Stack Pointers
disp
Displacement (numeric suffix
indicates number of bits)
imm
Immediate operand (numeric suffix indicates number of bits)
Iposition
Bit position in memory
Rbase
Base register (relative mode)
Rdest
Destination register
Rindex
Index register
RPbase, RPbasex
Base register pair (relative mode)
RPdest
Destination register pair
RPlink
Link register pair
Rposition
Bit position in register
Rproc
16-bit processor register
Rprocd
32-bit processor register
RPsrc
Source register pair
RPtarget
Target register pair
Rsrc, Rsrc1, Rsrc2
Source register
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5.6.3
te
In the mnemonic column, the lower-case letter “i” is used to
indicate the type of integer that the instruction operates on,
either “B” for byte or “W” for word. For example, the notation
5.6.1
Interrupt Stack
ADDi for the “add” instruction means that there are two
The processor uses the interrupt stack to save and restore
forms of this instruction, ADDB and ADDW, which operate
the program state during the exception handling. Hardware
on bytes and words, respectively.
automatically pushes this data onto the interrupt stack before entering an exception handler. When the exception Similarly, the lower-case string “cond” is used to indicate the
handler returns, hardware restores the processor state with type of condition tested by the instruction. For example, the
data popped from the interrupt stack. The interrupt stack notation Jcond represents a class of conditional jump instructions: JEQ for Jump on Equal, JNE for Jump on Not
pointer is held in the ISP register.
Equal, etc. For detailed information on all instructions, see
5.6.2
Program Stack
the CompactRISC CR16C Programmer's Reference ManuThe program stack is normally used by software to save and al.
restore register values on subroutine entry and exit, hold loTable 6 Key to Operand Specifiers
cal and temporary variables, and hold parameters passed
between the calling routine and the subroutine. The only
Operand Specifier
Description
hardware mechanisms which operate on the program stack
are the PUSH, POP, and POPRET instructions.
abs
Absolute address
To support multitasking operating systems, support is provided for two program stack pointers: a user stack pointer
and a supervisor stack pointer. When the PSR.U bit is clear,
the SP register is used for all program stack operations. This
is the default mode when the user/supervisor protection
mechanism is not used, and it is the supervisor mode when
protection is used.
O
bs
When the PSR.U bit is set, the processor is in user mode,
and the USP register is used as the program stack pointer.
User mode can only be entered using the JUSR instruction,
which performs a jump and sets the PSR.U bit. User mode
is exited when an exception is taken and re-entered when
the exception handler returns. In user mode, the LPRD instruction cannot be used to change the state of processor
registers (such as the PSR).
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20
CP3UB17
Table 7 Instruction Set Summary
Mnemonic
Operands
Description
Rsrc/imm, Rdest
Move
MOVXB
Rsrc, Rdest
Move with sign extension
MOVZB
Rsrc, Rdest
Move with zero extension
MOVXW
Rsrc, RPdest
Move with sign extension
MOVZW
Rsrc, RPdest
Move with zero extension
MOVD
imm, RPdest
Move immediate to register-pair
RPsrc, RPdest
Move between register-pairs
ADD[U]i
Rsrc/imm, Rdest
Add
ADDCi
Rsrc/imm, Rdest
Add with carry
ADDD
RPsrc/imm, RPdest
MACQWa
Rsrc1, Rsrc2, RPdest
MACSWa
Rsrc1, Rsrc2, RPdest
MACUWa
Rsrc1, Rsrc2, RPdest
Multiply unsigned and add result:
RPdest := RPdest + (Rsrc1 × Rsrc2)
MULi
Rsrc/imm, Rdest
Multiply: Rdest(8) := Rdest(8) × Rsrc(8)/imm
Rdest(16) := Rdest(16) × Rsrc(16)/imm
MULSB
Rsrc, Rdest
Multiply: Rdest(16) := Rdest(8) × Rsrc(8)
MULSW
Rsrc, RPdest
Multiply: RPdest := RPdest(16) × Rsrc(16)
MULUW
Rsrc, RPdest
Multiply: RPdest := RPdest(16) × Rsrc(16);
SUBi
Rsrc/imm, Rdest
Subtract: (Rdest := Rdest - Rsrc/imm)
RPsrc/imm, RPdest
Subtract: (RPdest := RPdest - RPsrc/imm)
Rsrc/imm, Rdest
Subtract with carry: (Rdest := Rdest - Rsrc/imm)
Rsrc/imm, Rdest
Compare Rdest - Rsrc/imm
RPsrc/imm, RPdest
Compare RPdest - RPsrc/imm
BEQ0i
Rsrc, disp
Compare Rsrc to 0 and branch if EQUAL
BNE0i
Rsrc, disp
Compare Rsrc to 0 and branch if NOT EQUAL
ANDi
Rsrc/imm, Rdest
Logical AND: Rdest := Rdest & Rsrc/imm
ANDD
RPsrc/imm, RPdest
Logical AND: RPdest := RPsrc & RPsrc/imm
ORi
Rsrc/imm, Rdest
Logical OR: Rdest := Rdest | Rsrc/imm
ORD
RPsrc/imm, RPdest
Logical OR: Rdest := RPdest | RPsrc/imm
Scond
Rdest
Save condition code as boolean
XORi
Rsrc/imm, Rdest
Logical exclusive OR: Rdest := Rdest ^ Rsrc/imm
XORD
RPsrc/imm, RPdest
Logical exclusive OR: Rdest := RPdest ^ RPsrc/imm
ASHUi
Rsrc/imm, Rdest
Arithmetic left/right shift
SUBCi
CMPi
Multiply signed Q15:
RPdest := RPdest + (Rsrc1 × Rsrc2)
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e
Multiply signed and add result:
RPdest := RPdest + (Rsrc1 × Rsrc2)
O
CMPD
Add with RP or immediate.
bs
SUBD
te
MOVi
21
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CP3UB17
Table 7 Instruction Set Summary
Mnemonic
Operands
Description
ASHUD
Rsrc/imm, RPdest
Arithmetic left/right shift
LSHi
Rsrc/imm, Rdest
Logical left/right shift
LSHD
Rsrc/imm, RPdest
Logical left/right shift
SBITi
Iposition, disp(Rbase)
Set a bit in memory
(Because this instruction treats the destination as a readmodify-write operand, it not be used to set bits in writeonly registers.)
Iposition, disp(RPbase)
Iposition, (Rindex)disp(RPbasex)
Iposition, abs
Iposition, (Rindex)abs
Iposition, disp(Rbase)
Iposition, disp(RPbase)
Iposition, (Rindex)disp(RPbasex)
Iposition, abs
Iposition, (Rindex)abs
Rposition/imm, Rsrc
Test a bit in a register
Test a bit in memory
ol
e
TBIT
TBITi
Clear a bit in memory
te
CBITi
Iposition, disp(Rbase)
Iposition, disp(RPbase)
Iposition, (Rindex)disp(RPbasex)
Iposition, abs
Iposition, (Rindex)abs
LPRD
SPR
SPRD
Bcond
Rsrc, Rproc
Load processor register
RPsrc, Rprocd
Load double processor register
Rproc, Rdest
Store processor register
Rprocd, RPdest
Store 32-bit processor register
disp9
Conditional branch
bs
LPR
O
disp17
disp24
BAL
RPlink, disp24
Branch and link
BR
disp9
Branch
disp17
disp24
EXCP
vector
Trap (vector)
Jcond
RPtarget
Conditional Jump to a large address
JAL
RA, RPtarget,
Jump and link to a large address
RPlink, RPtarget
JUMP
RPtarget
Jump
JUSR
RPtarget
Jump and set PSR.U
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22
CP3UB17
Table 7 Instruction Set Summary
Mnemonic
Operands
Description
RETX
Return from exception
imm, Rsrc, RA
Push “imm” number of registers on user stack, starting
with Rsrc and possibly including RA
POP
imm, Rdest, RA
Restore “imm” number of registers from user stack,
starting with Rdest and possibly including RA
POPRET
imm, Rdest, RA
Restore registers (similar to POP) and JUMP RA
LOADi
disp(Rbase), Rdest
Load (register relative)
abs, Rdest
Load (absolute)
(Rindex)abs, Rdest
Load (absolute index relative)
(Rindex)disp(RPbasex), Rdest
Load (register relative index)
disp(RPbase), Rdest
Load (register pair relative)
LOADD
disp(Rbase), Rdest
abs, Rdest
Load (register relative)
Load (absolute)
Load (absolute index relative)
ol
e
(Rindex)abs, Rdest
te
PUSH
Load (register pair relative index)
disp(RPbase), Rdest
Load (register pair relative)
Rsrc, disp(Rbase)
Store (register relative)
Rsrc, disp(RPbase)
Store (register pair relative)
Rsrc, abs
Store (absolute)
Rsrc, (Rindex)disp(RPbasex)
Store (register pair relative index)
Rsrc, (Rindex)abs
Store (absolute index)
RPsrc, disp(Rbase)
Store (register relative)
RPsrc, disp(RPbase)
Store (register pair relative)
RPsrc, abs
Store (absolute)
RPsrc, (Rindex)disp(RPbasex)
Store (register pair index relative)
RPsrc, (Rindex)abs
Store (absolute index relative)
imm4, disp(Rbase)
Store unsigned 4-bit immediate value extended to operand
length in memory
bs
STORi
(Rindex)disp(RPbasex), Rdest
O
STORD
STOR IMM
imm4, disp(RPbase)
imm4, (Rindex)disp(RPbasex)
imm4, abs
imm4, (Rindex)abs
LOADM
imm3
Load 1 to 8 registers (R2-R5, R8-R11) from memory
starting at (R0)
LOADMP
imm3
Load 1 to 8 registers (R2-R5, R8-R11) from memory
starting at (R1, R0)
STORM
STORM imm3
Store 1 to 8 registers (R2-R5, R8-R11) to memory starting
at (R2)
23
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Mnemonic
STORMP
Operands
Description
imm3
Store 1 to 8 registers (R2-R5, R8-R11) to memory starting
at (R7,R6)
DI
Disable maskable interrupts
EI
Enable maskable interrupts
EIWAIT
Enable maskable interrupts and wait for interrupt
NOP
No operation
WAIT
Wait for interrupt
O
bs
ol
e
te
CP3UB17
Table 7 Instruction Set Summary
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24
Memory
The CP3UB17 supports a uniform 16M-byte linear address are reserved and must not be read or written. The BIU
space. Table 8 lists the types of memory and peripherals zones are regions of the address space that share the same
that occupy this memory space. Unlisted address ranges control bits in the Bus Interface Unit (BIU).
Table 8 CP3UB17 Memory Map
End
Address
Size in
Bytes
00 0000h
03 FFFFh
256K
On-chip Flash Program Memory, including Boot
Memory
04 0000h
0D FFFFh
640K
Reserved
0E 0000h
0E 1FFFh
8K
On-chip Flash Data Memory
0E 2000h
0E 7FFFh
24K
Reserved
0E 8000h
0E 91FFh
4.5K
Reserved
0E 9200h
0E BFFFh
11.5K
Reserved
0E C000h
0E E7FFh
10K
System RAM
0E E800h
0E EBFFh
1K
Reserved
0E EC00h
0E EFFFh
1K
Reserved
0E F000h
0E F13Fh
0E F140h
0E F17Fh
0E F180h
0E F1FFh
0E F200h
0F FFFFh
10 0000h
3F FFFFh
40 0000h
7F FFFFh
Description
BIU Zone
Static Zone 0
(mapped internally
in IRE and ERE
mode; mapped to
the external bus in
DEV mode)
ol
e
te
N/A
Reserved
64
Reserved
128
Reserved
67.5K
Reserved
3072K
Reserved
4096K
External Memory Zone 1
bs
320
Static Zone 1
80 0000h
FE FFFFh
8128K
External Memory Zone 2
FF 0000h
FF FAFFh
64256
BIU Peripherals
FF FB00h
FF FBFFh
256
I/O Expansion
I/O Zone
FF FC00h
FF FFFFh
1K
Peripherals and Other I/O Ports
N/A
OPERATING ENVIRONMENT
O
6.1
Start
Address
The operating environment controls whether external memory is supported and whether the reset vector jumps to a
code space intended to support In-System Programming
(ISP). Up to 12M of external memory space is available.
Static Zone 2
gard to the states of the EMPTY bits. See Section 8.4.2 for
more details.
In the DEV environment, the on-chip flash memory is disabled, and the corresponding region of the address space
is mapped to external memory.
The operating mode of the device is controlled by the states
on the ENV[2:0] pins at reset and the states of the EMPTY
bits in the Protection Word, as shown in Table 9. Internal
pullups on the ENV[2:0] pins select IRE mode or ISP mode
if these pins are allowed to float.
When ENV[2:0] = 111b, IRE mode is selected unless the
EMPTY bits in the Protection word indicate that the program
flash memory is empty (unprogrammed), in which case ISP
mode is selected. When ENV[2:0] = 011b, ERE mode is selected unless the EMPTY bits indicate that the program
flash memory is empty, in which case ISP mode is selected.
When ENV[2:0] = 110b, ISP mode is selected without re-
25
Table 9 Operating Environment Selection
ENV[2:0] EMPTY
Operating Environment
111
No
Internal ROM enabled (IRE) mode
011
No
External ROM enabled (ERE) mode
000
N/A
Development (DEV) mode
110
N/A
In-System-Programming (ISP) mode
111
Yes
In-System-Programming (ISP) mode
011
Yes
In-System-Programming (ISP) mode
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CP3UB17
6.0
CP3UB17
6.2
BUS INTERFACE UNIT (BIU)
6.4
The BIU controls the interface between the CPU core bus
and those on-chip modules which are mapped into BIU
zones. These on-chip modules are the flash program memory and the I/O zone. The BIU controls the configured parameters for bus access (such as the number of wait states
for memory access) and issues the appropriate bus signals
for the requested access.
6.3
The BIU has a set of control registers that determine how
many wait cycles and hold cycles are to be used for accessing memory. During initialization of the system, these registers should be programmed with appropriate values so that
the minimum allowable number of cycles is used. This number varies with the clock frequency.
There are five BIU control registers, as listed in Table 10.
These registers control the bus cycle configuration used for
accessing the various on-chip memory types.
BUS CYCLES
There are four types of data transfer bus cycles:
Table 10 Bus Control Registers
Normal read
Fast read
Early write
Late write
The type of data cycle used in a particular transaction depends on the type of CPU operation (a write or a read), the
type of memory or I/O being accessed, and the access type
programmed into the BIU control registers (early/late write
or normal/fast read).
For read operations, a basic normal read takes two clock cycles, and a fast-read bus cycle takes one clock cycle. Normal read bus cycles are enabled by default after reset.
Name
Address
Description
BCFG
FF F900h
BIU Configuration Register
IOCFG
FF F902h
I/O Zone Configuration
Register
te
BIU CONTROL REGISTERS
SZCFG0
FF F904h
Static Zone 0
Configuration Register
SZCFG1
FF F906h
Static Zone 1
Configuration Register
O
bs
ol
e
Static Zone 2
For write operations, a basic late-write bus cycle takes two
SZCFG2
FF F908h
Configuration
Register
clock cycles, and a basic early-write bus cycle takes three
clock cycles. Early-write bus cycles are enabled by default
BIU Configuration Register (BCFG)
after reset. However, late-write bus cycles are needed for 6.4.1
ordinary write operations, so this configuration must be The BCFG register is a byte-wide, read/write register that
changed by software (see Section 6.4.1).
selects early-write or late-write bus cycles. At reset, the regIn certain cases, one or more additional clock cycles are ister is initialized to 07h. The register format is shown below.
added to a bus access cycle. There are two types of additional clock cycles for ordinary memory accesses, called in7
3
2
1
0
ternal wait cycles (TIW) and hold (Thold) cycles.
Reserved
1
1
EWR
A wait cycle is inserted in a bus cycle just after the memory
address has been placed on the address bus. This gives the
accessed memory more time to respond to the transaction
EWR
The Early Write bit controls write cycle timing.
request.
0 – Late-write operation (2 clock cycles to
A hold cycle is inserted at the end of a bus cycle. This holds
write).
the data on the data bus for an extended number of clock cy1 – Early-write operation.
cles.
At reset, the BCFG register is initialized to 07h, which selects early-write operation. However, late-write operation is
required for normal device operation, so software must
change the register value to 06h. Bits 1 and 2 of this register
must always be set when writing to this register.
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26
I/O Zone Configuration Register (IOCFG)
6.4.3
The IOCFG register is a word-wide, read/write register that
controls the timing and bus characteristics of accesses to
the 256-byte I/O Zone memory space (FF FB00h to FF
FBFFh). The registers associated with Port B and Port C reside in the I/O memory array. At reset, the register is initialized to 069Fh. The register format is shown below.
7
BW
6
5
Reserved
4
3
2
HOLD
15
The SZCFG0 register is a word-wide, read/write register
that controls the timing and bus characteristics of Zone 0
memory accesses. Zone 0 is used for the on-chip flash
memory (including the boot area, program memory, and
data memory).
At reset, the register is initialized to 069Fh. The register format is shown below.
0
WAIT
10
Reserved
Static Zone 0 Configuration Register (SZCFG0)
9
8
IPST
Res.
7
6
5
BW
WBR
RBE
15
4
BW
O
12
11
FRE
WAIT
10
9
IPRE IPST
8
Res.
te
bs
IPST
0
WAIT
HOLD
The Memory Wait field specifies the number
of TIW (internal wait state) clock cycles added
for each memory access, ranging from 000b
for no additional TIW wait cycles to 111b for
seven additional TIW wait cycles. These bits
are ignored if the SZCFG0.FRE bit is set.
The Memory Hold field specifies the number
of Thold clock cycles used for each memory
access, ranging from 00b for no Thold cycles
to 11b for three Thold clock cycles. These bits
are ignored if the SZCFG0.FRE bit is set.
The Read Burst Enable enables burst cycles
on 16-bit reads from 8-bit bus width regions of
the address space. Because the flash program memory is required to be 16-bit bus
width, the RBE bit is a don’t care bit. This bit
is ignored when the SZCFG0.FRE bit is set.
0 – Burst read disabled.
1 – Burst read enabled.
The Wait on Burst Read bit controls if a wait
state is added on burst read transaction. This
bit is ignored, when SZCFG0.FRE bit is set or
when SZCFG0.RBE is clear.
0 – No TBW on burst read cycles.
1 – One TBW on burst read cycles.
The Bus Width bit controls the bus width of the
zone. The flash program memory must be
configured for 16-bit bus width.
0 – 8-bit bus width.
1 – 16-bit bus width (required).
The Fast Read Enable bit controls whether
fast read bus cycles are used. A fast read operation takes one clock cycle. A normal read
operation takes at least two clock cycles.
0 – Normal read cycles.
1 – Fast read cycles.
The Post Idle bit controls whether an idle cycle
follows the current bus cycle, when the next
bus cycle accesses a different zone. No idle
cycles are required for on-chip accesses.
0 – No idle cycle (recommended).
1 – Idle cycle inserted.
ol
e
HOLD
The Memory Wait Cycles field specifies the
number of TIW (internal wait state) clock cycles added for each memory access, ranging
from 000 binary for no additional TIW wait cycles to 111 binary for seven additional TIW
wait cycles.
The Memory Hold Cycles field specifies the
number of Thold clock cycles used for each
memory access, ranging from 00b for no
Thold cycles to 11b for three Thold clock cycles.
The Bus Width bit defines the bus width of the
IO Zone.
0 – 8-bit bus width.
1 – 16-bit bus width (default)
The Post Idle bit controls whether an idle cycle
follows the current bus cycle, when the next
bus cycle accesses a different zone. No idle
cycles are required for on-chip accesses.
0 – No idle cycle (recommended).
1 – Idle cycle.
2
HOLD
Reserved
WAIT
3
RBE
WBR
BW
FRE
IPST
27
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CP3UB17
6.4.2
CP3UB17
IPRE
The Preliminary Idle bit controls whether an
idle cycle is inserted prior to the current bus
cycle, when the new bus cycle accesses a different zone. No idle cycles are required for onchip accesses.
0 – No idle cycle (recommended).
1 – Idle cycle inserted.
6.4.4
Static Zone 1 Configuration Register (SZCFG1)
The SZCFG1 register is a word-wide, read/write register
that controls the timing and bus characteristics for off-chip
accesses selected with the SEL1 output signal.
At reset, the register is initialized to 069Fh. The register format is shown below.
7
6
5
BW
WBR
RBE
15
4
2
HOLD
12
Reserved
11
FRE
10
O
bs
RBE
WBR
BW
FRE
IPST
IPRE
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28
9
IPRE IPST
8
Res.
The Memory Wait field specifies the number
of TIW (internal wait state) clock cycles added
for each memory access, ranging from 000b
for no additional TIW wait cycles to 111b for
seven additional TIW wait cycles. These bits
are ignored if the SZCFG1.FRE bit is set.
The Memory Hold field specifies the number
of Thold clock cycles used for each memory
access, ranging from 00b for no Thold cycles
to 11b for three Thold clock cycles. These bits
are ignored if the SZCFG1.FRE bit is set.
The Read Burst Enable enables burst cycles
on 16-bit reads from 8-bit bus width regions of
the address space. This bit is ignored when
the SZCFG1.FRE bit is set or the
SZCFG1.BW is clear.
0 – Burst read disabled.
1 – Burst read enabled.
The Wait on Burst Read bit controls if a wait
state is added on burst read transaction. This
bit is ignored, when SZCFG1.FRE bit is set or
when SZCFG1.RBE is clear.
0 – No TBW on burst read cycles.
1 – One TBW on burst read cycles.
The Bus Width bit controls the bus width of the
zone.
0 – 8-bit bus width.
1 – 16-bit bus width.
The Fast Read Enable bit controls whether
fast read bus cycles are used. A fast read operation takes one clock cycle. A normal read
operation takes at least two clock cycles.
0 – Normal read cycles.
1 – Fast read cycles.
The Post Idle bit controls whether an idle cycle
follows the current bus cycle, when the next
bus cycle accesses a different zone.
0 – No idle cycle.
1 – Idle cycle inserted.
The Preliminary Idle bit controls whether an
idle cycle is inserted prior to the current bus
cycle, when the new bus cycle accesses a different zone.
0 – No idle cycle.
1 – Idle cycle inserted.
ol
e
HOLD
0
WAIT
te
WAIT
3
Static Zone 2 Configuration Register (SZCFG2) 6.5
WAIT AND HOLD STATES
The SZCFG2 register is a word-wide, read/write register The number of wait cycles and hold cycles inserted into a
that controls the timing and bus characteristics for off-chip bus cycle depends on whether it is a read or write operation,
accesses selected with the SEL2 output signal.
the type of memory or I/O being accessed, and the control
At reset, the register is initialized to 069Fh. The register for- register settings.
mat is shown below.
7
6
5
BW
WBR
RBE
15
WBR
HOLD
FRE
IPST
IPRE
When the CPU accesses the Flash program and data memory (address ranges 000000h–03FFFFh and 0E0000h–
0E1FFFh), the number of added wait and hold cycles depends on the type of access and the BIU register settings.
0
WAIT
11
10
9
8
FRE
IPRE
IPST
Res.
In fast-read mode (SZCFG0.FRE=1), a read operation is a
single cycle access. This limits the maximum CPU operating frequency to 24 MHz.
te
For
a
read
operation
in
normal-read
mode
(SZCFG0.FRE=0), the number of inserted wait cycles is
The Memory Wait field specifies the number specified in the SZCFG0.WAIT field. The total number of
of TIW (internal wait state) clock cycles added wait cycles is the value in the WAIT field plus 1, so it can
for each memory access, ranging from 000b range from 1 to 8. The number of inserted hold cycles is
for no additional TIW wait cycles to 111b for specified in the SCCFG0.HOLD field, which can range from
seven additional TIW wait cycles. These bits 0 to 3.
are ignored if the SZCFG2.FRE bit is set.
For a write operation in fast read mode (SZCFG0.FRE=1),
The Memory Hold field specifies the number
the number of inserted wait cycles is 1. No hold cycles are
of Thold clock cycles used for each memory
used.
access, ranging from 00b for no Thold cycles
to 11b for three Thold clock cycles. These bits For a write operation normal read mode (SZCFG0.FRE=0),
the number of wait cycles is equal to the value written to the
are ignored if the SZCFG2.FRE bit is set.
The Read Burst Enable enables burst cycles SZCFG0.WAIT field plus 1 (in the late write mode) or 2 (in
on 16-bit reads from 8-bit bus width regions of the early write mode). The number of inserted hold cycles is
the address space. This bit is ignored when equal to the value written to the SCCFG0.HOLD field, which
the SZCFG2.FRE bit is set or the can range from 0 to 3.
SZCFG2.BW is clear.
6.5.2
RAM Memory
0 – Burst read disabled.
Read and write accesses to on-chip RAM is performed with1 – Burst read enabled.
The Wait on Burst Read bit controls if a wait in a single cycle, without regard to the BIU settings. The
state is added on burst read transaction. This RAM address is in the range of 0E 8000h–0E 91FFh and 0E
bit is ignored, when SZCFG2.FRE bit is set or C000h–0E EBFFh.
when SZCFG2.RBE is clear.
0 – No TBW on burst read cycles.
1 – One TBW on burst read cycles.
The Bus Width bit controls the bus width of the
zone.
0 – 8-bit bus width.
1 – 16-bit bus width.
The Fast Read Enable bit controls whether
fast read bus cycles are used. A fast read operation takes one clock cycle. A normal read
operation takes at least two clock cycles.
0 – Normal read cycles.
1 – Fast read cycles.
The Post Idle bit controls whether an idle cycle
follows the current bus cycle, when the next
bus cycle accesses a different zone.
0 – No idle cycle.
1 – Idle cycle inserted.
The Preliminary Idle bit controls whether an
idle cycle is inserted prior to the current bus
cycle, when the new bus cycle accesses a different zone.
0 – No idle cycle.
1 – Idle cycle inserted.
O
BW
2
Flash Program/Data Memory
ol
e
RBE
3
bs
HOLD
4
12
Reserved
WAIT
6.5.1
6.5.3
Access to Peripherals
When the CPU accesses on-chip peripherals in the range of
0E F000h–0E F1FFh and FF 0000h–FF FBFFh, one wait
cycle and one preliminary idle cycle is used. No hold cycles
are used. The IOCFG register determines the access timing
for the address range FF FB00h–FF FBFFh.
29
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CP3UB17
6.4.5
CP3UB17
7.0
System Configuration Registers
The system configuration registers control and provide status for certain aspects of device setup and operation, such
as indicating the states sampled from the ENV[2:0] inputs.
The system configuration registers are listed in Table 11.
MISC_IO_SPEED The MISC_IO_SPEED bit controls the slew
rate of the output drivers for the ENV[2:0],
RDY, RFDATA, and TDO pins. To minimize
noise, the slow slew rate is recommended.
0 – Fast slew rate.
1 – Slow slew rate.
MEM_IO_SPEED The MEM_IO_SPEED bit controls the slew
rate of the output drivers for the A[21:0], RD,
SEL[2:1], and WR[1:0] pins. Memory speeds
for the CP3UB17 are characterized with fast
slew rate. Slow slew rate reduces the available memory access time by 5 ns.
0 – Fast slew rate.
1 – Slow slew rate.
Table 11 System Configuration Registers
Address
Description
MCFG
FF F910h
Module Configuration
Register
MSTAT
FF F914h
Module Status
Register
MODULE CONFIGURATION REGISTER
(MCFG)
7.2
The MCFG register is a byte-wide, read/write register that
selects the clock output features of the device.
The register must be written in active mode only, not in power save, HALT, or IDLE mode. However, the register contents are preserved during all power modes.
The MSTAT register is a byte-wide, read-only register that
indicates the general status of the device. The MSTAT register format is shown below.
7
5
4
3
2
1
0
Reserved DPGMBUSY PGMBUSY OENV2 OENV1 OENV0
ol
e
The MCFG register format is shown below.
MODULE STATUS REGISTER (MSTAT)
te
7.1
Name
The Operating Environment bits hold the
states sampled from the ENV[2:0] input pins
MEM_IO MISC_IO
USB
SCLK MCLK PLLCLK EXI
Res.
at reset. These states are controlled by exter_SPEED _SPEED _ENABLE OE
OE
OE
OE
nal hardware at reset and are held constant in
the register until the next reset.
PGMBUSY The Flash Programming Busy bit is automatiEXIOE
The EXIOE bit controls whether the external
cally set when either the program memory or
bus is enabled in the IRE environment for imthe data memory is being programmed or
plementing the I/O Zone (FF FB00h–FF
erased. It is clear when neither of the memoFBFFh).
ries is busy. When this bit is set, software must
0 – External bus disabled.
not attempt to program or erase either of
1 – External bus enabled.
these two memories. This bit is a copy of the
PLLCLKOE The PLLCLKOE bit controls whether the PLL
FMBUSY bit in the FMSTAT register.
clock is driven on the ENV0/PLLCLK pin.
0 – Flash memory is not busy.
0 – ENV0/PLLCLK pin is high impedance.
1 – Flash memory is busy.
1 – PLL clock driven on ENV0/PLLCLK.
DPGMBUSY The Data Flash Programming Busy indicates
MCLKOE
The MCLKOE bit controls whether the Main
that the flash data memory is being erased or
Clock is driven on the ENV1/CPUCLK pin.
a pipelined programming sequence is current0 – ENV1/CPUCLK pin is high impedance.
ly ongoing. Software must not attempt to per1 – Main Clock is driven on ENV1/CPUCLK.
form any write access to the flash program
SCLKOE
The SCLKOE bit controls whether the Slow
memory at this time, without also polling the
Clock is driven on the ENV2/SLOWCLK pin.
FSMSTAT.FMFULL bit in the flash memory in0 – ENV2/SLOWCLK pin is high impedance.
terface. The DPGMBUSY bit is a copy of the
1 – Slow Clock driven on ENV2/SLOWCLK.
FMBUSY bit in the FSMSTAT register.
USB_ENABLE The USB_ENABLE bit can be used to force
0 – Flash data memory is not busy.
an external USB transceiver into its low-power
1 – Flash data memory is busy.
mode. The power mode is dependent on the
USB controller status, the USB_ENABLE bit
in the Function Word (see Section 8.4.1), and
the USB_ENABLE bit in the MCFG register.
0 – External USB transceiver forced into lowpower mode.
1 – Transceiver power mode dependent on
USB controller status and programming
of the Function Word. (This is the state of
the USB_ENABLE bit after reset.)
6
5
4
3
2
1
OENV[2:0]
0
O
bs
7
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30
Flash Memory
The flash memory consists of the flash program memory default (after reset) all bits in the FM0WER, FM1WER, and
and the flash data memory. The flash program memory is FSM0WER registers are cleared, which disables write acfurther divided into the Boot Area and the Code Area.
cess by the CPU to all sections. Write access to a section is
A special protection scheme is applied to the lower portion enabled by setting the corresponding write enable bit. After
of the flash program memory, called the Boot Area. The completing a programming or erase operation, software
Boot Area always starts at address 0 and ranges up to a should clear all write enable bits to protect the flash program
programmable end address. The maximum boot area ad- memory against any unintended writes.
dress which can be selected is 00 1BFFh. The intended use
of this area is to hold In-System-Programming (ISP) routines or essential application routines. The Boot Area is always protected against CPU write access, to avoid
unintended modifications.
8.1.2
Global Protection
te
The WRPROT field in the Protection Word controls global
write protection. The Protection Word is located in a special
flash memory outside of the CPU address space. If a majority of the bits in the 3-bit WRPROT field are clear, write proThe Code Area is intended to hold the application code and tection is enabled. Enabling this mode prevents the CPU
constant data. The Code Area begins with the next byte af- from writing to flash memory.
ter the Boot Area. Table 12 summarizes the properties of
The RDPROT field in the Protection Word controls global
the regions of flash memory mapped into the CPU address
read protection. If a majority of the bits in the 3-bit RDPROT
space.
field are clear, read protection is enabled. Enabling this
Table 12 Flash Memory Areas
mode prevents reading by an external debugger through the
serial debug interface or by an external flash programmer.
Read
Write Access CPU read access is not affected by the RDPROT bits.
Area
Address Range
Access
8.2
Data
Area
Yes
No
Each of the flash memories are divided into main blocks and
information blocks. The main blocks hold the code or data
used by application software. The information blocks hold
factory parameters, protection settings, and other devicespecific data. The main blocks are mapped into the CPU address space. The information blocks are accessed indirectly
through a register-based interface. Separate sets of registers are provided for accessing flash program memory (FM
registers) and flash data memory (FSM registers). The flash
program memory consists of two main blocks and two data
blocks, as shown in Table 13. The flash data memory consists of one main block and one information block.
Yes
Write access
only if section
write enable
bit is set and
global write
protection is
disabled.
Write access
only if section
write enable
bit is set and
global write
protection is
disabled.
0E 0000h–0E 1FFFh
Yes
The memory protection mechanisms provide both global
and section-level protection. Section-level protection
against CPU writes is applied to individual 8K-byte sections
of the flash program memory and 512-byte sections of the
flash data memory. Section-level protection is controlled
through read/write registers mapped into the CPU address
space. Global write protection is applied at the device level,
to disable flash memory writes by the CPU. Global write protection is controlled by the encoding of bits stored in the
flash memory array.
8.1.1
Table 13 Flash Memory Blocks
Name
Address Range
Function
Main Block 0
00 0000h–01 FFFFh
(CPU address space)
Flash Program
Memory
Information
Block 0
000h–07Fh
(address register)
Function Word,
Factory
Parameters
Main Block 1
02 0000h–03 FFFFh
(CPU address space)
Flash Program
Memory
Information
Block 1
080h–0FFh
(address register)
Protection Word,
User Data
Main Block 2
0E 0000h–0E 1FFFh
(CPU address space)
Flash Data
Memory
FLASH MEMORY PROTECTION
O
8.1
BOOTAREA–03
FFFFh
FLASH MEMORY ORGANIZATION
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Code
Area
0–BOOTAREA - 1
bs
Boot
Area
Section-Level Protection
Information
000h–07Fh
User Data
(address register)
Block 2
Each bit in the Flash Memory Write Enable (FM0WER and
FM1WER) registers enables or disables write access to a
corresponding section of flash program memory. Write ac- 8.2.1
Main Block 0 and 1
cess to the flash data memory is controlled by the bits in the
Main Block 0 and Main Block 1 hold the 256K-byte program
Flash Slave Memory Write Enable (FSM0WER) register. By
space, which consists of the Boot Area and Code Area.
31
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CP3UB17
8.0
CP3UB17
Each block consists of sixteen 8K-byte sections. Write access by the CPU to Main Block 0 and Main Block 1 is controlled by the corresponding bits in the FM0WER and
FM1WER registers, respectively. The least significant bit in
each register controls the section at the lowest address.
8.2.2
8.2.5
Information Block 2
Information Block 2 contains 128 bytes, which can be used
to store user data. The CPU can always read Information
Block 2. The CPU can write Information Block 2 only when
global write protection is disabled. Erasing Information
Block 2 also erases Main Block 2.
Information Block 0
Information Block 0 contains 128 bytes, of which one 16-bit
word has a dedicated function, called the Function Word.
The Function Word resides at address 07Eh. It controls the
power mode of an external USB transceiver. The remaining
Information Block 0 locations are used to hold factory parameters.
8.3
FLASH MEMORY OPERATIONS
Function
Word
07Eh–07Fh
Other (Used
for Factory
Parameters)
000h–07Dh
Information Block 1
progress. When the FMFULL bit in the FMSTAT or FSMSTAT register is clear, the pipeline is ready to receive a new
request. New requests may be loaded after checking only
the FMFULL bit.
No
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8.2.3
Yes
te
Flash memory programming (erasing and writing) can be
performed on the flash data memory while the CPU is executing out of flash program memory. Although the CPU can
execute out of flash data memory, it cannot erase or write
the flash program memory while executing from flash data
Software only has read access to Information Block 0 memory. To erase or write the flash program memory, the
through a register-based interface. The Function Word and CPU must be executing from the on-chip static RAM or offthe factory parameters are protected against CPU writes. chip memory.
Table 14 shows the structure of Information Block 0.
An erase operation is required before programming. An
Table 14 Information Block 0
erase operation sets all of the bits in the erased region. A
programming operation clears selected bits.
Address
Read
The programming mechanism is pipelined, so that a new
Name
Write Access
Range
Access
write request can be loaded while a previous request is in
8.3.1
bs
Information Block 1 contains 128 bytes, of which one 16-bit
word has a dedicated function, called the Protection Word.
The Protection Word resides at address 0FEh. It controls
the global protection mechanisms and the size of the Boot
Area. The Protection Word can be written by the CPU, however the changes only become valid after the next device reset. The remaining Information Block 1 locations can be
used to store other user data. Erasing Information Block 1
also erases Main Block 1. Table 15 shows the structure of
the Information Block 1.
Table 15 Information Block 1
Address
Range
Protection
Word
0FEh–0FFh
Read
Access
Write Access
Yes
Write access only
if section write
enable bit is set
and global write
protection is disabled.
O
Name
Other
(User Data)
8.2.4
080h–0FDh
Main Block 2 holds the 8K-byte data area, which consists of
sixteen 512-byte sections. Write access by the CPU to Main
Block 2 is controlled by the corresponding bits in the
FSM0WER register. The least significant bit in the register
controls the section at the lowest address.
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8.3.2
32
Information Block Read
Information block data is read through the register-based interface. Only word read operations are supported and the
read address must be word-aligned (LSB = 0). The following
steps are used to read from an information block:
1. Load the word address in the Flash Memory Information Block Address (FMIBAR) or Flash Slave Memory
Information Block Address (FSMIBAR) register.
2. Read the data word by reading out the Flash Memory
Information Block Data (FMIBDR) or Flash Slave Memory Information Block Data (FSMIBDR) register.
8.3.3
Main Block 2
Main Block Read
Read accesses from flash program memory can only occur
when the flash program memory is not busy from a previous
write or erase operation. Read accesses from the flash data
memory can only occur when both the flash program memory and the flash data memory are not busy. Both byte and
word read operations are supported.
Main Block Page Erase
A flash erase operation sets all of the bits in the erased region. Pages of a main block can be individually erased if
their write enable bits are set. This method cannot be used
to erase the boot area, if defined. Each page in Main Block
0 and 1 consists of 1024 bytes (512 words). Each page in
Main Block 2 consists of 512 bytes (256 words). To erase a
page, the following steps are performed:
1. Verify that the Flash Memory Busy (FMBUSY) bit is
clear. The FMBUSY bit is in the FMSTAT or FSMSTAT
register.
2. Prevent accesses to the flash memory while erasing is
in progress.
8.3.4
1. Verify that the Flash Memory Busy (FMBUSY) bit is
clear. The FMBUSY bit is in the FMSTAT or FSMSTAT
register.
2. Prevent accesses to the flash memory while the write
is in progress.
3. Set the Program Enable (PE) bit. The PE bit is in the
FMCTRL or FSMCTRL register.
4. Write a word to the desired word-aligned address. This
starts a new pipelined programming sequence. The
FMBUSY bit becomes set while the write operation is in
progress. The FMFULL bit in the FMSTAT or FSMSTAT
register becomes set if a previous write operation is still
in progress.
5. Wait until the FMFULL bit becomes clear.
6. Repeat steps 4 and 5 for additional words.
7. Wait until the FMBUSY bit becomes clear again.
8. Check the programming error (PERR) bit to confirm
successful programming. The PERR bit is in the FMSTAT or FSMSTAT register.
9. Clear the Program Enable (PE) bit.
Main Block Module Erase
8.3.7
Information Block Write
Writing is only allowed when global write protection is disabled. Writing by the CPU is only allowed when the write enable bit is set for the sector which contains the word to be
written. The CPU cannot write Information Block 0. Only
word-wide write access to word-aligned addresses is supported. The following steps are performed to write a word:
ol
e
1. Verify that the Flash Memory Busy (FMBUSY) bit is
clear. The FMBUSY bit is in the FMSTAT or FSMSTAT
register.
2. Prevent accesses to the flash memory while erasing is
in progress.
3. Set the Module Erase (MER) bit. The MER bit is in the
FMCTRL or FSMCTRL register.
4. Write to any address within the desired main block.
5. Wait until the FMBUSY bit becomes clear again.
6. Check the Erase Error (EERR) bit to confirm successful
erase of the block. The EERR bit is in the FMSTAT or
FSMSTAT register.
7. Clear the MER bit.
te
A module erase operation can be used to erase an entire
main block. All sections within the block must be enabled for
writing. If a boot area is defined in the block, it cannot be
erased. The following steps are performed to erase a main
block:
O
bs
1. Verify that the Flash Memory Busy (FMBUSY) bit is
clear. The FMBUSY bit is in the FMSTAT or FSMSTAT
8.3.5
Information Block Module Erase
register.
Erasing an information block also erases the corresponding 2. Prevent accesses to the flash memory while the write
main block. If a boot area is defined in the main block, neiis in progress.
ther block can be erased. Page erase is not supported for 3. Set the Program Enable (PE) bit. The PE bit is in the
information blocks. The following steps are performed to
FMCTRL or FSMCTRL register.
erase an information block:
4. Write the desired target address into the FMIBAR or
FSMIBAR register.
1. Verify that the Flash Memory Busy (FMBUSY) bit is
5.
Write the data word into the FMIBDR or FSMIBDR regclear. The FMBUSY bit is in the FMSTAT or FSMSTAT
ister. This starts a new pipelined programming seregister.
quence. The FMBUSY bit becomes set while the write
2. Prevent accesses to the flash memory while erasing is
operation is in progress. The FMFULL bit in the FMin progress.
STAT or FSMSTAT register becomes set if a previous
3. Set the Module Erase (MER) bit. The MER bit is in the
write operation is still in progress.
FMCTRL or FSMCTRL register.
4. Load the FMIBAR or FSMIBAR register with any ad- 6. Wait until the FMFULL bit becomes clear.
dress within the block, then write any data to the FMIB- 7. Repeat steps 4 through 6 for additional words.
8. Wait until the FMBUSY bit becomes clear again.
DR or FSMIBDR register.
9. Check the programming error (PERR) bit to confirm
5. Wait until the FMBUSY bit becomes clear again.
successful programming. The PERR bit is in the FM6. Check the Erase Error (EERR) bit to confirm successful
STAT or FSMSTAT register.
erase of the block. The EERR bit is in the FMSTAT or
10.
Clear the Program Enable (PE) bit.
FSMSTAT register.
7. Clear the MER bit.
8.3.6
8.4
Main Block Write
Writing is only allowed when global write protection is disabled. Writing by the CPU is only allowed when the write enable bit is set for the sector which contains the word to be
written. The CPU cannot write the Boot Area. Only wordwide write access to word-aligned addresses is supported.
The following steps are performed to write a word:
INFORMATION BLOCK WORDS
Two words in the information blocks are dedicated to hold
settings that affect the operation of the system: the Function
Word in Information Block 0 and the Protection Word in Information Block 1.
33
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CP3UB17
3. Set the Page Erase (PER) bit. The PER bit is in the FMCTRL or FSMCTRL register.
4. Write to an address within the desired page.
5. Wait until the FMBUSY bit becomes clear again.
6. Check the Erase Error (EERR) bit to confirm successful
erase of the page. The EERR bit is in the FMSTAT or
FSMSTAT register.
7. Repeat steps 4 through 6 to erase additional pages.
8. Clear the PER bit.
Function Word
Table 16 Boot Area Encodings
The Function Word resides in the Information Block 0 at address 07Eh. At reset, the Function Word is copied into the
FMAR0 register.
15
BOOT
AREA
Size of the Boot
Area
Code Area
Start
Address
0
001
6144 bytes
00 1800h
USB_ENABLE
000
7168 bytes
00 1C00h
1
Reserved
USB_ENABLE The USB_ENABLE bit can be used to force
an external USB transceiver into its low-power
mode. The power mode is dependent on the
USB controller status, the USB_ENABLE bit
in the MCFG register (see Section 7.1), and
the USB_ENABLE bit in the Function Word.
0 – External USB transceiver forced into lowpower mode.
1 – Transceiver power mode dependent on
USB controller status and programming
of the Function Word.
8.4.2
Protection Word
EMPTY
13
12
10
9
7
WRPROT RDPROT ISPE
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The Protection Word resides in Information Block 1 at adISPE
dress 0FEh. At reset, the Protection Word is copied into the
FMAR1 register.
15
The EMPTY field indicates whether the flash
program memory has been programmed or
should be treated as blank. If a majority of the
three EMPTY bits are clear, the flash program
memory is treated as programmed. If a majority of the EMPTY bits are set, the flash program memory is treated as empty. If the
ENV[1:0] inputs (see Section 6.1) are sampled high at reset and the EMPTY bits indicate
the flash program memory is empty, the device will begin execution in ISP mode. The device enters ISP mode without regard to the
EMPTY status if ENV0 is driven low and
ENV1 is driven high.
The ISPE field indicates whether the Boot
Area is used to hold In-System-Programming
routines or user application routines. If a majority of the three ISPE bits are set, the Boot
Area holds ISP routines. If majority of the
ISPE bits are clear, the Boot Area holds user
application routines. Table 17 summarizes all
possible EMPTY, ISPE, and Boot Area settings and the corresponding start-up operation for each combination. In DEV mode, the
EMPTY bit settings are ignored and the CPU
always starts executing from address 0.
te
CP3UB17
8.4.1
6
4
3
1
0
EMPTY BOOTAREA 1
O
bs
BOOTAREA The BOOTAREA field specifies the size of the
Boot Area. The Boot Area starts at address 0
and ends at the address specified by this field.
The inverted bits of the BOOTAREA field
count the number of 1024-byte blocks to be
reserved as the Boot Area. The maximum
Boot Area size is 7K bytes (address range 0 to
1BFFh). The end of the Boot Area defines the
start of the Code Area. If the device starts in
ISP mode and there is no Boot Area defined
(encoding 111b), the device is kept in reset.
Table 16 lists all possible boot area encodings.
Table 17 CPU Reset Behavior
EMPTY
Not Empty
ISPE
Boot Area
Start-Up Operation
ISP
Defined
Device starts in IRE/
ERE mode from
Code Area start
address
Device starts in IRE/
ERE mode from
Code Area start
address
Table 16 Boot Area Encodings
ISP
Size of the Boot
Area
Code Area
Start
Address
Not Empty
BOOT
AREA
Not
Defined
111
No Boot Area defined
00 0000h
Not Empty
No ISP
Don’t Care
110
1024 bytes
00 0400h
Device starts in IRE/
ERE mode from
address 0
101
2048 bytes
00 0800h
Empty
ISP
Defined
100
3072 bytes
00 0C00h
Device starts in ISP
mode from Code
Area start address
011
4096 bytes
00 1000h
Empty
ISP
Not
Defined
010
5120 bytes
00 1400h
Empty
No ISP
Don’t Care
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34
Device starts in ISP
mode and is kept in
its reset state
8.5
FLASH MEMORY INTERFACE
REGISTERS
Program
Memory
Data
Memory
Description
FMPROG
FF F956h
FSMPROG
FF F756h
Flash Memory
Programming Time
Reload Register
FMPERASE
FF F958h
FSMPERASE
FF F758h
Flash Memory Page
Erase Time Reload
Register
FMMERASE0
FF F95Ah
FSMMERASE0
FF F75Ah
Flash Memory Module
Erase Time Reload
Register 0
FMEND
FF F95Eh
FSMEND
FF F75Eh
Flash Memory End
Time Reload Register
Table 18 Flash Memory Interface Registers
Data
Memory
FMIBAR
FF F940h
FSMIBAR
FF F740h
Description
Flash Memory
Information Block
Address Register
FSMMEND
FF F760h
Flash Memory Module
Erase End Time
Reload Register
FMRCV
FF F962h
FSMRCV
FF F762h
Flash Memory
Recovery Time
Reload Register
FSMIBDR
FF F742h
Flash Memory
Information Block
Address Register
FM0WER
FF F944h
FSM0WER
FF F744h
Flash Memory 0
Write Enable Register
FM1WER
FF F946h
N/A
Flash Memory 1
Write Enable Register
FMCTRL
FF F94Ch
FSMCTRL
FF F74Ch
Flash Memory
Control Register
O
FMIBDR
FF F942h
FMSTAT
FF F94Eh
FSMSTAT
FF F74Eh
Flash Memory
Status Register
FMPSR
FF F950h
FSMPSR
FF F750h
Flash Memory
Prescaler Register
FMSTART
FF F952h
FSMSTART
FF F752h
Flash Memory Start
Time Reload Register
FMTRAN
FF F954h
FSMTRAN
FF F754h
Flash Memory
Transition Time
Reload Register
FMAR0
FF F964h
FSMAR0
FF F764h
Flash Memory
Auto-Read Register 0
FMAR1
FF F966h
FSMAR1
FF F766h
Flash Memory
Auto-Read Register 1
FMAR2
FF F968h
FSMAR2
FF F768h
Flash Memory
Auto-Read Register 2
8.5.1
bs
Program
Memory
FMMEND
FF F960h
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There is a separate interface for the program flash and data
flash memories. The same set of registers exist in both interfaces. In most cases they are independent of each other,
but in some cases the program flash interface controls the
interface for both memories, as indicated in the following
sections. Table 18 lists the registers.
Table 18 Flash Memory Interface Registers
te
WRPROT
The RDPROT field controls the global read
protection mechanism for the on-chip flash
program memory. If a majority of the three
RDPROT bits are clear, the flash program
memory is protected against read access
from the serial debug interface or an external
flash programmer. CPU read access is not affected by the RDPROT bits. If a majority of the
RDPROT bits are set, read access is allowed.
The WRPROT field controls the global write
protection mechanism for the on-chip flash
program memory. If a majority of the three
WRPROT bits are clear, the flash program
memory is protected against write access
from any source and read access from the serial debug interface. If a majority of the WRPROT bits are set, write access is allowed.
CP3UB17
RDPROT
Flash Memory Information Block Address
Register (FMIBAR/FSMIBAR)
The FMIBAR register specifies the 8-bit address for read or
write access to an information block. Because only word access to the information blocks is supported, the least significant bit (LSB) of the FMIBAR must be 0 (word-aligned). The
hardware automatically clears the LSB, without regard to
the value written to the bit. The FMIBAR register is cleared
after device reset. The CPU bus master has read/write access to this register.
15
8
Reserved
IBA
35
7
0
IBA
The Information Block Address field holds the
word-aligned address of an information block
location accessed during a read or write
transaction. The LSB of the IBA field is always
clear.
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CP3UB17
8.5.2
Flash Memory Information Block Data Register
(FMIBDR/FSMIBDR)
8.5.4
The FMIBDR register holds the 16-bit data for read or write
access to an information block. The FMIBDR register is
cleared after device reset. The CPU bus master has read/
write access to this register.
15
Flash Memory 1 Write Enable Register
(FM1WER)
The FM1WER register controls write protection for the second half of the program flash memory. The data block is divided into 16 8K-byte sections. Each bit in the FM1WER
register controls write protection for one of these sections.
The FM1WER register is cleared after device reset, so the
flash memory is write protected after reset. The CPU bus
master has read/write access to this registers.
0
IBD
15
8.5.3
The Information Block Data field holds the
data word for access to an information block.
For write operations the IBD field holds the
data word to be programmed into the informa- FM1WEn
tion block location specified by the IBA address. During a read operation from an
information block, the IBD field receives the
data word read from the location specified by
the IBA address.
Flash Memory 0 Write Enable Register
(FM0WER/FSM0WER)
The Flash Memory 1 Write Enable n bits control write protection for a section of a flash
memory data block. The address mapping of
the register bits is shown below.
Bit
Logical Address Range
0
02 0000h–02 1FFFh
1–14
...
15
bs
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e
The FM0WER register controls section-level write protection for the first half of the flash program memory. The
FMS0WER registers controls section-level write protection
for the flash data memory. Each data block is divided into 16
8K-byte sections. Each bit in the FM0WER and FSM0WER
registers controls write protection for one of these sections.
The FM0WER and FSM0WER registers are cleared after
device reset, so the flash memory is write protected after reset. The CPU bus master has read/write access to this registers.
FM1WE
te
IBD
0
0
15
8.5.5
03 E000h–03 FFFFh
Flash Data Memory 0 Write Enable Register
(FSM0WER)
The FSM0WER register controls write protection for the
flash data memory. The data block is divided into 16 512byte sections. Each bit in the FSM0WER register controls
write protection for one of these sections. The FSM0WER
register is cleared after device reset, so the flash memory is
write protected after reset. The CPU bus master has read/
write access to this registers.
FM0WE
The Flash Memory 0 Write Enable n bits control write protection for a section of a flash
memory data block. The address mapping of
FSM0WEn
the register bits is shown below.
O
FM0WEn
15
Bit
Logical Address Range
0
00 0000h–00 1FFFh
1–14
...
15
01 E000h–01 FFFFh
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36
0
FSM0WE
The Flash Data Memory 0 Write Enable n bits
control write protection for a section of a flash
memory data block. The address mapping of
the register bits is shown below.
Bit
Logical Address Range
0
0E 0000h–0E 01FFh
1–14
...
15
0E 1E00h–0E 1FFFh
Flash Memory Control Register (FMCTRL/
FSMCTRL)
PER
The Page Erase Enable bit controls whether a
a valid write operation triggers an erase operation on a 1024-byte page of flash memory.
Page erase operations are only supported for
the main blocks, not the information blocks. A
page erase operation on an information block
is ignored and does not alter the information
block. When the PER bit is set, the PE and
MER bits must be clear. This bit must not be
changed while the flash program memory is
busy being programmed or erased.
0 – Page erase mode disabled. Write operations are performed normally.
1 – A valid write operation to a word location
in program memory erases the page that
contains the word.
The Module Erase Enable bit controls whether a valid write operation triggers an erase operation on an entire block of flash memory. If
an information block is written in this mode,
both the information block and its corresponding main block are erased. When the MER bit
is set, the PE and PER bits must be clear. This
bit must not be changed while the flash program memory is busy being programmed or
erased.
0 – Module erase mode disabled. Write operations are performed normally.
1 – A valid write operation to a word location
in a main block erases the block that contains the word. A valid write operation to a
word location in an information block
erases the block that contains the word
and its associated main block.
This register controls the basic functions of the Flash program memory. The register is clear after device reset. The
CPU bus master has read/write access to this register.
7
6
5
4
3
2
1
0
MER PER PE IENPROG DISVRF Res. CWD LOWPRW
MER
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CWD
The Low Power Mode controls whether flash
program memory is operated in low-power
mode, which draws less current when data is
read. This is accomplished be only accessing
the flash program memory during the first half
of the clock period. The low-power mode must
not be used at System Clock frequencies
above 25 MHz, otherwise a read access may
return undefined data. This bit must not be
changed while the flash program memory is
busy being programmed or erased.
0 – Normal mode.
1 – Low-power mode.
The CPU Write Disable bit controls whether
the CPU has write access to flash memory.
This bit must not be changed while FMBUSY
is set.
0 – The CPU has write access to the flash
memory
1 – An external debugging tool is the current
“owner” of the flash memory interface, so
write accesses by the CPU are inhibited.
The Disable Verify bit controls the automatic
verification feature. This bit must not be
changed while the flash program memory is
busy being programmed or erased.
0 – New flash program memory contents are
automatically verified after programming.
1 – Automatic verification is disabled.
The Interrupt Enable for Program bit is clear
after reset. The flash program and data memories share a single interrupt channel but have
independent interrupt enable control bits.
0 – No interrupt request is asserted to the
ICU when the FMFULL bit is cleared.
1 – An interrupt request is made when the
FMFULL bit is cleared and new data can
be written into the write buffer.
The Program Enable bit controls write access
of the CPU to the flash program memory. This
bit must not be altered while the flash program
memory is busy being programmed or erased.
The PER and MER bits must be clear when
this bit is set.
0 – Programming the flash program memory
by the CPU is disabled.
1 – Programming the flash program memory
is enabled.
te
LOWPRW
bs
DISVRF
O
IENPROG
PE
8.5.7
Flash Memory Status Register (FMSTAT/
FSMSTAT)
This register reports the currents status of the on-chip Flash
memory. The FLSR register is clear after device reset. The
CPU bus master has read/write access to this register.
7
5
Reserved
EERR
37
4
3
2
1
0
DERR FMFULL FMBUSY PERR EERR
The Erase Error bit indicates whether an error
has occurred during a page erase or module
(block) erase. After an erase error occurs,
software can clear the EERR bit by writing a 1
to it. Writing a 0 to the EERR bit has no effect.
Software must not change this bit while the
flash program memory is busy being programmed or erased.
0 – The erase operation was successful.
1 – An erase error occurred.
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CP3UB17
8.5.6
7
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5
4
Reserved
FTDIV
8.5.9
O
DERR
Flash Memory Prescaler Register (FMPSR/
FSMPSR)
The FMPSR register is a byte-wide read/write register that
selects the prescaler divider ratio. The CPU must not modify
this register while an erase or programming operation is in
progress (FMBUSY is set). At reset, this register is initialized to 04h if the flash memory is idle. The CPU bus master
has read/write access to this register.
bs
FMFULL
8.5.8
0
FTDIV
The prescaler divisor scales the frequency of
the System Clock by a factor of (FTDIV + 1).
Flash Memory Start Time Reload Register
(FMSTART/FSMSTART)
te
FMBUSY
The Program Error bit indicates whether an
error has occurred during programming. After
a programming error occurs, software can
clear the PERR bit by writing a 1 to it. Writing
a 0 to the PERR bit has no effect. Software
must not change this bit while the flash program memory is busy being programmed or
erased.
0 – The programming operation was successful.
1 – A programming error occurred.
The Flash Memory Busy bit indicates whether
the flash memory (either main block or information block) is busy being programmed or
erased. During that time, software must not
request any further flash memory operations.
If such an attempt is made, the CPU is
stopped as long as the FMBUSY bit is active.
The CPU must not attempt to read from program memory (including instruction fetches)
while it is busy.
0 – Flash memory is ready to receive a new
erase or programming request.
1 – Flash memory busy with previous erase
or programming operation.
The Flash Memory Buffer Full bit indicates
whether the write buffer for programming is
full or not. When the buffer is full, new erase
and write requests may not be made. The
IENPROG bit can be enabled to trigger an interrupt when the buffer is ready to receive a
new request.
0 – Buffer is ready to receive new erase or
write requests.
1 – Buffer is full. No new erase or write requests can be accepted.
The Data Loss Error bit indicates that a buffer
overrun has occurred during a programming
sequence. After a data loss error occurs, software can clear the DERR bit by writing a 1 to
it. Writing a 0 to the DERR bit has no effect.
Software must not change this bit while the
flash program memory is busy being programmed or erased.
0 – No data loss error occurred.
1 – Data loss error occurred.
The FMSTART/FSMSTART register is a byte-wide read/
write register that controls the program/erase start delay
time. Software must not modify this register while a program/erase operation is in progress (FMBUSY set). At reset, this register is initialized to 18h if the flash memory is
idle. The CPU bus master has read/write access to this register.
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CP3UB17
PERR
38
7
0
FTSTART
FTSTART
The Flash Timing Start Delay Count field generates a delay of (FTSTART + 1) prescaler
output clocks.
Flash Memory Transition Time Reload
Register (FMTRAN/FSMTRAN)
8.5.13
The FMTRAN/FMSTRAN register is a byte-wide read/write
register that controls some program/erase transition times.
Software must not modify this register while program/erase
operation is in progress (FMBUSY set). At reset, this register is initialized to 30h if the flash memory is idle. The CPU
bus master has read/write access to this register.
7
Flash Memory Module Erase Time Reload
Register 0 (FMMERASE0/FSMMERASE0)
The FMMERASE0/FSMMERASE0 register is a byte-wide
read/write register that controls the module erase pulse
width. Software must not modify this register while a program/erase operation is in progress (FMBUSY set). At reset, this register is initialized to EAh if the flash memory is
idle. The CPU bus master has read/write access to this register.
0
7
FTTRAN
0
FTMER
8.5.11
The Flash TIming Transition Count field specifies a delay of (FTTRAN + 1) prescaler output
clocks.
Flash Memory Programming Time Reload
Register (FMPROG/FSMPROG)
8.5.14
The Flash Timing Module Erase Pulse Width
field specifies a module erase pulse width of
4096 × (FTMER + 1) prescaler output clocks.
Flash Memory End Time Reload Register
(FMEND/FSMEND)
The FMEND/FSMEND register is a byte-wide read/write
register that controls the delay time after a program/erase
operation. Software must not modify this register while a
program/erase operation is in progress (FMBUSY set). At
reset, this register is initialized to 18h when the flash memory on the chip is idle. The CPU bus master has read/write
access to this register.
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The FMPROG/FSMPROG register is a byte-wide read/write
register that controls the programming pulse width. Software must not modify this register while a program/erase
operation is in progress (FMBUSY set). At reset, this register is initialized to 16h if the flash memory is idle. The CPU
bus master has read/write access to this register.
7
FTMER
te
FTTRAN
0
FTPROG
7
0
FTEND
FTPROG
FTEND
The Flash Timing End Delay Count field specifies a delay of (FTEND + 1) prescaler output
clocks.
Flash Memory Page Erase Time Reload
Register (FMPERASE/FSMPERASE)
bs
8.5.12
The Flash Timing Programming Pulse Width
field specifies a programming pulse width of
8 × (FTPROG + 1) prescaler output clocks.
O
The FMPERASE/FSMPERASE register is a byte-wide
read/write register that controls the page erase pulse width.
Software must not modify this register while a program/
erase operation is in progress (FMBUSY set). At reset, this
register is initialized to 04h if the flash memory is idle. The
CPU bus master has read/write access to this register.
7
0
8.5.15
Flash Memory Module Erase End Time Reload
Register (FMMEND/FSMMEND)
The FMMEND/FSMMEND register is a byte-wide read/write
register that controls the delay time after a module erase operation. Software must not modify this register while a program/erase operation is in progress (FMBUSY set). At
reset, this register is initialized to 3Ch if the flash memory is
idle. The CPU bus master has read/write access to this register.
FTPER
FTPER
7
0
FTMEND
The Flash Timing Page Erase Pulse Width
field specifies a page erase pulse width of
4096 × (FTPER + 1) prescaler output clocks.
FTMEND
39
The Flash Timing Module Erase End Delay
Count field specifies a delay of 8 × (FTMEND
+ 1) prescaler output clocks.
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CP3UB17
8.5.10
CP3UB17
8.5.16
8.5.18
Flash Memory Recovery Time Reload Register
(FMRCV/FSMRCV)
The FMAR1 register contains a copy of the Protection Word
from Information Block 1. The Protection Word is sampled
at reset. The contents of the FMAR1 register define the current Flash memory protection settings. The CPU bus master has read-only access to this register. The FSMAR1
register has the same value as the FMAR1 register. The format is the same as the format of the Protection Word (see
Section 8.4.2).
The FMRCV/FSMRCV register is a byte-wide read/write
register that controls the recovery delay time between two
flash memory accesses. Software must not modify this register while a program/erase operation is in progress (FMBUSY set). At reset, this register is initialized to 04h if the
flash memory is idle. The CPU bus master has read/write
access to this register.
7
Flash Memory Auto-Read Register 1 (FMAR1/
FSMAR1)
0
15
FTRCV
13
12
10
9
7
6
4
3
1
0
WRPROT RDPROT ISPE EMPTY BOOTAREA 1
8.5.17
The Flash Timing Recovery Delay Count field
specifies a delay of (FTRCV + 1) prescaler
output clocks.
Flash Memory Auto-Read Register 0 (FMAR0/
FSMAR0)
Flash Memory Auto-Read Register 2 (FMAR2/
FSMAR2)
The FMAR2 register is a word-wide read-only register,
which is loaded during reset. It is used to build the Code
Area start address. At reset, the CPU executes a branch,
using the contents of the FMAR2 register as displacement.
The CPU bus master has read-only access to this register.
The FSMAR2 register has the same value as the FMAR2
register.
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The FMAR0/FSMAR0 register contains a copy of the Function Word from Information Block 0. The Function Word is
sampled at reset. The contents of the FMAR0 register are
used to enable or disable special device functions. The CPU
bus master has read-only access to this register. The
FSMAR0 register has the same value as the FMAR0 register
8.5.19
te
FTRCV
7
0
CADR7:0
15
1
Reserved
0
USB_ENABLE
15
13
CADR15:13
O
bs
USB_ENABLE The USB_ENABLE bit can be used to force
an external USB transceiver into its low-power
mode. The USB power mode is dependent on CADR8:0
the USB controller status, the USB_ENABLE
bit in the MCFG register (see Section 7.1),
and the USB_ENABLE bit in the Function
Word.
CADR12:9
0 – External USB transceiver forced into lowpower mode.
1 – Transceiver power mode dependent on CADR15:13
USB controller status and programming
of the Function Word.
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40
12
9
CADR12:8
8
CADR8
The Code Area Start Address (bits 8:0) contains the lower 9 bits of the Code Area start
address. The CADR8:0 field has a fixed value
of 0.
The Code Area Start Address (bits 12:9) are
loaded during reset with the inverted value of
BOOTAREA3:0.
The Code Area Start Address (bits 15:13)
contains the upper 3 bits of the Code Area
start address. The CADR15:13 field has a
fixed value of 0.
CP3UB17
9.0
DMA Controller
The DMA Controller (DMAC) has a register-based programming interface, as opposed to an interface based on I/O
control blocks. After loading the registers with source and
destination addresses, as well as block size and type of operation, a DMAC channel is ready to respond to DMA transfer requests. A request can only come from on-chip
peripherals or software, not external peripherals. On receiving a DMA transfer request, if the channel is enabled, the
DMAC performs the following operations:
Peripheral
Transaction
Register
0 (Primary)
USB
R/W
RX/TX FIFO
0 (Secondary)
UART
R
RXBUF
1 (Primary)
UART
W
TXBUF
1 (Secondary)
unused
N/A
N/A
2 (Primary)
Audio Interface
R
ARDR0
2 (Secondary)
CVSD/PCM
Transcoder
R
PCMOUT
te
Channel
3 (Primary)
Audio Interface
W
ATDR0
3 (Secondary)
CVSD/PCM
Transcoder
W
PCMIN
9.2
TRANSFER TYPES
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e
1. Arbitrates to become master of the CPU bus.
2. Determines priority among the DMAC channels, one
clock cycle before T1 of the DMAC transfer cycle. (T1
is the first clock cycle of the bus cycle.) Priority among
the DMAC channels is fixed in descending order, with
Channel 0 having the highest priority.
3. Executes data transfer bus cycle(s) selected by the values held in the control registers of the channel being
serviced, and according to the accessed memory address. The DMAC acknowledges the request during the
bus cycle that accesses the requesting device.
4. If the transfer of a block is terminated, the DMAC does
the following:
Updates the termination bits.
Generates an interrupt (if enabled).
Goes to step 6.
5. If DMRQn is still active, and the Bus Policy is “continuous”, returns to step 3.
6. Returns mastership of the CPU bus to the CPU.
Table 19 DMA Channel Assignment
bs
The DMAC uses two data transfer modes, Direct (Flyby)
and Indirect (Memory-to-Memory). The choice of mode depends on the required bus performance and whether direct
mode is available for the transfer. Indirect mode must be
used when the source and destination have differing bus
Each DMAC channel can be programmed for direct (flyby) widths, when both the source and destination are in memoor indirect (memory-to-memory) data transfers. Once a ry, and when the destination does not support direct mode.
DMAC transfer cycle is in progress, the next transfer request
Direct (Flyby) Transfers
is sampled when the DMAC acknowledge is de-asserted, 9.2.1
then on the rising edge of every clock cycle.
In direct mode each data item is transferred using a single
The configuration of either address freeze or address update (increment or decrement) is independent of the number of transferred bytes, transfer direction, or number of
bytes in each DMAC transfer cycle. All these can be configured for each channel by programming the appropriate control registers.
bus cycle, without reading the data into the DMAC. It provides the fastest transfer rate, but it requires identical source
and destination bus widths. The DMAC cannot use Direct
cycles between two memory devices. One of the devices
must be an I/O device that supports the Direct (Flyby) mechanism, as shown in Figure 2.
Each DMAC channel has eight control registers. DMAC
channels are described hereafter with the suffix n, where n
= 0 to 3, representing the channel number in the registernames.
Bus State
O
T1
9.1
T2
Tidle
T1
CLK
CHANNEL ASSIGNMENT
DMRQ[3:0]
Table 19 shows the assignment of the DMA channels to different tasks. Four channels can be shared by a primary and
an secondary function. However, only one source at a time
can be enabled. If a channel is used for memory block transfers, other resources must be disabled.
ADDR
ADCA
DMACK[3:0]
DS005
Figure 2. Direct DMA Cycle Followed by a CPU Cycle
Direct mode supports two bus policies: intermittent and continuous. In intermittent mode, the DMAC gives bus mastership back to the CPU after every cycle. In continuous mode,
the DMAC remains bus master until the transfer is complet-
41
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CP3UB17
ed. The maximum bus throughput in intermittent mode is 9.3
OPERATION MODES
one transfer for every three System Clock cycles. The maxThe DMAC operates in three different block transfer modes:
imum bus throughput in continuous mode is one transfer for
single transfer, double buffer, and auto-initialize.
every clock cycle.
Single Transfer Operation
The I/O device which made the DMA request is called the 9.3.1
implied I/O device. The other device can be either memory
or another I/O device, and is called the addressed device.
This mode provides the simplest way to accomplish a single
block data transfer.
Because only one address is required in direct mode, this
address is taken from the corresponding ADCAn counter.
The DMAC channel generates either a read or a write bus
cycle, as controlled by the DMACNTLn.DIR bit.
Initialization
1. Write the block transfer addresses and byte count into
the corresponding ADCAn, ADCBn, and BLTCn
counters.
2. Clear the DMACNTLn.OT bit to select non-auto-initialize mode. Clear the DMASTAT.VLD bit by writing a 1 to
it.
3. Set the DMACNTLn.CHEN bit to activate the channel
and enable it to respond to DMA transfer requests.
When the DMACNTLn.DIR bit is clear, a read bus cycle
from the addressed device is performed, and the data is
written to the implied I/O device. When the DMACNTLn.DIR
bit is set, a write bus cycle to the addressed device is performed, and the data is read from the implied I/O device.
9.2.2
When the BLTCn counter reaches 0:
1. The transfer operation terminates.
2. The DMASTAT.TC and DMASTAT.OVR bits are set, and
the DMASTAT.CHAC bit is cleared.
3. An interrupt is generated if enabled by the
DMACNTLn.ETC or DMACNTLn.EOVR bits.
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Whether 8 or 16 bits are transferred in each cycle is selected by the DMACNTLn.TCS register bit. After the data item
has been transferred, the BLTCn counter is decremented by
one. The ADCAn counter is updated according to the INCA
and ADA fields in the DMACNTLn register.
Termination
te
The configuration of either address freeze or address update (increment or decrement) is independent of the number of transferred bytes, transfer direction, or number of
bytes in each DMAC transfer cycle. All these can be configured for each channel by programming the appropriate control register.
The DMACNTLn.CHEN bit must be cleared before loading
the DMACNTLn register to avoid prematurely starting a new
DMA transfer.
9.3.2
Indirect (Memory-To-Memory) Transfers
Double Buffer Operation
O
bs
In indirect (memory-to-memory) mode, data transfers use This mode allows software to set up the next block transfer
two consecutive bus cycles. The data is first read into a tem- while the current block transfer proceeds.
porary register, and then written to the destination in the fol- Initialization
lowing cycle. This mode is slower than the direct (flyby) 1. Write the block transfer addresses and byte count into
mode, but it provides support for different source and destithe ADCAn, ADCBn, and BLTCn counters.
nation bus widths. Indirect mode must be used for transfers 2. Clear the DMACNTLn.OT bit to select non-auto-initialbetween memory devices.
ize mode. Clear the DMASTAT.VLD bit by writing a 1 to
it.
If an intermittent bus policy is used, the maximum throughput is one transfer for every five clock cycles. If a continuous 3. Set the DMACNTLn.CHEN bit. This activates the channel and enables it to respond to DMA transfer requests.
bus policy is used, maximum throughput is one transfer for
4. While the current block transfer proceeds, write the adevery two clock cycles.
dresses and byte count for the next block into the
When the DMACNTLn.DIR bit is 0, the first bus cycle reads
ADRAn, ADRBn, and BLTRn registers. The BLTRn regdata from the source using the ADCAn counter, while the
ister must be written last, because it sets the DMASsecond bus cycle writes the data into the destination using
TAT.VLD bit which indicates that all the parameters for
the ADCBn counter. When the DMACNTLn.DIR bit is set,
the next transfer have been updated.
the first bus cycle reads data from the source using the ADCBn counter, while the second bus cycle writes the data into Continuation/Termination
the destination addressed by the ADCAn counter.
When the BLTCn counter reaches 0:
The number of bytes transferred in each cycle is taken from
1. The DMASTAT.TC bit is set.
the DMACNTLn.TCS register bit. After the data item has
2. An interrupt is generated if enabled by the
been transferred, the BLTCn counter is decremented by
DMACNTLn.ETC bit.
one. The ADCAn and ADCBn counters are updated accord3. The DMAC channel checks the value of the VLD bit.
ing to the INCA, INCB, ADA, and ADB fields in the
If the DMASTAT.VLD bit is set:
DMACNTLn register.
1. The channel copies the ADRAn, ADRBn, and BLTRn
values into the ADCAn, ADCBn, and BLTCn registers.
2. The DMASTAT.VLD bit is cleared.
3. The next block transfer is started.
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42
1.
2.
3.
4.
The transfer operation terminates.
The channel sets the DMASTAT.OVR bit.
The DMASTAT.CHAC bit is cleared.
An interrupt is generated if enabled
DMACNTLn.EOVR bit.
by
For each channel, use the software DMA transfer request
only when the corresponding hardware DMA request is inactive and no terminal count interrupt is pending. Software
can poll the DMASTAT.CHAC bit to determine whether the
DMA channel is already active. After verifying the DMASTATn.CHAC bit is clear (channel inactive), check the DMASTATn.TC (terminal count) bit. If the TC bit is clear, then no
terminal count condition exists and therefore no terminal
count interrupt is pending. If the channel is not active and no
terminal count interrupt is pending, software may request a
DMA transfer.
the
The DMACNTLn.CHEN bit must be cleared before loading
the DMACNTLn register to avoid prematurely starting a new
DMA transfer.
Note: The ADCBn and ADRBn registers are used only in
indirect (memory-to-memory) transfer. In direct (flyby)
9.5
DEBUG MODE
mode, the DMAC does not use them and therefore does not
When the FREEZE signal is active, all DMA operations are
copy ADRBn into ADCBn.
stopped. They will start again when the FREEZE signal
9.3.3
Auto-Initialize Operation
goes inactive. This allows breakpoints to be used in debug
This mode allows the DMAC to continuously fill the same systems.
memory area without software intervention.
9.6
DMA CONTROLLER REGISTER SET
O
bs
ol
e
te
Initialization
There are four identical sets of DMA controller registers, as
1. Write the block addresses and byte count into the ADlisted in Table 20.
CAn, ADCBn, and BLTCn counters, as well as the
Table 20 DMA Controller Registers
ADRAn, ADRBn, and BLTRn registers.
2. Set the DMACNTLn.OT bit to select auto-initialize
Name
Address
Description
mode.
3. Set the DMACNTLn.CHEN bit to activate the channel
Device A Address
and enable it to respond to DMA transfer requests.
ADCA0
FF F800h
Counter Register
Continuation
Device A Address
ADRA0
FF F804h
When the BLTCn counter reaches 0:
Register
1. The contents of the ADRAn, ADRBn, and BLTRn regisDevice B Address
ters are copied to the ADCAn, ADCBn, and BLTCn
ADCB0
FF F808h
Counter Register
counters.
2. The DMAC channel checks the value of the DMASDevice B Address
ADRB0
FF F80Ch
TAT.TC bit.
Register
If the DMASTAT.TC bit is set:
Block Length
BLTC0
FF F810h
1. The DMASTAT.OVR bit is set.
Counter Register
2. A level interrupt is generated if enabled by the
BLTR0
FF F814h
Block Length Register
DMACNTLn.EOVR bit.
3. The operation is repeated.
DMACNTL0
FF F81Ch
DMA Control Register
If the DMASTAT.TC bit is clear:
DMASTAT0
FF F81Eh
DMA Status Register
1. The DMASTAT.TC bit is set.
2. A level interrupt is generated if enabled by the
Device A Address
ADCA1
FF F820h
DMACNTLn.ETC bit.
Counter Register
3. The DMAC operation is repeated.
Device A Address
ADRA1
FF F824h
Termination
Register
The
DMA
transfer
is
terminated
when
the
Device B Address
ADCB1
FF F828h
DMACNTLn.CHEN bit is cleared.
Counter Register
9.4
SOFTWARE DMA REQUEST
In addition to the hardware requests from I/O devices, a
DMA transfer request can also be initiated by software. A
software DMA transfer request must be used for block copying between memory devices.
ADRB1
FF F82Ch
Device B Address
Register
BLTC1
FF F830h
Block Length
Counter Register
When the DMACNTLn.SWRQ bit is set, the corresponding
DMA channel receives a DMA transfer request. When the
DMACNTLn.SWRQ bit is clear, the software DMA transfer
request of the corresponding channel is inactive.
BLTR1
FF F834h
Block Length Register
DMACNTL1
FF F83Ch
DMA Control Register
DMASTAT1
FF F83Eh
DMA Status Register
43
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CP3UB17
If the DMASTAT.VLD bit is clear:
CP3UB17
9.6.2
Table 20 DMA Controller Registers
Name
Address
Description
ADCA2
FF F840h
Device A Address
Counter Register
ADRA2
FF F844h
Device A Address
Register
ADCB2
FF F848h
Device B Address
Counter Register
ADRB2
FF F84Ch
Device B Address
Register
Device A Address Register (ADRAn)
The Device A Address register is a 32-bit, read/write register. It holds the 24-bit starting address of either the next
source data block, or the next destination data area, according
to the DIR bit in the DMACNTLn register. The upper 8 bits of
the ADRAn register are reserved and always clear.
31
24
9.6.3
Device B Address Counter Register (ADCBn)
Block Length
Counter Register
BLTR2
FF F854h
Block Length Register
DMACNTL2
FF F85Ch
DMA Control Register
DMASTAT2
FF F85Eh
DMA Status Register
ADCA3
FF F860h
Device A Address
Counter Register
ADRA3
FF F864h
Device A Address
Register
ADCB3
FF F868h
ADRB3
FF F86Ch
Device B Address
Register
BLTC3
FF F870h
Block Length
Counter Register
BLTR3
FF F874h
DMACNTL3
FF F87Ch
DMA Control Register
31
DMASTAT3
FF F87Eh
DMA Status Register
Reserved
te
FF F850h
24
23
0
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31
Reserved
Device B Address
Counter Register
9.6.4
bs
Block Length Register
Device B Address Counter
Device B Address Register (ADRBn)
The Device B Address register is a 32-bit, read/write register. It holds the 24-bit starting address of either the next
source data block or the next destination data area, according to the DIR bit in the CNTLn register. In direct (flyby)
mode, this register is not used. The upper 8 bits of the ADCRBn register are reserved and always clear.
24
23
0
Device B Address
Device A Address Counter Register (ADCAn)
O
The Device A Address Counter register is a 32-bit, read/
write register. It holds the current 24-bit address of either the
source data item or the destination location, depending on
the state of the DIR bit in the CNTLn register. The ADA bit
of DMACNTLn register controls whether to adjust the pointer in the ADCAn register by the step size specified in the
INCA field of DMACNTLn register. The upper 8 bits of the
ADCAn register are reserved and always clear.
31
0
Device A Address
The Device B Address Counter register is a 32-bit, read/
write register. It holds the current 24-bit address of either the
source data item, or the destination location, according to
the DIR bit in the CNTLn register. The ADCBn register is updated after each transfer cycle by INCB field of the
DMACNTLn register according to ADB bit of the
DMACNTLn register. In direct (flyby) mode, this register is
not used. The upper 8 bits of the ADCBn register are reserved and always clear.
BLTC2
9.6.1
23
Reserved
24
Reserved
23
9.6.5
Block Length Counter Register (BLTCn)
The Block Length Counter register is a 16-bit, read/write
register. It holds the current number of DMA transfers to be
executed in the current block. BLTCn is decremented by one
after each transfer cycle. A DMA transfer may consist of 1 or
2 bytes, as selected by the DMACNTLn.TCS bit.
15
0
Block Length Counter
0
Device A Address Counter
Note: 0000h is interpreted as 216-1 transfer cycles.
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44
Block Length Register (BLTRn)
DIR
The Block Length register is a 16-bit, read/write register. It
holds the number of DMA transfers to be performed for the
next block. Writing this register automatically sets the DMASTAT.VLD bit.
15
0
OT
Block Length
Note: 0000h is interpreted as 216-1 transfer cycles.
9.6.7
DMA Control Register (DMACNTLn)
BPC
7
6
5
4
BPC
OT
DIR
IND
TCS EOVR ETC CHEN
15
14
13
12
11
ETC
TCS
IND
9
0
8
INCA
ADA SWRQ
SWRQ
The Channel Enable bit must be set to enable
any DMA operation on this channel. Writing a
1 to this bit starts a new DMA transfer even if
it is currently a 1. If all DMACNTLn.CHEN bits
are clear, the DMA clock is disabled to reduce
power.
0 – Channel disabled.
1 – Channel enabled.
If the Enable Interrupt on Terminal Count bit is
set, it enables an interrupt when the DMASTAT.TC bit is set.
0 – Interrupt disabled.
1 – Interrupt enabled.
If the Enable Interrupt on OVR bit is set, it enables an interrupt when the DMASTAT.OVR
bit is set.
0 – Interrupt disabled.
1 – Interrupt enabled.
The Transfer Cycle Size bit specifies the number of bytes transferred in each DMA transfer
cycle. In direct (fly-by) mode, undefined results occur if the TCS bit is not equal to the addressed memory bus width.
0 – Byte transfers (8 bits per cycle).
1 – Word transfers (16 bits per cycle).
The Direct/Indirect Transfer bit specifies the
transfer type.
0 – Direct transfer (flyby).
1 – Indirect transfer (memory-to-memory).
O
EOVR
ADB
10
1
ol
e
CHEN
INCB
2
bs
Res.
3
te
The DMA Control register n is a word-wide, read/write register that controls the operation of DMA channel n. This register is cleared at reset. Reserved bits must be written with
0.
The Transfer Direction bit specifies the direction of the transfer relative to Device A.
0 – Device A (pointed to by the ADCAn register) is the source. In Fly-By mode a read
transaction is initialized.
1 – Device A (pointed to by the ADCAn register) is the destination. In Fly-By mode a
write transaction is initialized.
The Operation Type bit specifies the operation
mode of the DMA controller.
0 – Single-buffer mode or double-buffer mode
enabled.
1 – Auto-Initialize mode enabled.
The Bus Policy Control bit specifies the bus
policy applied by the DMA controller. The operation mode can be either intermittent (cycle
stealing) or continuous (burst).
0 – Intermittent operation. The DMAC channel relinquishes the bus after each transaction, even if the request is still asserted.
1 – Continuous operation. The DMAC channel n uses the bus continuously as long
as the request is asserted. This mode can
only be used for software DMA requests.
For hardware DMA requests, the BPC bit
must be clear.
The Software DMA Request bit is written with
a 1 to initiate a software DMA request. Writing
a 0 to this bit deactivates the software DMA
request. The SWRQ bit must only be written
when the DMRQ signal for this channel is inactive (DMASTAT.CHAC = 0).
0 – Software DMA request is inactive.
1 – Software DMA request is active.
If the Device A Address Control bit is set, it enables updating the Device A address.
0 – ADCAn address unchanged.
1 – ADCAn address incremented or decremented, according to INCA field of
DMACNTLn register.
The Increment/Decrement ADCAn field specifies the step size for the Device A address increment/decrement.
00 – Increment ADCAn register by 1.
01 – Increment ADCAn register by 2.
10 – Decrement ADCAn register by 1.
11 – Decrement ADCAn register by 2.
If the Device B Address Control bit is set, it enables updating the Device B Address.
0 – ADCBn address unchanged.
1 – ADCBn address incremented or decremented, according to INCB field of
DMACNTLn register.
The Increment/Decrement ADCBn field specifies the step size for the Device B address increment/decrement.
00 – Increment ADCBn register by 1.
01 – Increment ADCBn register by 2.
10 – Decrement ADCBn register by 1.
11 – Decrement ADCBn register by 2.
ADA
INCA
ADB
INCB
45
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CP3UB17
9.6.6
DMA Status Register (DMASTAT)
The DMA status register is a byte-wide, read register that
holds the status information for the DMA channel n. This
register is cleared at reset. The reserved bits always return
zero when read. The VLD, OVR and TC bits are sticky (once
set by the occurrence of the specific condition, they remain
set until explicitly cleared by software). These bits can be individually cleared by writing 1 to the bit positions in the DMASTAT register to be cleared. Writing 0 to these bits has no
effect
7
4
Reserved
TC
2
1
VLD CHAC OVR
0
TC
The Terminal Count bit indicates whether the
transfer was completed by a terminal count
condition (BLTCn Register reached 0).
0 – Terminal count condition did not occur.
1 – Terminal count condition occurred.
The behavior of the Channel Overrun bit depends on the operation mode (single buffer,
double buffer, or auto-initialize) of the DMA
channel.
In double-buffered mode (DMACNTLn.OT =
0):
The OVR bit is set when the present transfer
is completed (BLTCn = 0), but the parameters
for the next transfer (address and block
length) are not valid (DMASTAT.VLD = 0).
In auto-initialize mode (DMACNTLn.OT = 1):
The OVR bit is set when the present transfer
is completed (BLTCn = 0), and the DMASTAT.TC bit is still set.
In single-buffer mode:
Operates in the same way as double-buffer
mode. In single-buffered mode, the DMASTAT.VLD bit should always be clear, so it will
also be set when the DMASTAT.TC bit is set.
Therefore, the OVR bit can be ignored in this
mode.
The Channel Active bit continuously indicates
the active or inactive status of the channel,
and therefore, it is read only. Data written to
the CHAC bit is ignored.
0 – Channel inactive.
1 – Indicates that the channel is active
(CHEN bit in the CNTLn register is 1 and
BLTCn > 0)
The Transfer Parameters Valid bit specifies
whether the transfer parameters for the next
block to be transferred are valid. Writing the
BLTRn register automatically sets this bit. The
bit is cleared in the following cases:
• The present transfer is completed and the
ADRAn, ADRBn (indirect mode only), and
BLTR registers are copied to the ADCAn,
ADCBn (indirect mode only), and BLTCn
registers.
• Writing 1 to the VLD bit.
O
CHAC
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OVR
3
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CP3UB17
9.6.8
VLD
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46
The Interrupt Control Unit (ICU) receives interrupt requests
from internal and external sources and generates interrupts
to the CPU. Interrupts from the timers, UARTs, Microwire/
SPI interface, and Multi-Input Wake-Up are all maskable interrupts. The highest-priority interrupt is the Non-Maskable
Interrupt (NMI), which is triggered by a falling edge received
on the NMI input pin.
knowledge bus cycle on receiving a maskable interrupt request from the ICU. During the interrupt acknowledge cycle,
a byte is read from address FF FE00h (IVCT register). The
byte is used as an index into the Dispatch Table to determine the address of the interrupt handler.
Because IRQ0 is not connected to any interrupt source, it
would seem that the interrupt vector would never return the
value 10h. If it does return a value of 10h, the entry in the
dispatch table should point to a default interrupt handler that
handles this error condition. One possible condition for this
to occur is deassertion of the interrupt before the interrupt
acknowledge cycle.
The priorities of the maskable interrupts are hardwired and
therefore fixed. The interrupts are named IRQ0 through
IRQ31, in which IRQ0 has the lowest priority and IRQ31 has
the highest priority.
NON-MASKABLE INTERRUPTS
The Interrupt Control Unit (ICU) receives the external NMI
input and generates the NMI signal driven to the CPU. The
NMI input is an asynchronous input with Schmitt trigger
characteristics and an internal synchronization circuit,
therefore no external synchronizing circuit is needed. The
NMI pin triggers an exception on its falling edge.
10.1.1
Non-Maskable Interrupt Processing
INTERRUPT CONTROLLER REGISTERS
Table 21 lists the ICU registers.
Table 21 Interrupt Controller Registers
Name
Address
Description
NMISTAT
FF FE02h
Non-Maskable Interrupt Status Register
EXNMI
FF FE04h
External NMI Trap
Control and Status
Register
IVCT
FF FE00h
Interrupt Vector
Register
IENAM0
FF FE0Eh
Interrupt Enable and
Mask Register 0
IENAM1
FF FE10h
Interrupt Enable and
Mask Register 1
ISTAT0
FF FE0Ah
Interrupt Status
Register 0
ISTAT1
FF FE0Ch
Interrupt Status
Register 1
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The CPU performs an interrupt acknowledge bus cycle
when beginning to process a non-maskable interrupt. The
address associated with this core bus cycle is within the internal core address space and may be monitored as a Core
Bus Monitoring (CBM) clock cycle.
10.3
te
10.1
10.2
bs
At reset, NMI interrupts are disabled and must remain disabled until software initializes the interrupt table, interrupt
base register (INTBASE), and the interrupt mode. The external NMI interrupt is enabled by setting the EXNMI.ENLCK bit and will remain enabled until a reset occurs.
Alternatively, the external NMI interrupt can be enabled by
setting the EXNMI.EN bit and will remain enabled until an interrupt event or a reset occurs.
MASKABLE INTERRUPTS
The ICU receives level-triggered interrupt request signals
from 31 internal sources and generates a vectored interrupt
to the CPU when required. Priority among the interrupt
sources (named IRQ1 through IRQ31) is fixed.
O
The maskable interrupts are globally enabled and disabled
by the E bit in the PSR register. The EI and DI instructions
are used to set (enable) and clear (disable) this bit. The global maskable interrupt enable bit (I bit in the PSR) must also
be set before any maskable interrupts are taken.
Each interrupt source can be individually enabled or disabled under software control through the ICU interrupt enable registers and also through interrupt enable bits in the
peripherals that request the interrupts. The CR16C core
supports IRQ0, but in the CP3UB17 it is not connected to
any interrupt source.
10.3.1
Non-Maskable Interrupt Status Register
(NMISTAT)
The NMISTAT register is a byte-wide read-only register. It
holds the status of the current pending Non-Maskable Interrupt (NMI) requests. On the CP3UB17, the external NMI input is the only source of NMI interrupts. The NMISTAT
register is cleared on reset and each time its contents are
read.
7
Maskable Interrupt Processing
Interrupt vector numbers are always positive, in the range EXT
10h to 2Fh. The IVCT register contains the interrupt vector
of the enabled and pending interrupt with the highest priority. The interrupt vector 10h corresponds to IRQ0 and the
lowest priority, while the vector 2Fh corresponds to IRQ31
and the highest priority. The CPU performs an interrupt ac-
1
Reserved
0
EXT
10.2.1
47
The External NMI request bit indicates whether an external non-maskable interrupt request
has occurred. Refer to the description of the
EXNMI register below for additional details.
0 – No external NMI request.
1 – External NMI request has occurred.
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CP3UB17
10.0 Interrupts
10.3.3
External NMI Trap Control and Status Register
(EXNMI)
The IVCT register is a byte-wide read-only register which reports the encoded value of the highest priority maskable interrupt that is both asserted and enabled. The valid range is
from 10h to 2Fh. The register is read by the CPU during an
interrupt acknowledge bus cycle, and INTVECT is valid during that time. It may contain invalid data while INTVECT is
updated.
The EXNMI register is a byte-wide read/write register. It indicates the current value of the NMI pin and controls the
NMI interrupt trap generation based on a falling edge of the
NMI pin. TST, EN and ENLCK are cleared on reset. When
writing to this register, all reserved bits must be written with
0 for the device to function properly
7
3
Reserved
0
7
6
ENLCK
PIN
EN
0
0
The EXNMI trap enable bit is one of two bits
that can be used to enable NMI interrupts.
The bit is cleared by hardware at reset and
whenever the NMI interrupt occurs (EXNMI.EXT set). It is intended for applications
where the NMI input toggles frequently but
nested NMI traps are not desired. For these
applications, the EN bit needs to be re-enabled before exiting the trap handler. When
used this way, the ENLCK bit should never be
set. The EN bit can be set and cleared by software (software can set this bit only if EXNMI.EXT is cleared), and should only be set
after the interrupt base register and the interrupt stack pointer have been set up.
0 – NMI interrupts not enabled by this bit (but
may be enabled by the ENLCK bit).
1 – NMI interrupts enabled.
The PIN bit indicates the state (non-inverted)
on the NMI input pin. This bit is read-only, data
written into it is ignored.
0 – NMI pin not asserted.
1 – NMI pin asserted.
The EXNMI trap enable lock bit is used to permanently enable NMI interrupts. Only a device reset can clear the ENLCK bit. This
allows the external NMI feature to be enabled
after the interrupt base register and the interrupt stack pointer have been set up. When the
ENLCK bit is set, the EN bit is ignored.
0 – NMI interrupts not enabled by this bit (but
may be enabled by the EN bit).
1 – NMI interrupts enabled.
INTVECT
10.3.4
O
ENLCK
1
5
0
INTVECT
The Interrupt Vector field indicates the highest
priority interrupt which is both asserted and
enabled.
Interrupt Enable and Mask Register 0 (IENAM0)
The IENAM0 register is a word-wide read/write register
which holds bits that individually enable and disable the
maskable interrupt sources IRQ1 through IRQ15. The register is initialized to FFFFh upon reset.
15
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PIN
2
bs
EN
Interrupt Vector Register (IVCT)
te
CP3UB17
10.3.2
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IENA
IENA
10.3.5
0
Res.
Each Interrupt Enable bit enables or disables
the corresponding interrupt request IRQ1
through IRQ15, for example IENA15 controls
IRQ15. Because IRQ0 is not used, IENA0 is
ignored.
0 – Interrupt is disabled.
1 – Interrupt is enabled.
Interrupt Enable and Mask Register 1 (IENAM1)
The IENAM1 register is a word-wide read/write register
which holds bits that individually enable and disable the
maskable interrupt sources IRQ16 through IRQ31. The register is initialized to FFFFh at reset.
15
0
IENA
IENA
48
1
Each Interrupt Enable bit enables or disables
the corresponding interrupt request IRQ16
through IRQ31, for example IENA15 controls
IRQ31.
0 – Interrupt is disabled.
1 – Interrupt is enabled.
10.4
Interrupt Status Register 0 (ISTAT0)
The ISTAT0 register is a word-wide read-only register. It indicates which maskable interrupt inputs to the ICU are active. These bits are not affected by the state of the
corresponding IENA bits.
15
1
IST
10.3.7
Table 22 Maskable Interrupts Assignment
IRQ Number
0
Res.
The Interrupt Status bits indicate if a
maskable interrupt source is signalling an interrupt request. IST[15:1] correspond to
IRQ15 to IRQ1 respectively. Because the
IRQ0 interrupt is not used, bit 0 always reads
back 0.
0 – Interrupt is not active.
1 – Interrupt is active.
Interrupt Status Register 1 (ISTAT1)
0
IST
The Interrupt Status bits indicate if a
maskable interrupt source is signalling an interrupt request. IST[31:16] correspond to
IRQ31 to IRQ16, respectively.
0 – Interrupt is not active.
1 – Interrupt is active.
O
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IST
Details
IRQ31
TWM (Timer 0)
IRQ30
Reserved
IRQ29
Reserved
IRQ28
Reserved
IRQ27
Reserved
IRQ26
Reserved
IRQ25
Reserved
IRQ24
USB Interface
IRQ23
DMA Channel 0
IRQ22
DMA Channel 1
IRQ21
DMA Channel 2
IRQ20
DMA Channel 3
IRQ19
Reserved
IRQ18
Advanced Audio Interface
IRQ17
UART Rx
IRQ16
CVSD/PCM Converter
IRQ15
ACCESS.bus Interface
IRQ14
TA (Timer input A)
IRQ13
TB (Timer input B)
IRQ12
VTUA (VTU Interrupt Request 1)
IRQ11
VTUB (VTU Interrupt Request 2)
IRQ10
VTUC (VTU Interrupt Request 3)
IRQ9
VTUD (VTU Interrupt Request 4)
IRQ8
Microwire/SPI Rx/Tx
IRQ7
UART Tx
IRQ6
UART CTS
IRQ5
MIWU Interrupt 0
IRQ4
MIWU Interrupt 1
IRQ3
MIWU Interrupt 2
IRQ2
MIWU Interrupt 3
IRQ1
Flash Program/Data Memory
IRQ0
Reserved
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The ISTAT1 register is a word-wide read-only register. It indicates which maskable interrupt inputs into the ICU are active. These bits are not affected by the state of the
corresponding IENA bits.
15
Table 22 shows the interrupts assigned to various on-chip
maskable interrupts. The priority of simultaneous maskable
interrupts is linear, with IRQ31 having the highest priority.
te
IST
MASKABLE INTERRUPT SOURCES
49
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CP3UB17
10.3.6
CP3UB17
All reserved or unused interrupt vectors should point to a
default or error interrupt handlers.
10.5
NESTED INTERRUPTS
Nested NMI interrupts are always enabled. Nested
maskable interrupts are disabled by default, however an interrupt handler can allow nested maskable interrupts by setting the I bit in the PSR. The LPR instruction is used to set
the I bit.
Nesting of specific maskable interrupts can be allowed by
disabling interrupts from sources for which nesting is not allowed, before setting the I bit. Individual maskable interrupt
sources can be disabled using the IENAM0 and IENAM1
registers.
O
bs
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te
Any number of levels of nested interrupts are allowed, limited only by the available memory for the interrupt stack.
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50
The Triple Clock and Reset module generates a 12 MHz
Main Clock and a 32.768 kHz Slow Clock from external
crystal networks or external clock sources. It provides various clock signals for the rest of the chip. It also provides the
main system reset signal, a power-on reset function, Main
Clock prescalers to generate two additional low-speed
clocks, and a 32-kHz oscillator start-up delay.
Figure 3 is block diagram of the Triple Clock and Reset module.
TWM (Invalid Watchdog Service)
Device Reset
Flash Interface (Program/Erase Busy)
Reset
Module
External Reset
Stretched
Reset
Reset
Power-On-Reset
Module (POR)
Stop Main Osc.
Stop Main Osc
te
Preset
X1CKI
Start-Up-Delay
14-Bit Timer
High Frequency
Oscillator
4-Bit Aux1
Prescaler
Auxiliary Clock 1
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X1CKO
Good Main Clock
4-Bit Aux2
Prescaler
Div.
by 2
8-Bit
Prescaler
Slow Clock Prescaler
X2CKI
Mux
Main Clock
Auxiliary Clock 2
Low Frequency
Oscillator
Slow Clock
Slow Clock
Select
Start-Up-Delay
8-Bit Timer
Time-out
Good Slow Clock
Bypass
32 kHz Osc
Fast Clock
Prescaler
4-Bit
Prescaler
System Clock
Fast Clock
Select
Mux
O
Stop Slow Osc
Mux
bs
Preset
X2CKO
PLL Clock
PLL
(x3, x4, or x5)
Bypass PLL
Good PLL Clock
Stop PLL
Stop PLL
DS006
Figure 3. Triple Clock and Reset Module
51
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CP3UB17
11.0 Triple Clock and Reset
CP3UB17
11.1
EXTERNAL CRYSTAL NETWORK
crystal network and Table 24 shows the component specifications for the 32.768 kHz crystal network.
An external crystal network is connected to the X1CKI and
X1CKO pins to generate the Main Clock, unless an external
clock signal is driven on the X1CKI pin. A similar external
crystal network may be used at pins X2CKI and X2CKO for
the Slow Clock. If an external crystal network is not used for
the Slow Clock, the Slow Clock is generated by dividing the
fast Main Clock.
X1CKI/X2CKI
C1
The crystal network you choose may require external components different from the ones specified in this datasheet.
In this case, consult with National’s engineers for the component specifications
12 MHz/32.768 kHz
Crystal
X1CKO/X2CKO
The crystals and other oscillator components must be
placed close to the X1CKI/X1CKO and X2CKI/X2CKO device input pins to keep the printed trace lengths to an absolute minimum.
GND
te
Figure 4 shows the required crystal network at X1CKI/
X1CKO and optional crystal network at X2CKI/X2CKO.
Table 23 shows the component specifications for the main
C2
DS007
Figure 4. External Crystal Network
Component
Crystal
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Table 23 Component Values of the High Frequency Crystal Circuit
Parameters
Resonance Frequency
Type
Max. Serial Resistance
Max. Shunt Capacitance
Load Capacitance
Capacitance
bs
Capacitor C1, C2
Values
Tolerance
12 MHz ± 20 ppm
AT-Cut
50 Ω
7 pF
22 pF
N/A
22 pF
20%
Table 24 Component Values of the Low Frequency Crystal Circuit
Component
Crystal
Parameters
Resonance Frequency
O
Type
Maximum Serial Resistance
Maximum Shunt Capacitance
Load Capacitance
Min. Q factor
Capacitor C1, C2
Tolerance
32.768 kHz
Parallel
N-Cut or XY-bar
40 kΩ
2 pF
12.5 pF
40000
N/A
25 pF
20%
Capacitance
Choose capacitor component values in the tables to obtain
the specified load capacitance for the crystal when combined with the parasitic capacitance of the trace, socket, and
package (which can vary from 0 to 8 pF). As a guideline, the
load capacitance is:
C1 × C2- + Cparasitic
CL = -------------------C1 + C2
C2 > C1
C1 can be trimmed to obtain the desired load capacitance.
The start-up time of the 32.768 kHz oscillator can vary from
one to six seconds. The long start-up time is due to the high
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Values
52
Q value and high serial resistance of the crystal necessary
to minimize power consumption in Power Save mode.
11.2
MAIN CLOCK
The Main Clock is generated by the 12-MHz high-frequency
oscillator or driven by an external signal. It can be stopped
by the Power Management Module to reduce power consumption during periods of reduced activity. When the Main
Clock is restarted, a 14-bit timer generates a Good Main
Clock signal after a start-up delay of 32,768 clock cycles.
This signal is an indicator that the high-frequency oscillator
is stable.
The PRSFC register must not be modified while the System
Clock is derived from the PLL Clock. The System Clock
must be derived from the low-frequency oscillator clock
while the MODE field is modified.
11.5
SYSTEM CLOCK
When the timer reaches zero, it stops counting and asserts
the Good Slow Clock signal, which indicates that the Slow
Clock is stable.
11.7
POWER-ON RESET
The CP3UB17 has specific Power On Reset (POR) timing
requirements that must be met to prevent corruption of the
on-chip flash program and data memories. This timing sequence shown in Figure 5.
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For systems that do not require a reduced power consumption mode, the external crystal network may be omitted for
the Slow Clock. In that case, the Slow Clock can be synthesized by dividing the Main Clock by a prescaler factor. The
prescaler circuit consists of a fixed divide-by-2 counter and
a programmable 8-bit prescaler register. This allows a
choice of clock divisors ranging from 2 to 512. The resulting
Slow Clock frequency must not exceed 100 kHz.
te
The System Clock drives most of the on-chip modules, including the CPU. Typically, it is driven by the Main Clock, but
it can also be driven by the PLL. In either case, the clock sig11.3
SLOW CLOCK
nal is passed through a programmable divider (scale factors
The Slow Clock is necessary for operating the device in re- from ÷1 to ÷16).
duced power modes and to provide a clock source for mod11.6
AUXILIARY CLOCKS
ules such as the Timing and Watchdog Module.
The Slow Clock operates in a manner similar to the Main Auxiliary Clock 1 and Auxiliary Clock 2 are generated from
Clock. The Stop Slow Osc signal from the Power Manage- Main Clock for use by certain peripherals. Auxiliary Clock 1
ment Module stops and starts the low-frequency (32.768 is available for the Advanced Audio Interface. Auxiliary
kHz) oscillator. When this signal is asserted, it presets a 6- Clock 2 is available for the CVSD/PCM transcoder. The Auxbit timer to 3Fh and disables the low-frequency oscillator. iliary clocks may be configured to keep these peripherals
When the signal goes inactive, the low-frequency oscillator running when the System Clock is slowed down or suspendstarts, and the 6-bit timer counts down from its preset value. ed during low-power modes.
All reset circuits must ensure that this timing sequence is always maintained during power-up and power-down. The
design of the power supply also affects how this sequence
is implemented.
The power-up sequence is:
1. The RESET pin must be held low until both IOVCC and
VCC have reached the minimum levels specified in the
DC Characteristics section. IOVCC and VCC are allowed to reach their nominal levels at the same time
which is the best-case scenario.
2. After both of these supply voltage rails have met this
condition, then the RESET pin may be driven high. At
power-up an internal 14-bit counter is set to 3FFFh and
begins counting down to 0 after the crystal oscillator
becomes stable. When this counter reaches 0, the onchip RESET signal is driven high unless the external
RESET pin is still being held low. This prevents the
CP3UB17 from coming out of reset with an unstable
clock source.
O
bs
A software-programmable multiplexer selects either the
prescaled Main Clock or the 32.768 kHz oscillator as the
Slow Clock. At reset, the prescaled Main Clock is selected,
ensuring that the Slow Clock is always present initially. Selection of the 32.768 kHz oscillator as the Slow Clock disables the clock prescaler, which allows the CLK1 oscillator
to be turned off, which reduces power consumption and radiated emissions. This can be done only if the module detects a toggling low-speed oscillator. If the low-speed
oscillator is not operating, the prescaler remains available
as the Slow Clock source.
11.4
PLL CLOCK
The PLL Clock is generated by the PLL from the 12 MHz
Main Clock by applying a multiplication factor of ×3, ×4, or The power-down sequence is:
×5. The USB interface is clocked directly by the PLL Clock
and requires a 48 MHz clock, so a ×4 scaling factor must be 1. The RESET pin must be driven low as soon as either
the IOVCC or VCC voltage rail reaches the minimum
used if the USB interface is active.
levels specified in the DC Characteristics.
To enable the PLL:
2. The RESET pin must then be held low until the Main
Clock is stopped. The Main Clock will decay with the
1. Set the PLL multiplication factor in PRFSC.MODE.
same profile as IOVCC.
2. Clear the PLL power-down bit CRCTRL.PLLPWD.
3. Clear the high-frequency clock select bit CRCTRL.FCLK.
4. Read CRCTRL.FCLK, and go back to step 3 if not clear.
The CRCTRL.FCLK bit will be clear only after the PLL has
stabilized, so software must repeat step 3 until the bit is
clear. The clock source can be switched back to the Main
Clock by setting the CRCTRL.FCLK bit.
Meeting the power-down reset conditions ensures that software will not be executed at voltage levels that may cause
incorrect program execution or corruption of the flash memories. This situation must be avoided because the Main
Clock decays with the IOVCC supply rather than stopping
immediately when IOVCC falls below the minimum specified
level.
53
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CP3UB17
The Stop Main Osc signal from the Power Management
Module stops and starts the high-frequency oscillator.
When this signal is asserted, it presets the 14-bit timer to
3FFFh and stops the high-frequency oscillator. When the
signal goes inactive, the high-frequency oscillator starts and
the 14-bit timer counts down from its preset value. When the
timer reaches zero, it stops counting and asserts the Good
Main Clock signal.
CP3UB17
The external reset circuits presented in the following sections provide varying levels of additional fault tolerance and
expandability and are presented as possible examples of
solutions to be used with the CP3UB17. It is important to
note, however, that any design for the reset circuit and power supply must meet the timing requirements shown in
Figure 5.
11.7.2
Manual and SDI External Reset
An external reset circuit based on the LM3724 5-Pin Microprocessor Reset Circuit is shown in Figure 7. The LM3724
produces a 190-ms logic low reset pulse when the power
supply rises above a threshold voltage or a manual reset
button is pressed. Various reset thresholds are available for
the LM3724, however the option for 3.08V is most suitable
for a CP3UB17 device operating from an IOVCC at 3.3V.
2.25V
IOVCC
IOVCC
IOVCC
2.25V
Core VCC
10k Ω
LM3724
5-Pin Reset
Circuit
RESET
RESET
Manual
Reset
Main
Clock
te
GND
Power Up
Power Down
DS515
Figure 5.
SDI Reset
Power-On Reset Timing
bs
A simple external reset circuit with brown-out and glitch protection based on the LM809 3-Pin Microprocessor Reset
Circuit is shown in Figure 6. The LM809 produces a 240-ms
logic low reset pulse when the power supply rises above a
threshold voltage. Various reset thresholds are available for
the LM809, however the options for 2.93V and 3.08V are
most suitable for a CP3UB17 device operating from an IOVCC at 3.0V to 3.3V.
IOVCC
IOVCC
CP3xx17
RESET
O
LM809
3-Pin Reset
Circuit
GND
DS512
Figure 6. Simple External Reset
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DS513
Figure 7. Manual and SDI External Reset
Simple External Reset
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11.7.1
CP3xx17
54
The LM3724 provides a debounced input for a manual
pushbutton reset switch. It also has an open-drain output
which can be used for implementing a wire-OR connection
with a reset signal from a serial debug interface. This circuit
is typical of a design to be used in a development or evaluation environment, however it is a good recommendation for
all general CP3UB17 designs. If an SDI interface is not implemented, an LM3722 with active pullup may be used.
11.8
Fault-Tolerant External Reset
CLOCK AND RESET REGISTERS
An external reset circuit based on the LM3710 Microproces- Table 25 lists the clock and reset registers.
sor Supervisory Circuit is shown in Figure 8. It provides a
Table 25 Clock and Reset Registers
high level of fault tolerance in that it provides the ability to
monitor both the VCC supply for the core logic and the IOName
Address
Description
VCC supply. It also provides a low-voltage indication for the
IOVCC supply and an external watchdog timer.
Clock and Reset
CRCTRL
FF FC40h
Control Register
IOVCC
PRSFC
FF FC42h
High Frequency Clock
Prescaler Register
PRSSC
FF FC44h
Low Frequency Clock
Prescaler Register
PRSAC
FF FC46h
Auxiliary Clock
Prescaler Register
IOVCC
10k Ω
LM3724
5-Pin Reset
Circuit
CP3xx17
RESET
Manual
Reset
11.8.1
SDI Reset
Clock and Reset Control Register (CRCTRL)
te
GND
The CRCTRL register is a byte-wide read/write register that
controls the clock selection and contains the power-on reset
status bit. At reset, the CRCTRL register is initialized as described below:
DS513
Figure 8. Fault-Tolerant External Reset
6
5
4
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7
Reserved
The signals shown in Figure 8 are:
O
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Core VCC—the 2.5V power supply rail for the core logic.
IOVCC—the 2.5–3.3V power supply rail for the I/O logic.
SCLK
Watchdog Input (WDI)—this signal is asserted by the
CP3UB17 at regular intervals to indicate normal operation. A general-purpose I/O (GPIO) port may be used to
provide this signal. If the internal watchdog timer in the
CP3UB17 is used, then the LM3704 Microprocessor Supervisory Circuit can provide the same features as the
FCLK
LM3710 but without the watchdog timer.
RESET—an active-low reset signal to the CP3UB17.
The LM3710 is available in versions with active pullup or
an open-drain RESET output.
Power-Fail Input (PFI)—this is a voltage level derived
from the Core VCC power supply rail through a simple
resistor divider network.
Power-Fail Output (PFO)—this signal is asserted when
the voltage on PFI falls below 1.225V. PFO is connected
to the non-maskable interrupt (NMI) input on the
CP3UB17. A system shutdown routine can then be invoked by the NMI handler.
Low Line Output (LLO)—this signal is asserted when the
PLLPWD
main IOVCC level fails below a warning threshold voltage
but remains above a reset detection threshold. This signal may be routed to the NMI input on the CP3UB17 or
to a separate interrupt input.
These additional status and feedback mechanisms allow
the CP3UB17 to recover from software hangs or perform
system shutdown functions before being placed into reset.
The standard reset threshold for the LM3710 is 3.08V with
other options for different watchdog timeout and reset timeouts. The selection of these values are much more application-specific. The combination of a watchdog timeout period
of 1600 ms and a reset period of 200 ms is a reasonable
starting point.
55
3
2
1
0
POR ACE2 ACE1 PLLPWD FCLK SCLK
The Slow Clock Select bit controls the clock
source used for the Slow Clock.
0 – Slow Clock driven by prescaled Main
Clock.
1 – Slow Clock driven by 32.768 kHz oscillator.
The Fast Clock Select bit selects between the
12 MHz Main Clock and the PLL as the source
used for the System Clock. After reset, the
Main Clock is selected. Attempting to switch to
the PLL while the PLLPWD bit is set (PLL is
turned off) is ignored. Attempting to switch to
the PLL also has no effect if the PLL output
clock has not stabilized.
0 – The System Clock prescaler is driven by
the output of the PLL.
1 – The System Clock prescaler is driven by
the 12-MHz Main Clock. This is the default after reset.
The PLL Power-Down bit controls whether the
PLL is active or powered down (Stop PLL signal asserted). When this bit is set, the on-chip
PLL stays powered-down. Otherwise it is powered-up or it can be controlled by the Power
Management Module, respectively. Before
software can power-down the PLL in Active
mode by setting the PLLPWD bit, the FCLK bit
must be set. Attempting to set the PLLPWD
bit while the FCLK bit is clear is ignored. The
FCLK bit cannot be cleared until the PLL clock
has stabilized. After reset this bit is set.
0 – PLL is active.
1 – PLL is powered down.
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CP3UB17
11.7.3
When the Auxiliary Clock Enable bit is set and
a stable Main Clock is provided, the Auxiliary
Clock 1 prescaler is enabled and generates
the first Auxiliary Clock. When the ACE1 bit is
clear or the Main Clock is not stable, Auxiliary
Clock 1 is stopped. After reset this bit is clear.
0 – Auxiliary Clock 1 is stopped.
1 – Auxiliary Clock 1 is active if the Main
Clock is stable.
When the Auxiliary Clock Enable 2 bit is set
and a stable Main Clock is provided, the Auxiliary Clock 2 prescaler is enabled and generates Auxiliary Clock 2. When the ACE2 bit is
clear or the Main Clock is not stable, the Auxiliary Clock 2 is stopped. Auxiliary Clock 2 is
used as the clock input for the CVSD/PCM
transcoder. After reset this bit is clear.
0 – Auxiliary Clock 2 is stopped.
1 – Auxiliary Clock 2 is active if the Main
Clock is stable.
Power-On-Reset - The Power-On-Reset bit is
set when a power-turn-on condition has been
detected. This bit can only be cleared by software, not set. Writing a 1 to this bit will be ignored, and the previous value of the bit will be
unchanged.
0 – Software cleared this bit.
1 – Software has not cleared his bit since the
last reset.
ACE2
11.8.2
MODE
Reserved
Reserved
001
Reserved
Reserved
010
Reserved
Reserved
011
36 MHz
3× Mode
100
48 MHz
4× Mode
101
60 MHz
5× Mode
110
Reserved
Reserved
11.8.3
Reserved
Reserved
Low Frequency Clock Prescaler Register
(PRSSC)
The PRSSC register is a byte-wide read/write register that
holds the clock divisor used to generate the Slow Clock from
the Main Clock. The register is initialized to B6h at reset.
7
6
4
MODE
3
0
FCDIV
The Fast Clock Divisor specifies the divisor
used to obtain the high-frequency System
Clock from the PLL or Main Clock. The divisor
is (FCDIV + 1).
The PLL MODE field specifies the operation
mode of the on-chip PLL. After reset the
MODE bits are initialized to 100b, so the PLL
is configured to generate a 48-MHz clock.
This register must not be modified when the
System Clock is derived from the PLL Clock.
The System Clock must be derived from the
11.8.4
Auxiliary Clock Prescaler Register (PRSAC)
7
4
ACDIV2
ACDIV2
56
The Slow Clock Divisor field specifies a divisor to be used when generating the Slow
Clock from the Main Clock. The Main Clock is
divided by a value of (2 × (SCDIV + 1)) to obtain the Slow Clock. At reset, the SCDIV register is initialized to B6h, which generates a
Slow Clock rate of 32786.89 Hz. This is about
0.5% faster than a Slow Clock generated from
an external 32768 Hz crystal network.
The PRSAC register is a byte-wide read/write register that
holds the clock divisor values for prescalers used to generate the two auxiliary clocks from the Main Clock. The register is initialized to FFh at reset.
ACDIV1
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0
SCDIV
O
FCDIV
000
111
High Frequency Clock Prescaler Register
(PRSFC)
bs
7
Description
MODE2:0
The PRSFC register is a byte-wide read/write register that
holds the 4-bit clock divisor used to generate the high-fre- SCDIV
quency clock. In addition, the upper three bits are used to
control the operation of the PLL. The register is initialized to
4Fh at reset (except in PROG mode.)
Res
Output
Frequency
(from 12 MHz
input clock)
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POR
low-frequency oscillator clock while the
MODE field is modified.
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CP3UB17
ACE1
3
0
ACDIV2
The Auxiliary Clock Divisor 1 field specifies
the divisor to be used for generating Auxiliary
Clock 1 from the Main Clock. The Main Clock
is divided by a value of (ACDIV1 + 1).
The Auxiliary Clock Divisor 2 field specifies
the divisor to be used for generating Auxiliary
Clock 2 from the Main Clock. The Main Clock
is divided by a value of (ACDIV2 + 1).
The Power Management Module (PMM) improves the efficiency of the CP3UB17 by changing the operating mode
(and therefore the power consumption) according to the required level of device activity. The device implements four
power modes:
In Power Save mode, Slow Clock is used as the System
Clock which drives the CPU and most on-chip modules. If
Slow Clock is driven by the 32.768 kHz oscillator and no onchip module currently requires the 12-MHz Main Clock, software can disable the high-frequency oscillator to further reduce power consumption. Auxiliary Clocks 1 and 2 can be
turned off under software control before switching to a reduced power mode, or they may remain active as long as
Main Clock is also active. If the system does not require the
PLL output clock, the PLL can be disabled. Alternatively, the
Main Clock and the PLL can also be controlled by the Hardware Clock Control function, if enabled. The clock architecture is described in Section 11.0.
Active
Power Save
Idle
Halt
Table 26 summarizes the differences between power
modes: the state of the high-frequency oscillator (on or off),
the System Clock source (clock used by most modules),
and the clock source used by the Timing and Watchdog
Module (TWM). The high-frequency oscillator generates the
12-MHz Main Clock, and the low-frequency oscillator generates a 32.768 kHz clock. The Slow Clock can be driven by
the 32.768 kHz clock or a scaled version of the Main Clock.
Table 26 Power Mode Operating Summary
Mode
On
Power Save On or Off
Idle
Off
Halt
Off
System
Clock
It is recommended to keep CPU activity at a minimum by executing the WAIT instruction to guarantee low power consumption in the system.
TWM Clock
Main Clock Slow Clock
Slow Clock
Slow Clock
12.3
None
Slow Clock
None
None
In Idle mode, the System Clock is disabled and therefore the
clock is stopped to most modules of the device. The DHC
and DMC bits in the PMMCR register must be set before entering this mode to disable the PLL and the high-frequency
oscillator. The low-frequency oscillator remains active. The
Power Management Module (PMM) and the Timing and
Watchdog Module (TWM) continue to operate off the Slow
Clock. Idle mode can only be entered from Active mode.
bs
The low-frequency oscillator continues to operate in all four
modes and power must be provided continuously to the device power supply pins. In Halt mode, however, Slow Clock
does not toggle, and as a result, the TWM timer and Watchdog Module do not operate. In Power Save mode, the highfrequency oscillator can be turned on or off under software
control, as long as the low-frequency oscillator is used to
drive Slow Clock.
12.1
In Power Save mode, some modules are disabled or their
operation is restricted. Other modules, including the CPU,
continue to function normally, but operate at a reduced clock
rate. Details of each module’s activity in Power Save mode
are described in each module’s descriptions.
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Active
High-Frequency
Oscillator
POWER SAVE MODE
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12.2
ACTIVE MODE
O
In Active mode, the high-frequency oscillator is active and
generates the 12-MHz Main Clock. The 32.768 kHz oscillator is active and may be used to generate the Slow Clock.
The PLL can be active or inactive, as required. Most on-chip
modules are driven by the System Clock. The System Clock
can be the PLL Clock after a programmable divider or the
12-MHz Main Clock. The activity of peripheral modules is
controlled by their enable bits.
12.4
IDLE MODE
HALT MODE
In Halt mode, all the device clocks, including the System
Clock, Main Clock, and Slow Clock, are disabled. The DHC
and DMC bits in the PMMCR register must be set before entering this mode. The high-frequency oscillator and PLL are
off. The low-frequency oscillator continues to operate, however its circuitry is optimized to guarantee lowest possible
power consumption. This mode allows the device to reach
the absolute minimum power consumption without losing its
state (memory, registers, etc.). Halt mode can only be entered from Active mode.
Power consumption can be reduced in this mode by selectively disabling modules and by executing the WAIT instruction. When the WAIT instruction is executed, the CPU stops
executing new instructions until it receives an interrupt signal. After reset, the CP3UB17 is in Active Mode.
57
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CP3UB17
12.0 Power Management
CP3UB17
12.5
CLOCK CONTROL
IDLE
Altogether, two mechanisms control whether the high-frequency oscillator is active, and three mechanisms control
whether the PLL is active:
Disable Bits: The DMC and DHC bits in the PMMCR
register may be used to disable the high-frequency oscillator and PLL, respectively, in Power Save mode. THese
bits must be set in Idle and Halt modes.
Power Management Mode: Halt mode disables the
high-frequency oscillator and PLL. Active Mode enables
them. The DMC and DHC bits have no effect in Active or HALT
Halt mode.
PLL Power Down Bit: The PLLPWD bit in the CRCTRL
register can be used to disable the PLL in all modes. This
bit does not affect the high-frequency oscillator.
12.6
POWER MANAGEMENT REGISTERS
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Table 27 lists the power management registers.
Table 27 Power Management Registers
Address
Description
PMMCR
FF FC60h
Power Management
Control Register
PMMSR
FF FC62h
12.6.1
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Name
Power Management
Status Register
WBPSM
Power Management Control Register (PMMCR)
bs
The Power Management Control/Status Register (PMMCR)
is a byte-wide, read/write register that controls the operating
power mode (Active, Power Save, Idle, or Halt) and enables
or disables the high-frequency oscillator and PLL in the
Power Save mode. At reset, the non-reserved bits of this
register are cleared. The format of the register is shown below.
7
6
5
Reserved
4
3
2
1
0
DHC DMC WBPSM HALT IDLE PSM
DMC
If the Power Save Mode bit is clear and the
WBPSM bit is clear, writing 1 to the PSM bit
causes the device to start the switch to Power
Save mode. If the WBPSM bit is set when the
PSM bit is written with 1, entry into Power
Save mode is delayed until execution of a
WAIT instruction. The PSM bit becomes set
after the switch to Power Save mode is complete. The PSM bit can be cleared by software, and it can be cleared by hardware when
a hardware wake-up event is detected.
DHC
0 – Device is not in Power Save mode.
1 – Device is in Power Save mode.
O
PSM
The Idle Mode bit indicates whether the device has entered Idle mode. The WBPSM bit
must be set to enter Idle mode. When the
IDLE bit is written with 1, the device enters
IDLE mode at the execution of the next WAIT
instruction. The IDLE bit can be set and
cleared by software. It is also cleared by the
hardware when a hardware wake-up event is
detected.
0 – Device is not in Idle mode.
1 – Device is in Idle mode.
The Halt Mode bit indicates whether the device is in Halt mode. Before entering Halt
mode, the WBPSM bit must be set. When the
HALT bit is written with 1, the device enters
the Halt mode at the execution of the next
WAIT instruction. When in HALT mode, the
PMM stops the System Clock and then turns
off the PLL and the high-frequency oscillator.
The HALT bit can be set and cleared by software. The Halt mode is exited by a hardware
wake-up event. When this signal is set high,
the oscillator is started. After the oscillator has
stabilized, the HALT bit is cleared by the hardware.
0 – Device is not in Halt mode.
1 – Device is in Halt mode.
When the Wait Before Power Save Mode bit is
clear, a switch from Active mode to Power
Save mode only requires setting the PSM bit.
When the WBPSM bit is set, a switch from Active mode to Power Save, Idle, or Halt mode is
performed by setting the PSM, IDLE, or HALT
bit, respectively, and then executing a WAIT
instruction. Also, if the DMC or DHC bits are
set, the high-frequency oscillator and PLL
may be disabled only after a WAIT instruction
is executed and the Power Save, Idle, or Halt
mode is entered.
0 – Mode transitions may occur immediately.
1 – Mode transitions are delayed until the
next WAIT instruction is executed.
The Disable Main Clock bit may be used to
disable the high-frequency oscillator in Power
Save mode. In Active mode, the high-frequency oscillator is enabled without regard to the
DMC value. The DMC bit is cleared by hardware when a hardware wake-up event is detected. This bit must be set in Idle and Halt
modes.
0 – High-frequency oscillator is not disabled
in Power Save mode.
1 – High-frequency oscillator is disabled in
Power Save mode.
The Disable High-Frequency (PLL) Clock bit
and may be used to disable the PLL in Power
Save modes. When the DHC bit is clear (and
PLLPWD = 0), the PLL is enabled in Power
Save mode. If the DHC bit is set, the PLL is
disabled in Power Save mode. The DHC bit is
cleared by hardware when a hardware wake-
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58
12.6.2
Switching from a higher to a lower power consumption
mode is performed by writing an appropriate value to the
Power Management Control/Status Register (PMMCR).
Switching from a lower power consumption mode to the Active mode is usually triggered by a hardware interrupt.
Figure 9 shows the four power consumption modes and the
events that trigger a transition from one mode to another.
Power Management Status Register (PMMSR)
The Management Status Register (PMMR) is a byte-wide,
read/write register that provides status signals for the various clocks. The reset value of PMSR register bits 0 to 2 depend on the status of the clock sources monitored by the
PMM. The upper 5 bits are clear after reset. The format of
the register is shown below.
3
Reserved
OMC
OHC OMC
0
OLC
Active Mode
WBPSM = 0 & PSM = 1
or
WBPSM = 1 & PSM = 1 & "WAIT"
WBPSM = 1 &
IDLE = 1 &
"WAIT"
The Oscillating Low Frequency Clock bit indicates whether the low-frequency oscillator is
producing a stable clock. When the low-frequency oscillator is unavailable, the PMM will
not switch to Power Save, Idle, or Halt mode.
0 – Low-frequency oscillator is unstable, disabled, or not oscillating.
1 – Low-frequency oscillator is available.
The Oscillating Main Clock bit indicates
whether the high-frequency oscillator is producing a stable clock. When the high-frequency oscillator is unavailable, the PMM will not
switch to Active mode.
0 – High-frequency oscillator is unstable, disabled, or not oscillating.
1 – High-frequency oscillator is available.
The Oscillating High Frequency (PLL) Clock
bit indicates whether the PLL is producing a
stable clock. Because the PMM tests the stability of the PLL clock to qualify power mode
state transitions, a stable clock is indicated
when the PLL is disabled. This removes the
stability of the PLL clock from the test when
the PLL is disabled. When the PLL is enabled
but unstable, the PMM will not switch to Active
mode.
0 – PLL is enabled but unstable.
1 – PLL is stable or disabled (CRCTRL.PLLPWD = 0).
O
bs
OHC
1
WBPSM = 1 &
HALT = 1 &
"WAIT"
Power Save Mode
HW Event
Idle Mode
Halt Mode
HW Event
HW Event
Note:
HW Event = MIWU wake-up or NMI
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OLC
2
Reset
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SWITCHING BETWEEN POWER MODES
DS422
Figure 9. Power Mode State Diagram
Some of the power-up transitions are based on the occurrence of a wake-up event. An event of this type can be either
a maskable interrupt or a non-maskable interrupt (NMI). All
of the maskable hardware wake-up events are monitored by
the Multi-Input Wake-Up (MIWU) Module, which is active in
all modes. Once a wake-up event is detected, it is latched
until an interrupt acknowledge cycle occurs or a reset is applied.
A wake-up event causes a transition to the Active mode and
restores normal clock operation, but does not start execution of the program. It is the interrupt handler associated
with the wake-up source (MIWU or NMI) that causes program execution to resume.
12.7.1
Active Mode to Power Save Mode
A transition from Active mode to Power Save mode is performed by writing a 1 to the PMMCR.PSM bit. The transition
to Power Save mode is either initiated immediately or at execution of the next WAIT instruction, depending on the state
of the PMMCR.WBPSM bit.
For an immediate transition to Power Save mode (PMMCR.WBPSM = 0), the CPU continues to operate using the
low-frequency clock. The PMMCR.PSM bit becomes set
when the transition to the Power Save mode is completed.
For a transition at the next WAIT instruction (PMMCR.WBPSM = 1), the CPU continues to operate in Active
mode until it executes a WAIT instruction. At execution of
the WAIT instruction, the device enters the Power Save
mode, and the CPU waits for the next interrupt event. In this
case, the PMMCR.PSM bit becomes set when it is written,
even before the WAIT instruction is executed.
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CP3UB17
12.7
up event is detected. This bit must be set in
Idle and Halt modes.
0 – PLL is not disabled in Power Save mode.
1 – PLL is disabled in Power Save mode.
CP3UB17
12.7.2
Entering Idle Mode
12.7.6
Entry into Idle mode is performed by writing a 1 to the PMMCR.IDLE bit and then executing a WAIT instruction. The
PMMCR.WBPSM bit must be set before the WAIT instruction is executed. Idle mode can be entered only from the Active mode. The DHC and DMC bits must be set when
entering Idle mode.
12.7.3
A hardware wake-up event switches the device directly from
Power Save, Idle, or Halt mode to Active mode. Hardware
wake-up events are:
Non-Maskable Interrupt (NMI)
Valid wake-up event on a Multi-Input Wake-Up channel
When a wake-up event occurs, the on-chip hardware performs the following steps:
Disabling the High-Frequency Clock
When the low-frequency oscillator is used to generate the
Slow Clock, power consumption can be reduced further in
the Power Save mode by disabling the high-frequency oscillator. This is accomplished by writing a 1 to the PMMCR.DHC bit before executing the WAIT instruction that
puts the device in the Power Save mode. The high-frequency clock is turned off only after the device enters the Power
Save mode.
12.7.4
Entering Halt Mode
12.7.7
Power Mode Switching Protection
The Power Management Module has several mechanisms
to protect the device from malfunctions caused by missing
or unstable clock signals.
The PMMSR.OHC, PMMSR.OMC, and PMMSR.OLC bits
indicate the current status of the PLL, high-frequency oscillator, and low-frequency oscillator, respectively. Software
can check the appropriate bit before switching to a power
mode that requires the clock. A set status bit indicates an
operating, stable clock. A clear status bit indicates a clock
that is disabled, not available, or not yet stable. (Except in
the case of the PLL, which has a set status bit when disabled.)
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Immediately after power-up and entry into Active mode,
software must wait for the low-frequency clock to become
stable before it can put the device in Power Save mode. It
should monitor the PMMSR.OLC bit for this purpose. Once
this bit is set, Slow Clock is stable and Power Save mode
can be entered.
1. Clears the PMMCR.DMC bit, which enables the highfrequency clock (if it was disabled).
2. Waits for the PMMSR.OMC bit to become set, which indicates that the high-frequency clock is operating and
is stable.
3. Clears the PMMCR.DHC bit, which enables the PLL.
4. Waits for the PMMSR.OHC bit to become set.
5. Switches the device into Active mode.
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The CPU operates on the low-frequency clock in Power
Save mode. It can turn off the high-frequency clock at any
time by writing a 1 to the PMMCR.DHC bit. The high-frequency oscillator is always enabled in Active mode and always disabled in Halt mode, without regard to the
PMMCR.DHC bit setting.
Wake-Up Transition to Active Mode
Entry into Halt mode is accomplished by writing a 1 to the
PMMCR.HALT bit and then executing a WAIT instruction.
The PMMCR.WBPSM bit must be set before the WAIT instruction is executed. Halt mode can be entered only from
Active mode. The DHC and DMC bits must be set when entering Idle mode.
During a power mode transition, if there is a request to
switch to a mode with a clear status bit, the switch is delayed
until that bit is set by the hardware.
O
bs
When the system is built without an external crystal network
for the low-frequency clock, Main Clock is divided by a prescaler factor to produce the low-frequency clock. In this situ12.7.5 Software-Controlled Transition to Active Mode ation, Main Clock is disabled only in the Idle and Halt
A transition from Power Save mode to Active mode can be modes, and cannot be disabled for the Power Save mode.
accomplished by either a software command or a hardware Without an external crystal network for the low-frequency
wake-up event. The software method is to write a 0 to the clock, the device comes out of Halt or Idle mode and enters
PMMCR.PSM bit. The value of the register bit changes only Active mode with Main Clock driving Slow Clock.
after the transition to the Active mode is completed.
Note: For correct operation in the absence of a low-freIf the high-frequency oscillator is disabled for Power Save quency crystal, the X2CKI pin must be tied low (not left floatoperation, the oscillator must be enabled and allowed to sta- ing) so that the hardware can detect the absence of the
bilize before the transition to Active mode. To enable the crystal.
high-frequency oscillator, software writes a 0 to the PMMCR.DMC bit. Before writing a 0 to the PMMCR.PSM bit,
software must first monitor the PMMSR.OMC bit to determine when the oscillator has stabilized.
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60
The Multi-Input Wake-Up Unit (MIWU) monitors its 16 input
channels for a software-selectable trigger condition. On detection of a trigger condition, the module generates an interrupt request and if enabled, a wake-up request. A wake-up
request can be used by the power management unit to exit
the Halt, Idle, or Power Save mode and return to the active
mode. An interrupt request generates an interrupt to the
CPU (interrupt IRQ2–IRQ5), which allows an interrupt handler to respond to MIWU events.
The MIWU is active at all times, including the Halt mode. All
device clocks are stopped in this mode. Therefore, detecting
an external trigger condition and the subsequent setting of
the pending bit are not synchronous to the System Clock.
13.1
Table 29 Multi-Input Wake-Up Registers
The MIWU channels are named WUI0 through WUI15, as
shown in Table 28.
MIWU Channel
WUI0
WUI1
WUI2
WUI3
Source
Description
WKEDG
FF FC80h
Wake-Up Edge
Detection Register
WKENA
FF FC82h
Wake-Up Enable
Register
WKIENA
FF FC8Ch
Wake-Up Interrupt
Enable Register
WKICTL1
FF FC84h
Wake-Up Interrupt
Control Register 1
WKICTL2
FF FC86h
Wake-Up Interrupt
Control Register 2
ACCESS.bus
Reserved
FF FC88h
Wake-Up Pending
Register
WKPCL
FF FC8Ah
Wake-Up Pending
Clear Register
13.1.1
MWCS
CTS
WUI5
RXD
WUI6
Reserved
WUI7
AAI SFS
WUI8
USB Wake-Up
WUI9
PI6
O
WKPND
TWM-T0OUT
bs
WUI4
Address
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Table 28 MIWU Sources
Name
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The wake-up event only activates the clocks and CPU, but
does not by itself initiate execution of any code. It is the interrupt request associated with the MIWU that gets the CPU
to start executing code, by jumping to the corresponding interrupt handler. Therefore, setting up the MIWU interrupt
handler is essential for any wake-up operation.
There are four interrupt requests that can be routed to the
ICU as shown in Figure 10. Each of the 16 MIWU channels
can be programmed to activate one of these four interrupt
requests.
MULTI-INPUT WAKE-UP REGISTERS
Table 29 lists the MIWU unit registers.
WUI10
PG0
WUI11
PG1
WUI12
PG2
WUI13
PG3
WUI14
PG6
WUI15
PG7
Wake-Up Edge Detection Register (WKEDG)
The WKEDG register is a word-wide read/write register that
controls the edge sensitivity of the MIWU channels. The
WKEDG register is cleared upon reset, which configures all
channels to be triggered on rising edges. The register format is shown below.
15
0
WKED
WKED
The Wake-Up Edge Detection bits control the
edge sensitivity for MIWU channels. The
WKED15:0 bits correspond to the WUI[15:0]
channels, respectively.
0 – Triggered on rising edge (low-to-high
transition).
1 – Triggered on falling edge (high-to-low
transition).
Each channel can be configured to trigger on rising or falling
edges, as determined by the setting in the WKEDG register.
Each trigger event is latched into the WKPND register. If a
trigger event is enabled by its respective bit in the WKENA
register, an active wake-up/interrupt signal is generated.
Software can determine which channel has generated the
active signal by reading the WKPND register.
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CP3UB17
13.0 Multi-Input Wake-Up
CP3UB17
Peripheral BUS
...........
15
0
WKICTL 1-2
WKIENA
WUI0
0
Encoder
4
EXINT3:0 to ICU
15
WKEDG
WKPND
te
WUI15
Wake-Up Signal
To Power Mgt
WKENA
...........
Figure 10.
13.1.2
Wake-Up Enable Register (WKENA)
13.1.4
bs
The Wake-Up Enable bits enable and disable
the MIWU channels. The WKEN15:0 bits correspond to the WUI15:0 channels, respectively.
0 – MIWU channel wake-up events disabled.
1 – MIWU channel wake-up events enabled.
O
13.1.3
Wake-Up Interrupt Enable Register (WKIENA)
The WKIENA register is a word-wide read/write register that
enables and disables interrupts from the MIWU channels.
The register format is shown below.
15
0
WKIEN
WKIEN
Wake-Up Interrupt Control Register 1
(WKICTL1)
The WKICTL1 register is a word-wide read/write register
that selects the interrupt request signal for the associated
MIWU channels WUI7:0. At reset, the WKICTL1 register is
cleared, which selects MIWU Interrupt Request 0 for all
eight channels. The register format is shown below.
0
WKEN
WKEN
DS009
Multi-Input Wake-Up Module Block Diagram
The Wake-Up Enable (WKENA) register is a word-wide
read/write register that individually enables or disables
wake-up events from the MIWU channels. The WKENA register is cleared upon reset, which disables all wake-up/interrupt channels. The register format is shown below.
15
0
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15
The Wake-Up Interrupt Enable bits control
whether MIWU channels generate interrupts.
0 – Interrupt disabled.
1 – Interrupt enabled.
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62
15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
WKIN WKIN WKIN WKIN WKIN WKIN WKIN WKIN
TR7 TR6 TR5 TR4 TR3 TR2 TR1 TR0
WKINTR
The Wake-Up Interrupt Request Select fields
select which of the four MIWU interrupt requests are activated for the corresponding
channel.
00 – Selects MIWU interrupt request 0.
01 – Selects MIWU interrupt request 1.
10 – Selects MIWU interrupt request 2.
11 – Selects MIWU interrupt request 3.
Wake-Up Interrupt Control Register 2
(WKICTL2)
13.1.7
The Wake-Up Pending Clear (WKPCL) register is a wordwide write-only register that lets the CPU clear bits in the
WKPND register. Writing a 1 to a bit position in the WKPCL
register clears the corresponding bit in the WKPND register.
Writing a 0 has no effect. Do not modify this register with instructions that access the register as a read-modify-write
operand, such as the bit manipulation instructions.
The WKICTL2 register is a word-wide read/write register
that selects the interrupt request signal for the associated
MIWU channels WUI15 to WUI8. At reset, the WKICTL2
register is cleared, which selects MIWU Interrupt Request 0
for all eight channels. The register format is shown below.
15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
Reading this register location returns undefined data.
Therefore, do not use a read-modify-write sequence (such
as the SBIT instruction) to set individual bits. Do not attempt
to read the register, then perform a logical OR on the register value. Instead, write the mask directly to the register address. The register format is shown below.
0
WKIN WKIN WKIN WKIN WKIN WKIN WKIN WKIN
TR15 TR14 TR13 TR12 TR11 TR10 TR9 TR8
13.1.6
The Wake-Up Interrupt Request Select fields
select which of the four MIWU interrupt re15
quests are activated for the corresponding
channel.
00 – Selects MIWU interrupt request 0.
01 – Selects MIWU interrupt request 1.
10 – Selects MIWU interrupt request 2.
WKCL
11 – Selects MIWU interrupt request 3.
Wake-Up Pending Register (WKPND)
WKCL
13.2
Writing 1 to a bit clears it.
0 – Writing 0 has no effect.
1 – Writing 1 clears the corresponding bit in
the WKPD register.
PROGRAMMING PROCEDURES
ol
e
The WKPND register is a word-wide read/write register in
which the Multi-Input Wake-Up module latches any detected trigger conditions. The CPU can only write a 1 to any bit
position in this register. If the CPU attempts to write a 0, it
has no effect on that bit. To clear a bit in this register, the
CPU must use the WKPCL register. This implementation
prevents a potential hardware-software conflict during a
read-modify-write operation on the WKPND register.
0
te
WKINTR
Wake-Up Pending Clear Register (WKPCL)
To set up and use the Multi-Input Wake-Up function, use the
following procedure. Performing the steps in the order
shown will prevent false triggering of a wake-up condition.
This same procedure should be used following a reset because the wake-up inputs are left floating, resulting in unknown data on the input pins.
15
bs
This register is cleared upon reset. The register format is
shown below.
0
WKPD
The Wake-Up Pending bits indicate which
MIWU channels have been triggered. The
WKPD[15:0] bits correspond to the WUI[15:0]
channels. Writing 1 to a bit sets it.
To change the edge sensitivity of a wake-up channel, use
0 – Trigger condition did not occur.
1 – Trigger condition occurred.
the following procedure. Performing the steps in the order
shown will prevent false triggering of a wake-up/interrupt
condition.
O
WKPD
1. Clear the WKENA register to disable the MIWU channels.
2. Write the WKEDG register to select the desired type of
edge sensitivity (clear for rising edge, set for falling
edge).
3. Set all bits in the WKPCL register to clear any pending
bits in the WKPND register.
4. Set up the WKICTL1 and WKICTL2 registers to define
the interrupt request signal used for each channel.
5. Set the bits in the WKENA register corresponding to
the wake-up channels to be activated.
1. Clear the WKENA bit associated with the input to be reprogrammed.
2. Write the new value to the corresponding bit position in
the WKEDG register to reprogram the edge sensitivity
of the input.
3. Set the corresponding bit in the WKPCL register to
clear the pending bit in the WKPND register.
4. Set the same WKENA bit to re-enable the wake-up
function.
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CP3UB17
13.1.5
CP3UB17
14.0 Input/Output Ports
Each device has up to 40 software-configurable I/O pins, organized into five 8-bit ports. The ports are named Port B,
Port C, Port G, Port H, and Port I.
Different pins within the same port can be individually configured to operate in different modes.
Figure 11 is a diagram showing the I/O port pin logic. The
register bits, multiplexers, and buffers allow the port pin to
be configured into the various operating modes.The output
buffer is a TRI-STATE buffer with weak pull-up capability.
The weak pull-up, if used, prevents the port pin from going
to an undefined state when it operates as an input.
In addition to their general-purpose I/O capability, the I/O
pins of Ports G, H, and I have alternate functions for use
with on-chip peripheral modules such as the UART or the
Multi-Input Wake-Up module. The alternate functions of all
I/O pins are shown in Table 2.
Ports B and C are used as the 16-bit data bus when an external bus is enabled (100-pin devices only). This alternate
function is selected by enabling the DEV or ERE operating
environments, not by programming the port registers.
To reduce power consumption, input buffers configured for
general-purpose I/O are only enabled when they are read.
When configured for an alternate function, the input buffers
are enabled continuously. To minimize power consumption,
input signals to enabled buffers must be held within 0.2 volts
of the VCC or GND voltage.
The I/O pin characteristics are fully programmable. Each pin
can be configured to operate as a TRI-STATE output, pushpull output, weak pull-up input, or high-impedance input.
Q
D
Q
D
PxWKPU Register
VCC
ol
e
PxALT Register
te
D
PxALTS Register
The electrical characteristics and drive capabilities of the input and output buffers are described in Section 26.0.
Weak Pull-Up Enable
Q
Alt. A Device Direction
Output Enable
Alt. B Device Direction
D
Q
bs
PxDIR Register
Pin
Alt. A Device Data Outout
Data Out
Alt. B Device Data Outout
D
Q
PxDOUT Register
O
Alt. A Data Input
Data In
PxDIN Register
Alt. B Data Input
1
Data In Read Strobe
DS190
Analog Input
Figure 11.
I/O Port Pin Logic
Each port has an associated set of memory-mapped regis
ters used for controlling the port and for holding the port da
ta:
14.1
PORT REGISTERS
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64
PxALT: Port alternate function register
PxALTS: Port alternate function select register
PxDIR: Port direction register
PxDIN: Port data input register
PxDOUT: Port data output register
PxWPU: Port weak pull-up register
PxHDRV: Port high drive strength register
Table 30 Port Registers
PBDIR
PBDIN
PBDOUT
PBWPU
PBHDRV
PBALTS
PCALT
PCDIR
PCDIN
PCDOUT
PCHDRV
PCALTS
Port H Direction
Register
PHDIN
FF FCC4h
Port H Data Input
Register
PHDOUT
FF FCC6h
Port H Data Output
Register
PHWPU
FF FCC8h
Port H Weak Pull-Up
Register
PHHDRV
FF FCCAh
Port H High Drive
Strength Register
Port B Weak Pull-Up
Register
FF FB08h
FF FB0Ah
Port B High Drive
Strength Register
FF FB0Ch
Port B Alternate Function Select Register
FF FB10h
FF FB1Ah
Port C Alternate
Function Register
PHALTS
FF FCCCh
Port H Alternate Function Select Register
PIALT
FF FEE0h
Port I Alternate
Function Register
PIDIR
FF FEE2h
Port I Direction
Register
PIDIN
FF FEE4h
Port I Data Input
Register
PIDOUT
FF FEE6h
Port I Data Output
Register
PIWPU
FF FEE8h
Port I Weak Pull-Up
Register
PIHDRV
FF FEEAh
Port I High Drive
Strength Register
PIALTS
FF FEECh
Port I Alternate Function Select Register
Port C Direction
Register
Port C Data Input
Register
Port C Data Output
Register
Port C Weak Pull-Up
Register
Port C High Drive
Strength Register
FF FB1Ch
Port C Alternate Function Select Register
FF FCA0h
Port G Alternate
Function Register
O
PGALT
FF FCC2h
Port B Data Output
Register
FF FB06h
FF FB18h
PHDIR
Port B Data Input
Register
bs
PCWPU
Port H Alternate
Function Register
Port B Direction
Register
FF FB04h
FF FB16h
FF FCC0h
Port B Alternate
Function Register
FF FB02h
FF FB14h
PHALT
Description
FF FB00h
FF FB12h
Description
te
PBALT
Address
Address
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Name
Name
PGDIR
FF FCA2h
Port G Direction
Register
PGDIN
FF FCA4h
Port G Data Input
Register
PGDOUT
FF FCA6h
Port G Data Output
Register
PGWPU
FF FCA8h
Port G Weak Pull-Up
Register
PGHDRV
FF FCAAh
Port G High Drive
Strength Register
PGALTS
FF FCACh
Port G Alternate Function Select Register
In the descriptions of the ports and port registers, the lowercase letter “x” represents the port designation, either B, C,
G, H, or I. For example, “PxDIR register” means any one of
the port direction registers: PBDIR, PCDIR, PGDIR, PHDIR, or PIDIR.
All of the port registers are byte-wide read/write registers,
except for the port data input registers, which are read-only
registers. Each register bit controls the function of the corresponding port pin. For example, PGDIR.2 (bit 2 of the
PGDIR register) controls the direction of port pin PG2.
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CP3UB17
Table 30 Port Registers
CP3UB17
14.1.1
14.1.3
Port Alternate Function Register (PxALT)
Port Data Input Register (PxDIN)
The PxALT registers control whether the port pins are used The data input register (PxDIN) is a read-only register that
for general-purpose I/O or for their alternate function. Each returns the current state on each port pin. The CPU can
read this register at any time even when the pin is configport pin can be controlled independently.
A clear bit in the alternate function register causes the cor- ured as an output.
responding pin to be used for general-purpose I/O. In this
configuration, the output buffer is controlled by the direction
register (PxDIR) and the data output register (PxDOUT).
The input buffer is visible to software as the data input register (PxDIN).
7
PxDIN
A set bit in the alternate function register (PxALT) causes
the corresponding pin to be used for its peripheral I/O function. When the alternate function is selected, the output
buffer data and TRI-STATE configuration are controlled by
signals from the on-chip peripheral device.
7
Port Data Output Register (PxDOUT)
The data output register (PxDOUT) holds the data to be
driven on output port pins. In this configuration, writing to
the register changes the output value. Reading the register
returns the last value written to the register.
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14.1.2
14.1.4
The PxDIN bits indicate the state on the corresponding port pin.
0 – Pin is low.
1 – Pin is high.
A reset operation leaves the register contents unchanged.
At power-up, the PxDOUT registers contain unknown values.
0
PxALT
PxALT
PxDIN
te
A reset operation clears the port alternate function registers, which initializes the pins as general-purpose I/O ports.
This register must be enabled before the corresponding alternate function is enabled.
0
7
The PxALT bits control whether the corresponding port pins are general-purpose I/O
ports or are used for their alternate function by
an on-chip peripheral.
PxDOUT
0 – General-purpose I/O selected.
1 – Alternate function selected.
Port Direction Register (PxDIR)
bs
The port direction register (PxDIR) determines whether
each port pin is used for input or for output. A clear bit in this
register causes the corresponding pin to operate as an input, which puts the output buffer in the high-impedance
state. A set bit causes the pin to operate as an output, which
enables the output buffer.
14.1.5
0
PxDOUT
The PxDOUT bits hold the data to be driven
on pins configured as outputs in general-purpose I/O mode.
0 – Drive the pin low.
1 – Drive the pin high.
Port Weak Pull-Up Register (PxWPU)
O
The weak pull-up register (PxWPU) determines whether the
port pins have a weak pull-up on the output buffer. The pullup device, if enabled by the register bit, operates in the genA reset operation clears the port direction registers, which eral-purpose I/O mode whenever the port output buffer is
disabled. In the alternate function mode, the pull-ups are alinitializes the pins as inputs.
ways disabled.
7
0
A reset operation clears the port weak pull-up registers,
which disables all pull-ups.
PxDIR
PxDIR
7
The PxDIR bits select the direction of the corresponding port pin.
0 – Input.
1 – Output.
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66
0
PxWPU
PxWPU
The PxWPU bits control whether the weak
pull-up is enabled.
0 – Weak pull-up disabled.
1 – Weak pull-up enabled.
Port High Drive Strength Register (PxHDRV)
Table 31
The PxHDRV register is a byte-wide, read/write register that
controls the slew rate of the corresponding pins. The high
drive strength function is enabled when the corresponding
bits of the PxHDRV register are set. In both GPIO and alternate function modes, the drive strength function is enabled
by the PxHDRV registers. At reset, the PxHDRV registers
are cleared, making the ports low speed.
7
0
PxHDRV
14.1.7
The PxHDRV bits control whether output pins
are driven with slow or fast slew rate.
0 – Slow slew rate.
1 – Fast slew rate.
Port Alternate Function Select Register
(PxALTS)
7
0
PxALTS
The PxALTS bits select among two alternate
functions. Table 31 shows the mapping of the
PxALTS bits to the alternate functions. Unused PxALTS bits must be clear.
O
bs
PxALTS
PxALTS = 0
PxALTS = 1
PG0
RXD
WUI10
PG1
TXD
WUI11
PG2
RTS
WUI12
PG3
CTS
WUI13
PG4
Reserved
TB
PG5
SRFS
NMI
PG6
Reserved
WUI14
PG7
Reserved
WUI15
PH0
MSK
TIO1
PH1
MDIDO
TIO2
PH2
MDODI
TIO3
PH3
MWCS
TIO4
PH4
SCK
TIO5
PH5
SFS
TIO6
PH6
STD
TIO7
PH7
SRD
TIO8
PI0
Reserved
Reserved
PI1
Reserved
Reserved
PI2
Reserved
SRCLK
PI3
Reserved
Reserved
PI4
Reserved
Reserved
PI5
Reserved
Reserved
PI6
WUI9
Reserved
PI7
TA
Reserved
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The PxALTS register selects which of two alternate functions are selected for the port pin. These bits are ignored
unless the corresponding PxALT bits are set. Each port pin
can be controlled independently.
Port Pin
te
PxHDRV
Alternate Function Select
14.2
OPEN-DRAIN OPERATION
A port pin can be configured to operate as an inverting
open-drain output buffer. To do this, the CPU must clear the
bit in the data output register (PxDOUT) and then use the
port direction register (PxDIR) to set the value of the port
pin. With the direction register bit set (direction = out), the
value zero is forced on the pin. With the direction register bit
clear (direction = in), the pin is placed in the TRI-STATE
mode. If desired, the internal weak pull-up can be enabled
to pull the signal high when the output buffer is in TRISTATE mode.
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CP3UB17
14.1.6
CP3UB17
15.0 USB Controller
The USB node is an integrated USB node controller that fea- NodeOperational
tures enhanced DMA support with many automatic data This is the normal operating state of the node. In this state,
handling features. It is compatible with USB specification the node is configured for operation on the USB.
versions 1.0 and 1.1.
NodeSuspend
It integrates the required USB transceiver, a Serial Interface
Engine (SIE), and USB endpoint (EP) FIFOs. Seven end- A USB node is expected to enter NodeSuspend state when
point pipes are supported: one for the mandatory control 3 ms have elapsed without any detectable bus activity. The
endpoint and six to support interrupt, bulk, and isochronous USB node looks for this event and signals it by setting the
endpoints. Each endpoint pipe has a dedicated FIFO, 8 SD3 bit in the ALTEV register, which causes an interrupt, to
bytes for the control endpoint and 64 bytes for the other end- be generated (if enabled). Software should respond by putting the USB node in the NodeSuspend state.
points.
15.1
FUNCTIONAL STATES
15.1.1
Line Condition Detection
The USB node can resume normal operation under software control in response to a local event in the device. It can
wake up the USB bus via a NodeResume, or when detecting a resume command on the USB bus, which signals an
interrupt to the CPU.
te
At any given time, the USB node is in one of the following
states
NodeResume
Table 32 State Descriptions
State
If the host has enabled remote wake-ups from the node, the
USB node can initiate a remote wake-up.
Descriptions
Normal operation
NodeSuspend
Device operation suspend due to
USB inactivity
NodeResume
Device wake-up from suspended
state
NodeReset
Device reset
bs
The NodeSuspend, NodeResume, or NodeReset line condition causes a transition from one operating state to another. These conditions are detected by specialized hardware
and reported in the Alternate Event (ALTEV) register. If interrupts are enabled, an interrupt is generated on the occurrence of any of the specified conditions.
O
In addition to the dedicated input to the ICU for generating
interrupts on these USB state changes, a wake-up signal is
sent to the MIWU (see Section 13.0) when any activity is detected on the USB, if the bus was in the Idle state and the
USB node is in the NodeSuspend state. The MIWU can be
programmed to generate an edge-triggered interrupt when
this occurs.
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Once software detects the event, which wakes up the bus,
it releases the USB node from NodeSuspend state by initiating a NodeResume on the USB using the NFSR register.
The node software must ensure at least 5 ms of Idle on the
USB. While in NodeResume state, a constant “K” is signalled on the USB. This should last for at least 1 ms and no
more than 5 ms, after which the USB host should continue
sending the NodeResume signal for at least an additional
20 ms, and then completes the NodeResume operation by
issuing the End Of Packet (EOP) sequence.
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NodeOperational
68
To successfully detect the EOP, software must enter the
USB NodeOperational state by setting the NFSR register.
If no EOP is received from the host within 100 ms, software
must re-initiate NodeResume.
NodeReset
When detecting a NodeResume or NodeReset signal while
in NodeSuspend state, the USB node can signal this to the
CPU by generating an interrupt.
USB specifications require that a device must be ready to
respond to USB tokens within 10 ms after wake-up or reset.
ENDPOINT OPERATION
15.2.2
Transmit and Receive Endpoint FIFOs
The USB node uses a total of seven transmit and receive
FIFOs: one bidirectional transmit and receive FIFO for the
Packets are broadcast from the host controller to all nodes mandatory control endpoint, three transmit FIFOs, and
on the USB network. Address detection is implemented in three receive FIFOs. As shown in Table 33, the bidirectional
hardware to allow selective reception of packets and to per- FIFO for the control endpoint is 8 bytes deep. The additional
mit optimal use of CPU bandwidth. One function address unidirectional FIFOs are 64 bytes each for both transmit and
with seven different endpoint combinations is decoded in receive. Each FIFO can be programmed for one exclusive
parallel. If a match is found, then that particular packet is re- USB endpoint, used together with one globally decoded
ceived into the FIFO; otherwise it is ignored.
USB function address. Software must not enable both transThe incoming USB Packet Address field and Endpoint field mit and receive FIFOs for endpoint zero at any given time.
are extracted from the incoming bit stream. Then the adTable 33 Endpoint FIFO Sizes
dress field is compared to the Function Address register
(FADR). If a match is detected, the Endpoint field is comTX FIFO
RX FIFO
pared to all of the Endpoint Control registers (EPCn) in parEndpoint
allel. A match then causes the payload data to be received
Size
Size
Number
Name
Name
or transmitted using the respective endpoint FIFO.
(Bytes)
(Bytes)
15.2.1
Address Detection
FADR Register
Endpoint Field
Match
Match
Receive/
Transmit FIFO0
EPC0 Register
Transmit FIFO1
EPC1 Register
1
64
TXFIFO1
-
-
2
-
-
64
RXFIFO1
3
64
TXFIFO2
-
-
4
-
-
64
RXFIFO2
5
64
TXFIFO3
-
-
6
-
-
64
RXFIFO3
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ADDR Field
FIFO0 (bidirectional, 8 bytes)
te
0
USB Packet
bs
Receive FIFO1
EPC2 Register
Transmit FIFO2
EPC3 Register
Receive FIFO2
O
EPC4Register
Transmit FIFO3
If two endpoints in the same direction are programmed with
the same endpoint number and both are enabled, data is received or transmitted to/from the endpoint with the lower
number, until that endpoint is disabled for bulk or interrupt
transfers, or becomes full or empty for ISO transfers. For example, if receive EP2 and receive EP4 both use endpoint 5
and are both isochronous, the first OUT packet is received
into EP2 and the second OUT packet into EP4, assuming
no software interaction in between. For ISO endpoints, this
allows implementing a ping-pong buffer scheme together
with the frame number match logic.
Endpoints in different directions programmed with the same
endpoint number operate independently.
EPC5 Register
EPC6 Register
Figure 12.
Receive FIFO3
DS049
USB Function Address/Endpoint Decoding
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CP3UB17
15.2
CP3UB17
Bidirectional Control Endpoint FIFO0 Operation
Transmit Endpoint FIFO Operation (TXFIFO1, TXFIFO2,
TXFIFO3)
FIFO0 should be used for the bidirectional control endpoint
0. It can be configured to receive data sent to the default ad- The Transmit FIFOs for endpoints 1, 3, and 5 support bulk,
dress with the DEF bit in the EPC0 register. Isochronous interrupt, and isochronous USB packet transfers larger than
transfers are not supported for the control endpoint.
the actual FIFO size. Therefore, software must update the
The Endpoint 0 FIFO can hold a single receive or transmit FIFO contents while the USB packet is transmitted on the
packet with up to 8 bytes of data. Figure 13 shows the basic bus. Figure 14 illustrates the operation of the transmit
FIFOs.
operation in both receive and transmit direction.
Note: The actual current operating state is not directly visible to software.
FLUSH Bit, TXC0 Register
FLUSH (Resets TXRP and TXWP)
FLUSH Bit, RXC0 Register
TXRP
TFnS - 1
0X0
+
Write to TXD0
TXFL = TXWP - TXRP
RX_EN Bit,
RXC0 Register
te
IDLE
+
TXWP
TX FIFO n
TXFILL
+
RXWAIT
SETUP
Token
TX_EN Bit,
TXC0
Register
TXWAIT
OUT or
SETUP
Token
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TX_EN Bit,
TXC0 Register
(Zero-Length
Packet)
TCOUNT = TXRP - TXWP (= TFnS - TXFL)
Figure 14. Transmit FIFO Operation
FIFO0 Empty
(All Data Read)
IN Token
TFnS
TXRP
RX
bs
TX
DS050
Figure 13. Endpoint 0 Operation
TXWP
O
A packet written to the FIFO is transmitted if an IN token for
the respective endpoint is received. If an error condition is
detected, the packet data remains in the FIFO and transmission is retried with the next IN token.
The FIFO contents can be flushed to allow response to an
OUT token or to write new data into the FIFO for the next IN
token.
If an OUT token is received for the FIFO, software is informed that the FIFO has received data only if there was no
error condition (CRC or STUFF error). Erroneous receptions are automatically discarded.
TXFL
TCOUNT
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DS051
Transmission
Done
70
The Transmit FIFO n Size is the total number
of bytes available within the FIFO.
The Transmit Read Pointer is incremented every time the Endpoint Controller reads from
the transmit FIFO. This pointer wraps around
to zero if TFnS is reached. TXRP is never incremented beyond the value of the write
pointer TXWP. An underrun condition occurs if
TXRP equals TXWP and an attempt is made
to transmit more bytes when the LAST bit in
the TXCMDx register is not set.
The Transmit Write Pointer is incremented every time software writes to the transmit FIFO.
This pointer wraps around to zero if TFnS is
reached. If an attempt is made to write more
bytes to the FIFO than actual space available
(FIFO overrun), the write to the FIFO is ignored. If so, TCOUNT is checked for an indication of the number of empty bytes
remaining.
The Transmit FIFO Level indicates how many
bytes are currently in the FIFO. A FIFO warning is issued if TXFL decreases to a specific
value. The respective WARNn bit in the FWR
register is set if TXFL is equal to or less than
the number specified by the TFWL bit in the
TXCn register.
The Transmit FIFO Count indicates how many
empty bytes can be filled within the transmit
FIFO. This value is accessible by software in
the TXSn register.
USB CONTROLLER REGISTERS
The USB node has a set of memory-mapped registers that
can be read/written from the CPU bus to control the USB interface. Some register bits are reserved; reading from these
bits returns undefined data. Reserved register bits must always be written with 0.
The Receive FIFOs for endpoints 2, 4, and 6 support bulk,
interrupt, and isochronous USB packet transfers larger than
the actual FIFO size. If the packet length exceeds the FIFO
size, software must read the FIFO contents while the USB
packet is being received on the bus. Figure 15 shows the
detailed behavior of receive FIFOs.
Table 34 USB Controller Registers
Name
Address
Description
MCNTRL
FF FD80h
Main Control Register
NFSR
FF FD8Ah
Node Functional State
Register
MAEV
FF FD8Ch
Main Event Register
ALTEV
FF FD90h
Alternate Event
Register
FLUSH (Resets RXRP and RXWP)
RXRP
0X0
+
RCOUNT = RXWP - RXRF
+
te
RFnS - 1
RXWP
RX FIFO n
RXFL = RXRP - RXWP (= RFnS
- RCOUNT)
DS052
Figure 15. Receive FIFO Operation
RFnS
O
RXWP
The Receive FIFO n Size is the total number
of bytes available within the FIFO.
The Receive Read Pointer is incremented
with every read by software from the receive
FIFO. This pointer wraps around to zero if
RFnS is reached. RXRP is never incremented
beyond the value of RXWP. If an attempt is
made to read more bytes than are actually
available (FIFO underrun), the last byte is
read repeatedly.
The Receive Write Pointer is incremented every time the Endpoint Controller writes to the
receive FIFO. This pointer wraps around to
zero if RFnS is reached. An overrun condition
occurs if RXRP equals RXWP and an attempt
is made to write an additional byte.
The Receive FIFO Level indicates how many
more bytes can be received until an overrun
condition occurs with the next write to the
FIFO. A FIFO warning is issued if RXFL decreases to a specific value. The respective
WARNn bit in the FWR register is set if RXFL
is equal to or less than the number specified
by the RFWL bit in the RXCn register.
The Receive FIFO Count indicates how many
bytes can be read from the receive FIFO. This
value is accessible by software from the RXSn
register.
bs
RXRP
RXFL
RCOUNT
FF FD8Eh
Main Mask Register
ALTMSK
FF FD92h
Alternate Mask
Register
TXEV
FF FD94h
Transmit Event
Register
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+
MAMSK
71
TXMSK
FF FD96h
Transmit Mask
Register
RXEV
FF FD98h
Receive Event
Register
RXMSK
FF FD9Ah
Receive Mask
Register
NAKEV
FF FD9Ch
NAK Event Register
NAKMSK
FF FD9Eh
NAK Mask Register
FWEV
FF FDA0h
FIFO Warning Event
Register
FWMSK
FF FDA2h
FIFO Warning Mask
Register
FNH
FF FDA4h
Frame Number High
Byte Register
FNL
FF FDA6h
Frame Number Low
Byte Register
FAR
FF FD88h
Function Address
Register
DMACNTRL
FF FDA8h
DMA Control Register
DMAEV
FF FDAAh
DMA Event Register
DMAMSK
FF FDACh
DMA Mask Register
MIR
FF FDAEh
Mirror Register
DMACNT
FF FDB0h
DMA Count Register
DMAERR
FF FDB2h
DMA Error Register
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CP3UB17
15.3
Receive Endpoint FIFO Operation (RXFIFO1, RXFIFO2,
RXFIFO3)
Address
Description
Name
Address
Description
EPC0
FF FDC0h
Endpoint Control 0
Register
RXS3
FF FDFCh
Receive Status 3
Register
EPC1
FF FDD0h
Endpoint Control 1
Register
RXC0
FF FDCEh
Receive Command 0
Register
EPC2
FF FDD8h
Endpoint Control 2
Register
RXC1
FF FDDEh
Receive Command 1
Register
EPC3
FF FDE0h
Endpoint Control 3
Register
RXC2
FF FDEEh
Receive Command 2
Register
EPC4
FF FDDE8h
Endpoint Control 4
Register
RXC3
FF FDFEh
Receive Command 3
Register
EPC5
FF FDF0h
Endpoint Control 5
Register
RXD0
FF FDCAh
Receive Data 0
Register
EPC6
FF FDF8h
Endpoint Control 6
Register
TXS0
FF FDC4h
Transmit Status 0
Register
TXS1
FF FDD4h
Transmit Status 1
Register
TXS2
FF FDE4h
Transmit Status 2
Register
15.3.1
The MCNTRL register controls the main functions of the
USB node. The MCNTRL register provides read/write access from the CPU bus. Reserved bits must be written with
0, and they return 0 when read. It is clear after reset.
te
Name
FF FDDAh
Receive Data 2
Register
RXD2
FF FDEAh
Receive Data 2
Register
ol
e
TXS3
FF FDF4h
Transmit Status 3
Register
TXC0
FF FDC6h
Transmit Command 0
Register
TXC1
FF FDD6
Transmit Command 1
Register
TXC2
FF FDE6h
Transmit Command 2
Register
TXC3
FF FDF6h
Transmit Command 3
Register
FF FDC2h
Transmit Data 0
Register
TXD1
FF FDD2h
Transmit Data 1
Register
TXD2
FF FDE2h
Transmit Data 2
Register
TXD3
FF FDF2h
Transmit Data 3
Register
RXS0
FF FDCCh
Receive Status 0
Register
RXS1
FF FDDCh
Receive Status 1
Register
RXS2
FF FDECh
Receive Status 2
Register
O
TXD0
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RXD1
RXD3
bs
CP3UB17
Table 34 USB Controller Registers
Table 34 USB Controller Registers
72
FF FDFAh
Main Control Register (MCNTRL)
7
4
Reserved
USBEN
Receive Data 3
Register
3
NAT
2
1
Reserved
0
USBEN
The USB Enable controls whether the USB
module is enabled. If the USB module is disabled, the 48 MHz clock within the USB node
is stopped, all USB registers are initialized to
their reset state, and the USB transceiver forces SE0 on the bus to prevent the hub from detected the USB node. The USBEN bit is clear
after reset.
0 – The USB module is disabled.
1 – The USB module is enabled.
The Node Attached indicates that this node is
ready to be detected as attached to USB.
When clear, the transceiver forces SE0 on the
USB node controller to prevent the hub (to
which this node is connected) from detecting
an attach event. After reset or when the USB
node is disabled, this bit is cleared to give the
device time before it must respond to commands. After this bit has been set, the device
no longer drives the USB and should be ready
to receive Reset signaling from the hub.
0 – Node not ready to be detected as attached.
1 – Node ready to be detected as attached.
15.3.2
Node Functional State Register (NFSR)
The NFSR register reports and controls the current functional state of the USB node. The NFSR register provides
read/write access. It is clear after reset.
7
2
1
Reserved
NFS
0
NFS
The Node Functional State bits set the node
state, as shown in Table 35. Software should
initiate all required state transitions according
to the respective status bits in the Alternate
Event (ALTEV) register.
NFS
te
Table 35 USB Functional States
Node State
Description
NodeReset
01
NodeResume
In this state, resume “K” signalling is generated. This state should be entered by software to
initiate a remote wake-up sequence by the device. The node must remain in this state for at
least 1 ms and no more than 15 ms.
10
NodeOperational This is the normal operational state for operation on the USB bus.
NodeSuspend
Suspend state should be entered by software on detection of a Suspend event while in
Operational state. While in Suspend state, the transceivers operate in their low-power
suspend mode. All endpoint controllers and the bits TX_EN, LAST, and RX_EN are reset,
while all other internal states are frozen. On detection of bus activity, the RESUME bit in the
ALTEV register is set. In response, software can cause entry to NodeOperational state.
O
bs
11
ol
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00
This is the USB Reset state. This is entered upon a module reset or by software upon
detection of a USB Reset. Upon entry, all endpoint pipes are disabled. DEF in the Endpoint
Control 0 (EPC0) register and AD_EN in the Function Address (FAR) register should be
cleared by software on entry to this state. On exit, DEF should be reset so the device
responds to the default address.
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CP3UB17
NAT
CP3UB17
15.3.3
Main Event Register (MAEV)
RX_EV
The Receive Event bit is set if any of the unmasked bits in the Receive Event (RXEV) register is set. It indicates that a SETUP or OUT
transaction has been completed. This bit is
cleared when all of the RX_LAST bits in each
Receive Status (RXSn) register and all RXOVRRN bits in the RXEV register are cleared.
0 – No receive event has occurred.
1 – A receive event has occurred.
The Master Interrupt Enable bit is hardwired
to 0 in the Main Event (MAEV) register; bit 7
in the Main Mask (MAMSK) register is the
Master Interrupt Enable.
0 – USB interrupts disabled.
1 – USB interrupts enabled.
The Main Event Register summarizes and reports the main
events of the USB transactions. This register provides readonly access. The MAEV register is clear after reset.
7
6
5
4
3
2
1
0
INTR RX_EV ULD NAK FRAME TX_EV ALT WARN
INTR
FRAME
O
NAK
UL
Main Mask Register (MAMSK)
The MAMSK register masks out events reported in the
MAEV registers. A set bit enables the interrupts for the respective event in the MAEV register. If the corresponding bit
is clear, interrupt generation for this event is disabled. This
register provides read/write access. The MAMSK register is
clear after reset.
te
TX_EV
15.3.4
7
6
5
4
ol
e
ALT
The Warning Event bit indicates whether one
of the unmasked bits in the FIFO Warning
Event (FWEV) register has been set. This bit
is cleared by reading the FWEV register.
0 – No warning event occurred.
1 – A warning event has occurred.
The Alternate Event bit indicates whether one
of the unmasked ALTEV register bits has
been set. This bit is cleared by reading the ALTEV register.
0 – No alternate event has occurred.
1 – An alternate event has occurred.
The Transmit Event bit indicates whether any
of the unmasked bits in the Transmit Event
(TXEV) register (TXFIFOn or TXUNDRNn) is
set. Therefore, it indicates that an IN transaction has been completed. This bit is cleared
when all the TX_DONE bits and the TXUNDRN bits in each Transmit Status (TXSn) register are cleared.
0 – No transmit event has occurred.
1 – A transmit event has occurred.
The Frame Event bit indicates whether the
frame counter has been updated with a new
value, due to receipt of a valid SOF packet on
the USB or to an artificial update if the frame
counter was unlocked or a frame was missed.
This bit is cleared when the register is read.
0 – The frame counter has not been updated.
1 – Frame counter has been updated.
The Negative Acknowledge Event indicates
whether one of the unmasked NAK Event
(NAKEV) register bits has been set. This bit is
cleared when the NAKEV register is read.
0 – No unmasked NAK event has occurred.
1 – An unmasked NAK event has occurred.
The Unlocked/Locked Detected bit is set
when the frame timer has either entered unlocked condition from a locked condition, or
has re-entered a locked condition from an unlocked condition as determined by the UL bit
in the Frame Number (FNH or FNL) register.
This bit is cleared when the register is read.
0 – Frame timer has not entered an unlocked
condition from a locked condition or reentered a locked condition from an unlocked condition.
1 – Frame timer has either entered an unlocked condition from a locked condition
or re-entered a locked condition from an
unlocked condition.
bs
WARN
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74
3
2
1
0
INTR RX_EV ULD NAK FRAME TX_EV ALT WARN
15.3.5
Alternate Event Register (ALTEV)
The ALTEV register summarizes and reports the further
events in the USB node. This register provides read-only access. The ALTEV register is clear after reset.
7
6
5
RESUME RESET SD5
DMA
EOP
4
3
2
1
0
SD3 EOP DMA Reserved
The DMA Event bit indicates that one of the
unmasked bits in the DMA Event (DMAEV)
register has been set. The DMA bit is readonly and clear, when the DMAEV register is
cleared.
0 – No DMA event has occurred.
1 – A DMA event has occurred.
The End of Packet bit indicates whether a valid EOP sequence has been detected on the
USB. It is used when this device has initiated a
Remote wake-up sequence to indicate that the
Resume sequence has been acknowledged
and completed by the host. This bit is cleared
when the register is read.
0 – No EOP sequence detected.
1 – EOP sequence detected.
7
4
3
TXUDRRN
TXFIFO
TXUDRRN
0
TXFIFO
The Transmit FIFO n bits are copies of the
TX_DONE bits from the corresponding Transmit Status registers (TXSn). A bit is set when
the IN transaction for the corresponding transmit endpoint n has been completed. These
bits are cleared when the corresponding
TXSn register is read.
The Transmit Underrun n bits are copies of the
respective TX_URUN bits from the corresponding Transmit Status registers (TXSn).
Whenever any of the Transmit FIFOs underflows, the respective TXUDRRN bit is set.
These bits are cleared when the corresponding Transmit Status register is read.
Note: Since Endpoint 0 implements a store
and forward principle, an underrun condition
for FIFO0 cannot occur. This results in the
TXUDRRN0 bit always being read as 0.
15.3.8
Transmit Mask Register (TXMSK)
The TXMSK register is used to select the bits of the TXEV
registers, which causes the TX_EV bit in the MAEV register
to be set. When a bit is set and the corresponding bit in the
TXEV register is set, the TX_EV bit in the MAEV register is
set. When clear, the corresponding bit in the TXEV register
does not cause TX_EV to be set. The TXMSK register provides read/write access. It is clear after reset.
7
4
TXUDRRN
3
0
TXFIFO
Alternate Mask Register (ALTMSK)
O
15.3.6
The TXEV register reports the current status of the FIFOs,
used by the three Transmit Endpoints. The TXEV register is
clear after reset. It provides read-only access.
bs
RESUME
Transmit Event Register (TXEV)
te
RESET
15.3.7
ol
e
SD5
The Suspend Detect 3 ms bit is set after 3 ms
of IDLE have been detected on the upstream
port, indicating that the device should be suspended. The suspend occurs under software
control by writing the suspend value to the
Node Functional State (NFSR) register. This
bit is cleared when the register is read.
0 – No 3 ms in IDLE has been detected.
1 – 3 ms in IDLE has been detected.
The Suspend Detect 5 ms bit is set after 5 ms
of IDLE have been detected on the upstream
port, indicating that this device is permitted to
perform a remote wake-up operation. The resume may be initiated under software control
by writing the resume value to the NFSR register. This bit is cleared when the register is
read.
0 – No 5 ms in IDLE has been detected.
1 – 5 ms in IDLE has been detected.
The Reset bit is set when 2.5 µs of SEO have
been detected on the upstream port. In response, the functional state should be reset
(NFS in the NFSR register is set to RESET),
where it must remain for at least 100 µs. The
functional state can then return to Operational
state. This bit is cleared when the register is
read.
0 – No 2.5 µs in SEO have been detected.
1 – 2.5 µs in SEO have been detected.
The Resume bit indicates whether resume
signalling has been detected on the USB
when the device is in Suspend state (NFS in
the NFSR register is set to SUSPEND), and a
non-IDLE signal is present on the USB, indicating that this device should begin its wakeup sequence and enter Operational state. Resume signalling can only be detected when
the 48 MHz PLL clock is enabled to the USB
controller. This bit is cleared when the register
is read.
0 – No resume signalling detected.
1 – Resume signalling detected.
A set bit in the ALTMSK register enables automatic setting
of the ALT bit in the MAEV register when the respective
event in the ALTEV register occurs. Otherwise, setting
MAEV.ALT bit is disabled. The ALTMSK register is clear after reset. It provides read/write access from the CPU bus.
7
6
5
RESUME RESET SD5
4
3
2
1
0
SD3 EOP DMA Reserved
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CP3UB17
SD3
Receive Event Register (RXEV)
15.3.11 NAK Event Register (NAKEV)
The RXEV register reports the current status of the FIFO,
used by the three Receive Endpoints. The RXEV register is
clear after reset. It provides read-only access from the CPU
bus.
7
4
3
RXOVRRN
7
RXFIFO
The Receive FIFO n are set whenever either
RX_ERR or RX_LAST in the respective Receive Status registers (RXSn) are set. Reading the corresponding RXSn register
automatically clears these bits. The USB node
discards all packets for Endpoint 0 received
with errors. This is necessary in case of retransmission due to media errors, ensuring
that a good copy of a SETUP packet is captured. Otherwise, the FIFO may potentially be
tied up, holding corrupted data and unable to
receive a retransmission of the same packet
(the RXFIFO0 bit only reflects the value of
RX_LAST for Endpoint 0). If data streaming is
used for the receive endpoints (EP2, EP4 and
EP6), software must check the respective
RX_ERR bits to ensure the packets received
are not corrupted by errors.
The Receive Overrun n bits are set when an
overrun condition is indicated in the corresponding receive FIFO n. They are cleared
when the register is read. Software must
check the respective RX_ERR bits that packets received for the other receive endpoints
(EP2, EP4 and EP6) are not corrupted by errors, as these endpoints support data streaming (packets which are longer than the actual
FIFO depth).
IN
15.3.10 Receive Mask Register (RXMSK)
O
The RXMSK register is used to select the bits of the RXEV
register, which cause the RX_EV bit in the MAEV register to
be set. When set and the corresponding bit in the RXEV
register is set, RX_EV bit in the MAEV register is set. When
clear, the corresponding bit in the RXEV register does not
cause the RX_EV bit to be set. The RXMSK register provides read/write access. This register is clear after reset.
7
4
RXOVRRN
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4
3
OUT
bs
RXOVRRN
0
OUT
0
IN
The IN n bits are set when a NAK handshake
is generated for an enabled address/endpoint
combination (AD_EN in the Function Address, FAR, register is set and EP_EN in the
Endpoint Control, EPCx, register is set) in response to an IN token. These bits are cleared
when the register is read.
The OUT n bits are set when a NAK handshake is generated for an enabled address/
endpoint combination (AD_EN in the FAR register is set and EP_EN in the EPCx register is
set) in response to an OUT token. These bits
are not set if NAK is generated as result of an
overrun condition. They are cleared when the
register is read.
ol
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RXFIFO
A bit in the NAKEV register is set when a Negative Acknowledge (NAK) was generated by the corresponding endpoint.
The NAKEV register provides read-only access from the
CPU bus. It is clear after reset.
te
CP3UB17
15.3.9
3
0
RXFIFO
76
15.3.12 NAK Mask Register (NAKMSK)
The NAKMSK register is used to select the bits of the NAKEV register, which cause the NAK bit in the MAEV register
to be set. When set and the corresponding bit in the NAKEV
register is set, the NAK bit in the MAEV register is set. When
cleared, the corresponding bit in the NAKEV register does
not cause NAK to be set. The NAKMSK register provides
read/write access. It is clear after reset.
7
4
OUT
3
0
IN
15.3.15 Frame Number High Byte Register (FNH)
The FWEV register signals whether a receive or transmit
FIFO has reached its warning limit. It reports the status for
all FIFOs, except for the Endpoint 0 FIFO, as no warning
limit can be specified for this FIFO. The FWEV register provides read-only access from the CPU bus. It is clear after reset.
The FNH register contains the three most significant bits
(MSB) of the current frame counter as well as status and
control bits for the frame counter. This register is loaded with
C0h after reset. It provides access from the CPU bus as described below.
7
5
RXWARN3:1
4
3
Res.
1
TXWARN3:1
0
7
6
5
MF
UL
RFC
4
3
2
0
Reserved
FN10:8
Res.
FN10:8
The Frame Number field holds the three most
significant bits (MSB) of the current frame
number, received in the last SOF packet. If a
valid frame number is not received within
12060 bit times (Frame Length Maximum, FLMAX, with tolerance) of the previous change,
the frame number is incremented artificially. If
two successive frames are missed or are incorrect, the current FN is frozen and loaded
with the next frame number from a valid SOF
packet. If the frame number low byte was read
by software before reading the FNH register,
software actually reads the contents of a buffer register which holds the value of the three
frame number bits of this register when the
low byte was read. Therefore, the correct sequence to read the frame number is: FNL,
FNH. Read operations to the FNH register,
without first reading the Frame Number Low
Byte (FNL) register directly, read the actual
value of the three MSBs of the frame number.
The FN bits provide read-only access. On reset, the FN bits are cleared.
The Reset Frame Count bit is used to reset
the frame number to 000h. This bit always
reads as 0. Due to the synchronization elements the frame counter reset actually occurs
a maximum of 3 USB clock cycles (12 MHz)
plus 2.5 CPU clock cycles after the write to the
RFC bit.
0 – Writing 0 has no effect.
1 – Writing 1 resets the frame counter.
The Unlock Flag bit indicates that at least two
frames were received without an expected
frame number, or that no valid SOF was received within 12060 bit times. If this bit is set,
the frame number from the next valid SOF
packet is loaded in FN. The UL bit provides
read-only access. After reset, this bit is set.
This bit is set by the hardware and is cleared
by reading the FNH register.
0 – No condition indicated.
1 – At least two frames were received without
an expected frame number, or no valid
SOF was received within 12060 bit times.
ol
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The Transmit Warning n bits are set when the
respective transmit endpoint FIFO reaches
the warning limit, as specified by the TFWL
bits of the respective TXCn register, and
transmission from the respective endpoint is
enabled. These bits are cleared when the
warning condition is cleared by either writing
new data to the FIFO when the FIFO is
flushed, or when transmission is done, as indicated by the TX_DONE bit in the TXSn register.
RXWARN3:1 The Receive Warning n bits are set when the
respective receive endpoint FIFO reaches the
warning limit, as specified by the RFWL bits of
the respective EPCx register. These bits are
cleared when the warning condition is cleared
by either reading data from the FIFO or when
the FIFO is flushed.
te
TXWARN3:1
15.3.14 FIFO Warning Mask Register (FWMSK)
5
RXWARN3:1
4
Res.
O
7
bs
The FWMSK register selects which FWEV bits are reported
in the MAEV register. A set FWMSK bit with the corresponding bit in the FWEV register set, causes the WARN bit in the RFC
MAEV register to be set. When clear, the corresponding bit
in the FWEV register does not cause WARN to be set. The
FWMSK register provides read/write access. This register is
clear after reset.
3
1
TXWARN3:1
0
Res.
UL
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CP3UB17
15.3.13 FIFO Warning Event Register (FWEV)
CP3UB17
MF
The Missed SOF bit is set when the frame
number in a valid received SOF does not
match the expected next value, or when an
SOF is not received within 12060 bit times.
The MF bit provides read-only access. On reset, this bit is set. This bit is set by the hardware and is cleared by reading the FNH
register.
0 – No condition indicated.
1 – The frame number in a valid SOF does
not match the expected next value, or no
valid SOF was received within 12060 bit
times.
15.3.18 Control Register (DMACNTRL)
The DMACNTRL register controls the main DMA functions
of the USB node. The DMACTRL register provides read/
write access. This register is clear after reset.
7
6
DEN
IGNRXTGL
DSRC
15.3.16 Frame Number Low Byte Register (FNL)
7
0
DMOD
bs
The Function Address Register specifies the device function address. The different endpoint numbers are set for
each endpoint individually using the Endpoint Control registers. The FAR register provides read/write access. After reset, this register is clear. If the DEF bit in the Endpoint
Control 0 register is set, Endpoint 0 responds to the default
address.
O
AD_EN
AD
AD_EN
0
AD
The Address field holds the 7-bit function ad- ADMA
dress used to transmit and receive all tokens
addressed to this device.
The Address Enable bit controls whether the
AD field is used for address comparison. If
not, the device does not respond to any token
on the USB bus.
0 – The device does not respond to any token
on the USB bus.
1 – The AD field is used for address comparison.
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0
DSRC
The DMA Source bit field holds the binary-encoded value that specifies which of the endpoints, 1 to 6, is enabled for DMA support. The
DSRC bits are cleared on reset. Table 36
summarizes the DSRC bit settings.
DSRC
15.3.17 Function Address Register (FAR)
6
2
Table 36 DSRC Bit Description
Note: If the frame counter is updated due to a receipt of a
valid SOF or an artificial update (i.e. missed frame or unlocked/locked detect), it will take the synchronization elements a maximum of 2.5 CPU clock cycles to update the
FNH and FNL registers.
7
3
DTGL ADMA DMOD
Endpoint Number
000
1
001
2
010
3
011
4
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FN7:0
4
te
The FNL register holds the low byte of the frame number, as
described above. To ensure consistency, reading this low
byte causes the three frame number bits in the FNH register
to be locked until this register is read. The correct sequence
to read the frame number is: FNL first, followed by FNH.
This register provides read-only access. After reset, the
FNL register is clear.
5
78
100
5
101
6
11x
Reserved
The DMA Mode bit specifies when a DMA request is issued. If clear, a DMA request is issued on transfer completion. For transmit
endpoints EP1, EP3, and EP5, the data is
completely transferred, as indicated by the
TX_DONE bit (to fill the FIFO with new transmit data). For receive endpoints EP2, EP4,
and EP6, this is indicated by the RX_LAST bit.
When the DMOD bit is set, a DMA request is
issued when the respective FIFO warning bit
is set. The DMOD bit is cleared after reset.
0 – DMA request is issued on transfer completion.
1 – DMA request is issued when the respective FIFO warning bit is set.
The Automatic DMA bit enables Automatic
DMA (ADMA) and automatically enables the
selected receive or transmit endpoint. Before
ADMA mode can be enabled, the DEN bit in
the DMA Control (DMACNTRL) register must
be cleared. ADMA mode functions until any bit
in the DMA Event (DMAEV) register is set, except for NTGL. To initiate ADMA mode, all bits
in the DMAEV register must be cleared, except for NTGL.
0 – Automatic DMA disabled.
1 – Automatic DMA enabled.
TX_DONE bit (set) and the ACK_STAT bit (not
set). If the AEH bit in the DMA Error Count
(DMAERR) register is set, the DERR bit is not
set until DMAERRCNT in the DMAERR register is cleared, and another error is detected.
Errors are handled as specified in the DMAERR register. The DERR bit provides read access and can only be written with a 0 from the
CPU bus. After reset this bit is cleared.
0 – No DMA error occurred.
1 – DMA error occurred.
The DMA Count bit is set when the DMA
Count (DMACNT) register is 0 (see the
DMACNT register for more information). The
DCNT bit provides read access and can only
be written with a 0 from the CPU bus. After reset this bit is cleared.
0 – DMACNT register is not 0.
1 – DMACNT register is 0.
The DMA Size bit is only significant for DMA
receive operations. It indicates, by being set,
that a packet has been received which is less
than the full length of the FIFO. This normally
indicates the end of a multi-packet transfer.
The DSIZ bit provides read access and can
only be written with a 0 from the CPU bus. After reset this bit is cleared.
0 – No condition indicated.
1 – A packet has been received which is less
than the full length of the FIFO.
The Automatic DMA Ready bit is set when the
ADMA mode is ready and active. After setting
the DMACNTRL.ADMA bit and the active
USB transaction (if any) is finished and the
specified endpoint (DMACNTRL.DSRC) is
flushed, the USB node enters ADMA mode.
This bit is automatically cleared when the
ADMA mode is finished and the current DMA
operation is completed. After reset the ARDY
bit is cleared.
0 – ADMA mode not ready.
1 – ADMA mode ready and active.
The Next Toggle bit determines the toggle
state of the next data packet sent (if transmitting), or the expected toggle state of the next
data packet (if receiving). This bit is initialized
by writing to the DTGL bit of the DMACNTRL
register. It then changes state with every
packet sent or received on the endpoint presently selected by DSRC[2:0]. If DTGL write
operation occurs simultaneously with the bit
update operation, the write takes precedence.
If transmitting, whenever ADMA operations
are in progress the DTGL bit overrides the
corresponding TOGGLE bit in the TXCx register. In this way, the alternating data toggle occurs correctly on the USB. Note that there is
no corresponding mask bit for this event because it is not used to generate interrupts.
The NTGL bit provides read-only access from
the CPU bus and is cleared after reset.
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The DMA Toggle bit is used to determine the
initial state of Automatic DMA (ADMA) operations. Software initially sets this bit if starting
with a DATA1 operation, and clears this bit if
starting with a DATA0 operation. Writes to this
bit also update the NTGL bit in the DMAEV
register.
IGNRXTGL The Ignore RX Toggle controls whether the
compare between the NTGL bit in the DMAEV
register and the TOGGLE bit in the respective
RXSn register is ignored during receive operations. If the compare is ignored, a mismatch DCNT
of the bits during a receive operation does not
stop ADMA operation. If the compare is not ignored, the ADMA stops in case of a mismatch
of the two toggle bits. After reset, this bit is
cleared.
0 – Compare toggle bits.
1 – Ignore toggle bits.
DEN
The DMA Enable bit enables DMA mode. If DSIZ
DMA mode is disabled and the current DMA
cycle has been completed (or was not yet issued) the DMA transfer is terminated. This bit
is cleared after reset.
0 – DMA mode disabled.
1 – DMA mode enabled.
15.3.19 DMA Event Register (DMAEV)
7
bs
The DMAEV register bits are used in ADMA mode. Bits 0 to
3 may cause an interrupt if not cleared, even if the device is
not set to ADMA mode. Until all of these bits are cleared, ARDY
ADMA mode cannot be initiated. Conversely, ADMA mode
is automatically terminated when any of these bits are set.
The DMAEV register provides access from the CPU bus as
described below. It is clear after reset.
6
Reserved
4
3
2
1
0
NTGL ARDY DSIZ DCNT DERR DSHLT
The DMA Software Halt bit is set when ADMA
operations have been halted by software. This NTGL
bit is set by the hardware only after the DMA
engine completes any necessary cleanup operations and returns to Idle state.
The DSHLST bits provide read access and
can only be written with a 0 from the CPU bus.
After reset these bits are cleared.
0 – No software ADMA halt.
1 – ADMA operations have been halted by
software.
The DMA Error bit is set to indicate that a
packet has not been received or transmitted
correctly. It is also set, if the TOGGLE bit in the
RXSx/TXSx register does not equal the NTGL
bit in the DMAEV register after packet reception/transmission. (Note that this comparison
is made before the NTGL bit changes state
due to packet transfer). For receiving, the
DERR bit is equivalent to the RX_ERR bit. For
transmitting, the DERR bit is equivalent to the
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DTGL
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15.3.20 DMA Mask Register (DMAMSK)
15.3.23 DMA Error Register (DMAERR)
Any set bit in the DMAMSK register enables automatic setting of the DMA bit in the ALTEV register when the respective event in the DMAEV register occurs. Otherwise, setting
the DMA bit is disabled. For a description of bits 0 to 3, see
the DMAEV register. The DMAMSK register provides read/
write access. After reset it is clear. Reading reserved bits returns undefined data.
The DMAERR register holds the 7-bit DMA error counter
and a control bit to specify DMA error handling. The DMAERR register provides read/write access. It is clear after reset.
7
AEH
7
4
Reserved
3
2
1
DMAERRCNT
The MIR register is a read-only register. Because reading it
does not alter the state of the TXSn or RXSn register to
which it points, software can freely check the status of the
channel. At reset it is initialized to 1Fh.
0
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DMAERRCNT The DMA Error Counter, together with the automatic error handling feature, defines the
maximum number of consecutive bus errors
before ADMA mode is stopped. Software can
set the 7-bit counter to a preset value. Once
ADMA is started, the counter decrements
from the preset value by 1 every time a bus error is detected. Every successful transaction
resets the counter back to the preset value.
When ADMA mode is stopped, the counter is
also set back to the preset value. If the
counter reaches 0 and another erroneous
packet is detected, the DERR bit in the DMA
Event register is set. This register cannot underrun. Software loads DMAERRCNT with 3D
(maximum number of allowable transfer attempts) - 1. A write access to this register is
only possible when ADMA is inactive. Otherwise, it is ignored. Reading from this register
while ADMA is active returns the current
counter value. Reading from it while ADMA is
inactive returns the preset value. The counter
decrements only if the AEH bit is set (automatic error handling activated).
AEH
The Automatic Error Handling bit has two different meanings, depending on the current
mode:
Non-Isochronous mode—This mode is
used for bulk, interrupt and control transfers. Setting AEH in this mode enables automatic handling of packets containing
CRC or bit-stuffing errors. If this bit is set
during transmit operations, the USB node
automatically reloads the FIFO and reschedules the packet to which the host did
not return an ACK. If this bit is clear, automatic error handling ceases. If this bit is
set during receive operations, a packet received with an error (as specified in the
DERR bit description in the DMAEV register) is automatically flushed from the FIFO
being used so that the packet can be received again. If this bit is cleared, automatic error handling ceases.
Isochronous mode—Setting this bit allows the USB node to ignore packets received with errors (as specified in the
DERR bit description in the DMAMSK register). If this bit is set during receive operations, the USB node is automatically
flushed and the receive FIFO is reset to
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15.3.21 Mirror Register (MIR)
STAT
The Status field mirrors the status bits of the
transmitter or receiver n selected by the
DSRC[2:0] field in the DMACNTRL register
(DMA need not be active or enabled). It corresponds to TXSn or RXSn, respectively.
15.3.22 DMA Count Register (DMACNT)
bs
The DMACNT register specifies a maximum count for
ADMA operations. The DMACNT register provides read/
write access. After reset this register is clear.
7
0
0
DSIZ DCNT DERR DSHLT
7
6
0
DCOUNT
The DMA Count field is decremented on completion of a DMA operation until it reaches 0.
Then the DCNT bit in the DMA Event register
is set, only when the next successful DMA operation is completed. This register does not
underflow. For receive operations, this count
decrements when the packet is received successfully, and then transferred to memory using DMA. For transmit operations, this count
decrements when the packet is transferred
from memory using DMA, and then transmitted successfully. Software loads DCOUNT
with (number of packets to transfer) - 1. If a
DMACNT write operation occurs simultaneously with the decrement operation, the
write takes precedence.
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15.3.25 Transmit Status 0 Register (TXS0)
The TXS0 register reports the transmit status of the mandatory Endpoint 0. It is loaded with 08h after reset. This register allows read-only access from the CPU bus.
15.3.24 Endpoint Control 0 Register (EPC0)
7
The EPC0 register controls the mandatory Endpoint 0. It is
clear after reset. Reserved bits read undefined data.
6
STALL
DEF
EP
4
3
Reserved
4
3
Res. ACK_STAT TX_DONE Res.
0
TCOUNT
0
TCOUNT
EP
The Endpoint Address field holds the 4-bit
endpoint address. For Endpoint 0, these bits
are hardwired to 0000b. Writing a 1 to any of
the EP bits is ignored.
The Default Address aids in the transition
from the default address to the assigned address. When set, the device responds to the
default address without regard to the contents
of FAR6-0/EP03-0 fields. When an IN packet
is transmitted for the endpoint, the DEF bit is
automatically cleared. This bit provides read/
write access from the CPU bus. After reset,
this bit is clear. The transition from the default
address 00000000000b to an address assigned during bus enumeration may not occur
in the middle of the SET_ADDRESS control
sequence. This is necessary to complete the
control sequence. However, the address must
change immediately after this sequence finishes in order to avoid errors when another
control sequence immediately follows the
SET_ADDRESS command. On USB reset,
software has 10 ms for set-up, and should
write 80h to the FAR register and 00h to the
EPC0
register.
On
receipt
of
a
SET_ADDRESS command, software must
write 40h to the EPC0 register and 80h to the
FAR register. It must then queue a zero length
IN packet to complete the status phase of the
SET_ADDRESS control sequence.
0 – Do not respond to the default address.
1 – Respond to default address.
The Stall bit can be used to enable STALL
handshakes under the following conditions:
The transmit FIFO is enabled and an IN
token is received.
The receive FIFO is enabled and an OUT
token is received.
A SETUP token does not cause a STALL
handshake to be generated when this bit is
set. After transmitting the STALL handshake,
the RX_LAST and the TX_DONE bits in the
respective Receive/Transmit Status registers
are set. This bit allows read/write access from
the CPU bus. After reset this bit is cleared.
0 – Disable STALL handshakes.
1 – Enable STALL handshakes.
TX_DONE
The Transmission Count field indicates the
number of empty bytes available in the FIFO.
This field is never larger than 8 for Endpoint 0.
The Transmission Done bit indicates whether
a packet has completed transmission. The
TX_DONE bit is cleared when this register is
read.
0 – No completion of packet transmission has
occurred.
1 – A packet has completed transmission.
The Acknowledge Status bit indicates the status, as received from the host, of the ACK for
the packet previously sent. This bit is to be interpreted when TX_DONE is set. It is set
when an ACK is received; otherwise, it remains cleared. This bit is cleared when this
register is read.
0 – No ACK received.
1 – ACK received.
ACK_STAT
15.3.26 Transmit Command 0 Register (TXC0)
The TXC0 register controls the mandatory Endpoint 0 when
used in transmit direction. This register allows read/write access from the CPU bus. It is clear after reset. Reading reserved bits returns undefined data.
7
STALL
5
Reserved
TX_EN
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5
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7
6
TOGGLE
81
4
3
2
1
0
IGN_IN FLUSH TOGGLE Res. TX_EN
The Transmission Enable bit enables data
transmission from the FIFO. It is cleared by
hardware after transmitting a single packet, or
a STALL handshake, in response to an IN token. It must be set by software to start packet
transmission. The RX_EN bit in the Receive
Command 0 (RXC0) register takes precedence over this bit; i.e. if the RX_EN bit is set,
the TX_EN bit is ignored until RX_EN is reset.
Zero length packets are indicated by setting
this bit without writing any data to the FIFO.
0 – Transmission from the FIFO disabled.
1 – Transmission from the FIFO enabled.
The Toggle bit specifies the PID used when
transmitting the packet. A value of 0 causes a
DATA0 PID to be generated, while a value of 1
causes a DATA1 PID to be generated. This bit
is not altered by the hardware.
0 – DATA0 PID is used.
1 – DATA1 PID is used.
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receive the next packet. The erroneous
packet is ignored and not transferred via
DMA. If this bit is cleared, automatic error
handling ceases.
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FLUSH
Writing a 1 to the Flush FIFO bit flushes all TOGGLE
The Toggle bit reports the PID used when redata from the control endpoint FIFOs, resets
ceiving the packet. When clear, this bit indithe endpoint to Idle state, clears the FIFO
cates that the last successfully received
read and write pointer, and then clears itself.
packet had a DATA0 PID. When set, this bit inIf the endpoint is currently using the FIFO0 to
dicates that the packet had a DATA1 PID. This
transfer data on USB, flushing is delayed until
bit is unchanged for zero-length packets. It is
after the transfer is complete. The FLUSH bit
cleared when this register is read.
is cleared on reset. It is equivalent to the
0 – DATA0 PID was used.
FLUSH bit in the RXC0 register.
1 – DATA1 PID was used.
0 – Writing 0 has no effect.
SETUP
The Setup bit indicates that the setup packet
1 – Writing 1 flushed the FIFOs.
has been received. This bit is unchanged for
IGN_IN
When the Ignore IN Tokens bit is set, the endzero-length packets. It is cleared when this
point will ignore any IN tokens directed to its
register is read.
configured address.
0 – Setup packet has not been received.
0 – Do not ignore IN tokens.
1 – Setup packet has been received.
1 – Ignore IN tokens.
15.3.29 Receive Command 0 Register (RXC0)
15.3.27 Transmit Data 0 Register (TXD0)
The RXC0 register controls the mandatory Endpoint 0 when
te
Data written to the TXD0 register is copied into the FIFO of used in receive direction. This register provides read/write
Endpoint 0 at the current location of the transmit write point- access from the CPU bus. It is clear after reset.
er. The register allows write-only access from the CPU bus.
7
7
0
4
Reserved
RX_EN
2
1
0
FLUSH IGN_SETUP IGN_OUT RX_EN
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The Receive Enable bit enables receiving
packets. OUT packet reception is disabled after every data packet is received, or when a
STALL handshake is returned in response to
an OUT token. The RX_EN bit must be set to
re-enable data reception. Reception of SET15.3.28 Receive Status 0 Register (RXS0)
UP packets is always enabled. In the case of
The RXS0 register indicates status conditions for the bidiback-to-back SETUP packets (for a given
rectional Control Endpoint 0. To receive a SETUP packet afendpoint) where a valid SETUP packet is reter receiving a zero length OUT/SETUP packet, there are
ceived with no other intervening non-SETUP
two copies of this register in hardware. One holds the retokens, the Endpoint Controller discards the
ceive status of a zero length packet, and another holds the
new SETUP packet and returns an ACK handstatus of the next SETUP packet with data. If a zero length
shake. If any other reasons prevent the Endpacket is followed by a SETUP packet, the first read of this
point Controller from accepting the SETUP
register indicates the status of the zero length packet (with
packet, it must not generate a handshake.
RX_LAST set and RCOUNT clear), and the second read inThis allows recovery from a condition where
dicates the status of the SETUP packet. This register prothe ACK of the first SETUP token was lost by
vides read-only access from the CPU bus. After reset it is
the host.
clear.
0 – Receive disabled.
1 – Receive enabled.
IGN_OUT
The Ignore OUT Tokens bit controls whether
7
6
5
4
3
0
OUT tokens are ignored. When this bit is set,
Res. SETUP TOGGLE RX_LAST
RCOUNT
the endpoint ignores any OUT tokens directed
to its configured address.
0 – Do not ignore OUT tokens.
RCOUNT
The Receive Count field reports the number of
1 – Ignore OUT tokens.
bytes presently in the RX FIFO. This number IGN_SETUP The Ignore SETUP Tokens bit controls whethis never larger than 8 for Endpoint 0.
er SETUP tokens are ignored. When this bit is
RX_LAST
The Receive Last Bytes bit indicates that an
set, the endpoint ignores any SETUP tokens
ACK was sent on completion of a successful
directed to its configured address.
receive operation. This bit is unchanged for
0 – Do not ignore SETUP tokens.
zero-length packets. It is cleared when this
1 – Ignore SETUP tokens.
register is read.
0 – No ACK was sent.
1 – An ACK was sent.
The Transmit FIFO Data Byte is used to load
the transmit FIFO. Software is expected to
write only the packet payload data. The PID
and CRC16 are created automatically.
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Writing 1 to the Flush bit flushes all data from
the control endpoint FIFOs, resets the endpoint to Idle state, clears the FIFO read and
write pointer, and then clears itself. If the endpoint is currently using FIFO0 to transfer data
on USB, flushing is delayed until after the
transfer is done. This bit is cleared on reset.
This bit is equivalent to FLUSH in the TXC0
register.
0 – Writing 0 has no effect.
1 – Writing 1 flushes the FIFOs.
ISO
STALL
15.3.30 Receive Data 0 Register (RXD0)
7
0
RXFD7:0
te
Reading the RXD0 register returns the data located at the
current position of the receive read pointer of the Endpoint
0 FIFO. The register allows read-only access from the CPU
bus. After reset, reading this register returns undefined data.
When the Isochronous bit is set, the endpoint
is isochronous. This implies that no NAK is
sent if the endpoint is not ready but enabled;
i.e. if an IN token is received and no data is
available in the FIFO to transmit, or if an OUT
token is received and the FIFO is full since
there is no USB handshake for isochronous
transfers.
0 – Isochronous mode disabled.
1 – Isochronous mode enabled.
The Stall bit can be used to enable STALL
handshakes under the following conditions:
The transmit FIFO is enabled and an IN
token is received.
The receive FIFO is enabled and an OUT
token is received.
A SETUP token does not cause a STALL
handshake to be generated when this bit is
set.
0 – Disable STALL handshakes.
1 – Enable STALL handshakes.
15.3.32 Transmit Status Register n (TXSn)
Each of the three transmit endpoints has a TXSn register.
The Receive FIFO Data Byte is used to un- The format of the TXSn registers is given below. The regisload the FIFO. Software should expect to read ters provide read-only access from the CPU bus. They are
only the packet payload data. The PID and loaded with 1Fh at reset.
CRC16 are removed from the incoming data
stream automatically.
7
6
5
4
0
15.3.31 Endpoint Control Register n (EPCn)
TX_URUN ACK_STAT TX_DONE
TCOUNT
Each unidirectional endpoint has an EPCn register. The format of the EPCn registers is defined below. These registers
provide read/write access from the CPU bus. After reset, the TCOUNT
The Transmission Count field reports the
EPCn registers are clear.
number of empty bytes available in the FIFO.
If this number is greater than 31, a value of 31
is reported.
7
6
5
4
3
0
TX_DONE When set, the Transmission Done bit indiSTALL Res. ISO EP_EN
EP
cates that the endpoint responded to a USB
packet. Three conditions can cause this bit to
be set:
EP
The Endpoint Address field holds the end A data packet completed transmission in
point address.
response to an IN token with non-ISO opEP_EN
When the Endpoint Enable bit is set, the
eration.
EP[3:0] field is used in address comparison,
The endpoint sent a STALL handshake in
together with the AD[6:0] field in the FAR regresponse to an IN token.
ister. When clear, the endpoint does not re A scheduled ISO frame was transmitted or
spond to any token on the USB bus. (The
discarded.
AD_EN bit in the FAR register is the global adThis bit is cleared when this register is read.
dress compare enable for the USB node. If it
is clear, the device does not respond to any
address, without regard to the EP_EN state.)
0 – Address comparison is disabled.
1 – If the AD_EN bit is also set, address comparison is enabled.
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FLUSH
15.3.33 Transmit Command Register n (TXCn)
Each of the transmit endpoints (1, 3, and 5) has a Transmit
Command Register, TXCn. These registers provide read/
write access from the CPU bus. After reset the registers are
clear.
6 5
4
3
2
1
0
bs
7
IGN_ISOMSK TFWL RFF FLUSH TOGGLE LAST TX_EN
FLUSH
The Transmission Enable bit enables data
transmission from the FIFO. It is cleared by
hardware after transmitting a single packet or
after a STALL handshake in response to an IN
token. It must be set by software to start packet transmission.
0 – Transmission disabled.
1 – Transmission enabled.
RFF
O
TX_EN
The Last Byte bit indicates whether the entire
packet has been written into the FIFO. This is
used especially for streaming data to the FIFO
while the actual transmission occurs. If the
LAST bit is not set and the transmit FIFO becomes empty during a transmission, a stuff error followed by an EOP is forced on the bus.
Zero length packets are indicated by setting
this bit without writing any data to the FIFO.
The transmit state machine transmits the payload data, CRC16, and the EOP signal before
clearing this bit.
0 – Last byte of the packet has not been written to the FIFO.
1 – Last byte of the packet has been written to
the FIFO.
The function of the Toggle bit differs depending on whether ISO or non-ISO operation is
used (as selected by the ISO bit in the EPCn
register).
Non-Isochronous mode—The TOGGLE
bit specifies the PID used when transmitting the packet. A value of 0 causes a
DATA0 PID to be generated, while a value
of 1 causes a DATA1 PID to be generated.
Isochronous mode—The TOGGLE bit
and the LSB of the frame counter (FNL0)
act as a mask for the TX_EN bit to allow
pre-queueing of packets to specific frame
numbers. (I.e. transmission is enabled
only if bit 0 in the FNL register is set to
TOGGLE.) If an IN token is not received
while this condition is true, the contents of
the FIFO are flushed with the next SOF. If
the endpoint is set to ISO, data is always
transferred with a DATA0 PID.
This bit is not altered by hardware.
Writing 1 to the Flush bit flushes all data from
the corresponding transmit FIFO, resets the
endpoint to Idle state, and clears both the
FIFO read and write pointers. If the MAC is
currently using the FIFO to transmit, data is
flushed after the transmission is complete. After data flushing, this bit is cleared by hardware.
0 – Writing 0 has no effect.
1 – Writing 1 flushes the FIFO.
The Refill FIFO bit is used to repeat a transmission for which no ACK was received. Setting the LAST bit to 1 automatically saves the
Transmit Read Pointer (TXRP) to a buffer.
When the RFF bit is set, the buffered TXRP is
reloaded into the TXRP. This allows software
to repeat the last transaction if no ACK was received from the host. If the MAC is currently
using the FIFO to transmit, TXRP is reloaded
only after the transmission is complete. After
reload, this bit is cleared by hardware.
0 – No action.
1 – Reload the saved TXRP.
te
TX_URUN
The Acknowledge Status bit is valid when the LAST
TX_DONE bit is set. The meaning of the
ACK_STAT bit differs depending on whether
ISO or non-ISO operation is used (as selected
by the ISO bit in the EPCn register).
Non-Isochronous mode—This bit indicates the acknowledge status (from the
host) about the ACK for the previously
sent packet. This bit itself is set when an
ACK is received; otherwise, it is clear.
Isochronous mode—This bit is set if a
frame number LSB match occurs (see
Section 15.3.33), and data was sent in response to an IN token. Otherwise, this bit
is cleared, the FIFO is flushed, and
TX_DONE is set.
The ACK_STAT bit is cleared when this regis- TOGGLE
ter is read.
The Transmit FIFO Underrun indicates whether the transmit FIFO became empty during a
transmission, and no new data was written to
the FIFO. If so, the Media Access Controller
(MAC) forces a bit stuff error followed by an
EOP. This bit is cleared when this register is
read.
0 – No transmit FIFO underrun event occurred.
1 – Transmit FIFO underrun event occurred.
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The Transmit FIFO Warning Limit bits specify
how many more bytes can be transmitted from
the respective FIFO before an underrun condition occurs. If the number of bytes remaining
in the FIFO is equal to or less than the selected warning limit, the TXWARN bit in the
FWEV register is set. To avoid interrupts
caused by setting this bit while the FIFO is being filled before a transmission begins, TXWARN is only set when transmission from the
endpoint is enabled (TX_ENn in the TXCn
register is set). See Table 37.
15.3.35 Receive Status Register n (RXSn)
Each receive endpoint pipe (2, 4, and 6) has one RXSn register with the bits defined below. To allow a SETUP packet
to be received after a zero length OUT packet is received,
hardware contains two copies of this register. One holds the
receive status of a zero length packet, and another holds the
status of the next SETUP packet with data. If a zero length
packet is followed by a SETUP packet, the first read of this
register indicates the zero-length packet status, and the
second read, the SETUP packet status. This register provides read-only access from the CPU bus. After reset it is
clear.
Table 37 Transmit FIFO Warning Limit
TFWL
Bytes Remaining in FIFO
00
TFWL disabled
01
≤4
10
≤8
11
≤ 16
7
6
5
4
3
RX_ERR SETUP TOGGLE RX_LAST
RCOUNT
The Receive Counter holds the number of
bytes presently in the endpoint receive FIFO.
If this number is greater than 15, a value of 15
is actually reported.
The Receive Last Bytes bit indicates that an
ACK was sent on completion of a successful
receive operation. This bit is cleared when this
register is read.
0 – No ACK was sent.
1 – An ACK was sent.
The function of the Toggle bit differs depending on whether ISO or non-ISO operation is
used (as controlled by the ISO bit in the EPCn
register).
Non-Isochronous mode—A value of 0 indicates that the last successfully received
packet had a DATA0 PID, while a value of
1 indicates that this packet had a DATA1
PID.
Non-Isochronous mode—This bit reflects
the LSB of the frame number (FNL0) after
a packet was successfully received for this
endpoint.
This bit is cleared by reading the RXSn register.
The Setup bit indicates that the setup packet
has been received. This bit is cleared when
this register is read.
0 – Setup packet has not been received.
1 – Setup packet has been received.
The Receive Error indicates a media error,
such as bit-stuffing or CRC. If this bit is set,
software must flush the respective FIFO.
0 – No receive error occurred.
1 – Receive error occurred.
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RCOUNT
0
RX_LAST
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IGN_ISOMSK The Ignore ISO Mask bit has an effect only if
the endpoint is set to be isochronous. If set,
this bit disables locking of specific frame numbers with the alternate function of the TOGGLE bit. Therefore, data is transmitted upon TOGGLE
reception of the next IN token. If clear, data is
only transmitted when FNL0 matches TOGGLE. This bit is cleared after reset.
0 – Data transmitted only when FNL0 matches TOGGLE.
1 – Locking of frame numbers disabled.
15.3.34 Transmit Data Register n (TXDn)
Each transmit FIFO has one TXDn register. Data written to
the TXDn register is loaded into the transmit FIFO n at the
current location of the transmit write pointer. The TXDn registers provide write-only access from the CPU bus.
0
O
7
TXFD
TXFD
SETUP
The Transmit FIFO Data Byte is used to load
the transmit FIFO. Software is expected to RX_ERR
write only the packet payload data. The PID
and CRC16 are inserted automatically in the
transmit data stream.
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CP3UB17
TFWL
CP3UB17
15.3.36 Receive Command Register n (RXCn)
15.3.37 Receive Data Register n (RXD)
Each of the receive endpoints (2, 4, and 6) has one RXCn
register. The registers provide read/write access from the
CPU bus. Reading reserved bits returns undefined data. After reset, it is clear.
Each of the three Receive Endpoint FIFOs has one RXD
register. Reading the Receive Data register n returns the
data located in the receive FIFO n at the current position of
the receive read pointer. These registers provide read-only
access from the CPU bus.
7
6
5
4
3
2
1
0
7
Res. RFWL Res. FLUSH IGN_SETUP Res. RX_EN
0
RXFD
RX_EN
RXFD
TRANSCEIVER INTERFACE
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15.4
The Receive FIFO Data Byte is used to read
the receive FIFO. Software should expect to
read only the packet payload data. The PID
and CRC16 are terminated by the receive
state machine.
Separate UVCC and UGND pins are provided for the USB
transceiver, so it can be powered at the standard USB voltage of 3.3V while the other parts of the device run at other
voltages. The USB transceiver is powered by the system,
not the USB cable, so these pins must be connected to a
power supply and the system ground.
O
bs
ol
e
The Receive Enable bit enables receiving
packets. OUT packet reception is disabled after every data packet is received, or when a
STALL handshake is returned in response to
an OUT token. The RX_EN bit must be set to
re-enable data reception. Reception of SETUP packets is always enabled. In the case of
back-to-back SETUP packets (for a given
endpoint) where a valid SETUP packet is received with no other intervening non-SETUP
tokens, the Endpoint Controller discards the
new SETUP packet and returns an ACK handshake. If any other reasons prevent the Endpoint Controller from accepting the SETUP
packet, it must not generate a handshake.
0 – Receive disabled.
1 – Receive enabled.
IGN_SETUP The Ignore SETUP Tokens bit controls whether SETUP tokens are ignored. When this bit is
set, the endpoint ignores any SETUP tokens
directed to its configured address.
0 – Do not ignore SETUP tokens.
1 – Ignore SETUP tokens.
FLUSH
Writing 1 to the Flush bit flushes all data from
the corresponding receive FIFO, resets the
endpoint to Idle state, and clears the FIFO
read and write pointers. If the endpoint is currently using FIFO to receive data, flushing is
delayed until after the transfer is complete.
0 – Writing 0 has no effect.
1 – Writing 1 flushes the FIFOs.
RFWL
The Receive FIFO Warning Limit field specifies how many more bytes can be received to
the respective FIFO before an overrun condition occurs. If the number of empty bytes remaining in the FIFO is equal to or less than
the selected warning limit, the RXWARN bit in
the FWEV register is set.
Table 38 Receive FIFO Warning Limit
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RFWL
Bytes Remaining in FIFO
00
RFWL disabled
01
≤4
10
≤8
11
≤ 16
86
The on-chip USB transceiver does not have enough impedance to meet the USB specification requirement, so external 22-ohm resistors are required in series with the D+ and
D- pins, as shown in Figure 16.
UVCC
+3.3V
22
D+
CP3UB17
22
D-
USB
Cable
UGND
DS150
Figure 16. USB Transceiver Interface
The Advanced Audio Interface (AAI) provides a serial synchronous, full duplex interface to codecs and similar serial
devices. The transmit and receive paths may operate asynchronously with respect to each other. Each path uses a 3wire interface consisting of a bit clock, a frame synchronization signal, and a data signal.
16.1.3
Serial Transmit Frame Sync (SFS)
The SFS pin is a bidirectional signal which provides frame
synchronization. In asynchronous mode, this signal is used
as frame sync only by the transmitter. In synchronous mode,
this signal is used as frame sync by both the transmitter and
receiver. The frame sync signal may be generated internally,
or it may be provided by an external source.
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e
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The CPU interface can be either interrupt-driven or DMA. If
the interface is configured for interrupt-driven I/O, data is
16.1.4 Serial Receive Data (SRD)
buffered in the receive and transmit FIFOs. If the interface is
The SRD pin is used as an input when data is shifted into
configured for DMA, the data is buffered in registers.
the Audio Receive Shift Register (ARSR). In asynchronous
The AAI is functionally similar to a MotorolaTM Synchronous
mode, data on the SRD pin is sampled on the negative edge
Serial Interface (SSI). Compared to a standard SSI impleof the serial receive shift clock (SRCLK). In synchronous
mentation, the AAI interface does not support the so-called
mode, data on the SRD pin is sampled on the negative edge
“On-demand Mode”. It also does not allow gating of the shift
of the serial shift clock (SCK). The data is shifted into ARSR
clocks, so the receive and transmit shift clocks are always
with the most significant bit (MSB) first.
active while the AAI is enabled. The AAI also does not support 12- and 24-bit data word length or more than 4 slots 16.1.5 Serial Receive Clock (SRCLK)
(words) per frame. The reduction of supported modes is acThe SRCLK pin is a bidirectional signal that provides the receptable, because the main purpose of the AAI is to connect
ceive serial shift clock in asynchronous mode. In this mode,
to audio codecs, rather than to other processors (DSPs).
data is sampled on the negative edge of SRCLK. The SRThe implementation of a FIFO as a 16-word receive and CLK signal may be generated internally or it may be providtransmit buffer is an additional feature, which simplifies ed by an external clock source. In synchronous mode, the
communication and reduces interrupt load. Independent SCK pin is used as shift clock for both the receiver and
DMA is provided for each of the four supported audio chan- transmitter, so the SRCLK pin is available for use as a gennels (slots). The AAI also provides special features and op- eral-purpose port pin or an auxiliary frame sync signal to acerating modes to simplify gain control in an external codec cess multiple slave devices (e.g. codecs) within a network
and to connect to an ISDN controller through an IOM-2 (see Network mode).
compatible interface.
16.1.6 Serial Receive Frame Sync (SRFS)
16.1
AUDIO INTERFACE SIGNALS
16.1.1
Serial Transmit Data (STD)
O
bs
The STD pin is used to transmit data from the serial transmit
shift register (ATSR). The STD pin is an output when data is
being transmitted and is in high-impedance mode when no
data is being transmitted. The data on the STD pin changes
on the positive edge of the transmit shift clock (SCK). The
STD pin goes into high-impedance mode on the negative
edge of SCK of the last bit of the data word to be transmitted, assuming no other data word follows immediately. If another data word follows immediately, the STD pin will not
change to the high-impedance mode, instead remaining active. The data is shifted out with the most significant bit
(MSB) first.
16.1.2
Serial Transmit Clock (SCK)
The SCK pin is a bidirectional signal that provides the serial
shift clock. In asynchronous mode, this clock is used only by
the transmitter to shift out data on the positive edge. The serial shift clock may be generated internally or it may be provided by an external clock source. In synchronous mode,
the SCK pin is used by both the transmitter and the receiver.
Data is shifted out from the STD pin on the positive edge,
and data is sampled on the SRD pin on the negative edge
of SCK.
The SRFS pin is a bidirectional signal that provides frame
synchronization for the receiver in asynchronous mode. The
frame sync signal may be generated internally, or it may be
provided by an external source. In synchronous mode, the
SFS signal is used as the frame sync signal for both the
transmitter and receiver, so the SRFS pin is available for use
as a general-purpose port pin or an auxiliary frame sync signal to access multiple slave devices (e.g. codecs) within a
network (see Network mode).
16.2
AUDIO INTERFACE MODES
There are two clocking modes: asynchronous mode and
synchronous mode. These modes differ in the source and
timing of the clock signals used to transfer data. When the
AAI is generating the bit shift clock and frame sync signals
internally, synchronous mode must be used. In asynchronous mode, an external frame sync signal must be used.
There are two framing modes: normal mode and network
mode. In normal mode, one word is transferred per frame.
In network mode, up to four words are transferred per frame.
A word may be 8 or 16 bits. The part of the frame which carries a word is called a slot. Network mode supports multiple
external devices sharing the interface, in which each device
is assigned its own slot. Separate frame sync signals are
provided, so that each device is triggered to send or receive
its data during its assigned slot.
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CP3UB17
16.0 Advanced Audio Interface
CP3UB17
16.2.1
Asynchronous Mode
IRQ Support
In asynchronous mode, the receive and transmit paths of
the audio interface operate independently, with each path
using its own bit clock and frame sync signal. Independent
clocks for receive and transmit are only used when the bit
clock and frame sync signal are supplied externally. If the bit
clock and frame sync signals are generated internally, both
paths derive their clocks from the same set of clock prescalers.
16.2.2
If the receiver interface is configured for interrupt-driven I/O
(RXDSA0 = 0), all received data are loaded into the receive
FIFO. An IRQ is asserted as soon as the number of data
bytes or words in the receive FIFO is greater than a programmable warning limit.
If the transmitter interface is configured for interrupt-driven
I/O (TXDSA0 = 0), all data to be transmitted is read from the
transmit FIFO. An IRQ is asserted as soon as the number
data bytes or words available in the transmit FIFO is equal
or less than a programmable warning limit.
Synchronous Mode
In synchronous mode, the receive and transmit paths of the
audio interface use the same shift clock and frame sync signal. The bit shift clock and frame sync signal for both paths
are derived from the same set of clock prescalers.
DMA Support
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If the receiver interface is configured for DMA (RXDSA0 =
1), received data is transferred from the ARSR into the DMA
receive buffer 0 (ARDR0). A DMA request is asserted when
16.2.3 Normal Mode
the ARDR0 register is full. If the transmitter interface is conIn normal mode, each rising edge on the frame sync signal
figured for DMA (TXDSA0 = 1), data to be transmitted are
marks the beginning of a new frame and also the beginning
read from the DMA transmit buffer 0 (ATDR0). A DMA reof a new slot. A slot does not necessarily occupy the entire
quest is asserted to the DMA controller when the ATDR0
frame. (A frame can be longer than the data word transmitregister is empty.
ted after the frame sync pulse.) Typically, a codec starts
transmitting a fixed length data word (e.g. 8-bit log PCM da- Figure 18 shows the data flow for IRQ and DMA mode in
ta) with the frame sync signal, then the codec’s transmit pin normal Mode.
returns to the high-impedance state for the remainder of the
DMA
frame.
SRD
The Audio Receive Shift Register (ARSR) de-serializes received on the SRD pin (serial receiver data). Only the data
sampled after the frame sync signal are treated as valid. If
the interface is interrupt-driven, valid data bits are transferred from the ARSR to the receive FIFO. If the interface is
configured for DMA, the data is transferred to the receive
DMA register 0 (ARDR0).
bs
The serial transmit data (STD) pin is only an active output
while data is shifted out. After the defined number of data
bits have been shifted out, the STD pin returns to the highimpedance state.
O
For operation in normal mode, the Slot Count Select bits
(SCS[1:0]) in the Global Configuration register (AGCR)
must be loaded with 00b (one slot per frame). In addition,
the Slot Assignment bits for receive and transmit must be
programmed to select slot 0.
If the interface is configured for DMA, the DMA slot assignment bits must also be programmed to select slot 0. In this
case, the audio data is transferred to or from the receive or
transmit DMA register 0 (ARDR0/ATDR0).
Figure 17 shows the frame timing while operating in normal
mode with a long frame sync interval.
Long Frame Sync
(SFS/SRFS)
Shift Data
(STD/SRD)
Data
High-impedance
Data
Frame
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ARDR 0
=1
A
DS
TX
DMA Slot
Assignment
TXDSA = 0
RX
FIFO
DMA
Request 0
STD
ATSR
DMA Slot
Assignment
IRQ
SA
=1
ATDR 0
D
RX
RXDSA = 0
TX
FIFO
IRQ
DS054
Figure 18. IRQ/DMA Support in Normal Mode
Network Mode
In network mode, each frame is composed of multiple slots.
Each slot may transfer 8 or 16 bits. All of the slots in a frame
must have the same length. In network mode, the sync signal marks the beginning of a new frame. Only frames with
up to four slots are supported by this audio interface.
More than two devices can communicate within a network
using the same clock and data lines. The devices connected
to the same bus use a time-multiplexed approach to share
access to the bus. Each device has certain slots assigned
to it, in which only that device is allowed to transfer data.
One master device provides the bit clock and the frame sync
signal(s). On all other (slave) devices, the bit clock and
frame sync pins are inputs.
Up to four slots can be assigned to the interface, as it supports up to four slots per frame. Any other slots within the
frame are reserved for other devices.
DS053
Figure 17.
Request 1
ARSR
Normal Mode Frame
88
DMA Support
On the receiver side, only the valid data bits which were received during the slots assigned to this interface are copied
into the receive FIFO or DMA registers. The assignment of
slots to the receiver is specified by the Receive Slot Assignment bits (RXSA) in the ATCR register. It can also be specified whether the received data is copied into the receive
FIFO or into the corresponding DMA receive register. There
is one DMA receive register (ARDRn) for each of the maximum four data slots. Each slot may be configured individually.
Figure 20 illustrates the data flow for IRQ and DMA support
in network mode, using four slots per frame and DMA support enabled for slots 0 and 1 in receive and transmit direction.
Long Frame Sync
(SFS/SRFS)
Shift Data
(STD/SRD)
Data
(ignored)
Slot0
Data
(valid)
Slot1
If DMA is enabled for a transmit slot n (TXDSAn = 1), all data
to be transmitted in slot n are read from the corresponding
DMA transmit register (ATDRn). A DMA request is asserted
to the DMA controller when the ATDRn register is empty.
te
ARDR 0
ta
SRD
High-impedance
ARDR 1
DMA
Request 1
DMA
Request 3
Sl
ot
0
da
ARSR
ata
1d
ot
Sl
DMA Slot
Assignment
Sl
ot
ARDR 2
ARDR 3
2
an
ol
e
Figure 19 shows the frame timing while operating in network
mode with four slots per frame, slot 1 assigned to the interface, and a long frame sync interval.
If DMA support is enabled for a receive slot n (RXDSA0 =
1), all data received in this slot is only transferred from the
ARSR into the corresponding DMA receive register
(ARDRn). A DMA request is asserted when the ARDRn register is full.
d
3
da
ta
RX
FIFO
Data
(ignored)
ATDR 0
Unused Slots
ta
STD
da
ATSR
0
ATDR 1
DMA
Request 0
DMA
Request 2
Sl
ot
Frame
IRQ
bs
DS055
Figure 19.
ot
O
If DMA is not enabled for a transmit slot n (TXDSAn = 0), all
data to be transmitted in this slot are read from the transmit
FIFO. An IRQ is asserted as soon as the number data bytes
or words available in the transmit FIFO is equal or less than
a configured warning limit.
2
an
d
If DMA is not enabled for a receive slot n (RXDSAn = 0), all
data received in this slot is loaded into the receive FIFO. An
IRQ is asserted as soon as the number of data bytes or
words in the receive FIFO is greater than a configured warning limit.
ATDR 2
ATDR 3
Sl
IRQ Support
1d
S
DMA Slot
Assignment
Network Mode Frame
ata
lot
3
da
ta
TX
FIFO
IRQ
DS056
Figure 20. IRQ/DMA Support in Network Mode
If the interface operates in synchronous mode, the receiver
uses the transmit bit clock (SCK) and transmit frame sync
signal (SFS). This allows the pins used for the receive bit
clock (SRCLK) and receive frame sync (SRFS) to be used
as additional frame sync signals in network mode. The extra
frame sync signals are useful when the audio interface communicates to more than one codec, because codecs typically start transmission immediately after the frame sync pulse.
The SRCLK pin is driven with a frame sync pulse at the beginning of the second slot (slot 1), and the SRFS pin is driven with a frame sync pulse at the beginning of slot 2.
Figure 21 shows a frame timing diagram for this configuration, using the additional frame sync signals on SRCLK and
SRFS to address up to three devices.
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CP3UB17
The transmitter only drives data on the STD pin during slots
which have been assigned to this interface. During all other
slots, the STD output is in high-impedance mode, and data
can be driven by other devices. The assignment of slots to
the transmitter is specified by the Transmit Slot Assignment
bits (TXSA) in the ATCR register. It can also be specified
whether the data to be transmitted is transferred from the
transmit FIFO or the corresponding DMA transmit register.
There is one DMA transmit register (ATDRn) for each of the
maximum four data slots. Each slot can be configured independently.
CP3UB17
The ideal required prescaler value Pideal can be calculated
as follows:
Pideal = fAudio In / fbit = 12 MHz / 256 kHz = 46.875
SFS
Therefore, the real prescaler value is 47. This results in a bit
clock error equal to:
SRCLK
(auxiliary
frame sync)
fbit_error = (fbit - fAudio In/Preal) / fbit × 100
= (256 kHz - 12 MHz/47) / 256 kHz × 100 = 0.27%
SRFS
(auxiliary
frame sync)
16.4
Data from/to Data from/to Data from/to
Codec 1
Codec 2
Codec 3
STD/SRD
Slot 0
Slot 1
Slot 2
Slot 3
Frame
DS057
16.3
Accessing Three Devices in Network Mode
BIT CLOCK GENERATION
In addition, software can specify the length of a long frame
sync signal. A long frame sync signal can be either 6, 13,
14, 15, or 16 bits long, depending on the external codec being used. The frame sync length can be configured by the
Frame Sync Length field (FSL) in the AGCR register.
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An 8-bit prescaler is provided to divide the audio interface
input clock down to the required bit clock rate. Software can
choose between two input clock sources, a primary and a
secondary clock source.
The clock for the frame synchronization signals is derived
from the bit clock of the audio interface. A 7-bit prescaler is
used to divide the bit clock to generate the frame sync clock
for the receive and transmit operations. The bit clock is divided by FCPRS + 1. In other words, the value software
must write into the ACCR.FCPRS field is equal to the bit
number per frame minus one. The frame may be longer than
the valid data word but it must be equal to or larger than the
8- or 16-bit word. Even if 13-, 14-, or 15-bit data is being
used, the frame width must always be at least 16 bits wide.
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Figure 21.
FRAME CLOCK GENERATION
bs
On the CP3UB17, the two optional input clock sources are
the 12-MHz Aux1 clock and the 48-MHz PLL output clock 16.5
AUDIO INTERFACE OPERATION
(also used by the USB node). The input clock is divided by
the value of the prescaler BCPRS[7:0] + 1 to generate the 16.5.1 Clock Configuration
bit clock.
The Aux1 clock (generated by the Clock module described
The bit clock rate fbit can be calculated by the following in Section 11.8) must be configured, because it is the time
base for the AAI module. Software must write an appropriequation:
ate divisor to the ACDIV1 field of the PRSAC register to profbit = n × fSample × Data Length
vide a 12 MHz input clock. Software also must enable the
Aux1 clock by setting the ACE1 bit in the CRCTRL register.
n = Number of Slots per Frame
For example:
= Sample Frequency in Hz
f
Sample
Data Length = Length of data word in multiples of 8 bits
The ideal required prescaler value Pideal can be calculated
as follows:
PRSAC &= 0xF0;
// Set Aux1 prescaler to 1 (F = 12 MHz)
CRCTRL |= ACE1; // Enable Aux1 clk
O
Pideal = fAudio In / fbit
16.5.2 Interrupts
The real prescaler must be set to an integer value, which The interrupt logic of the AAI combines up to four interrupt
should be as close as possible to the ideal prescaler value, sources and generates one interrupt request signal to the
to minimize the bit clock error, fbit_error.
Interrupt Control Unit (ICU).
fbit_error [%] = (fbit - fAudio In/Preal) / fbit × 100
The four interrupt sources are:
Example:
The audio interface is used to transfer 13-bit linear PCM
data for one audio channel at a sample rate of 8k samples
per second. The input clock of the audio interface is 12 MHz.
Furthermore, the codec requires a minimum bit clock of 256
kHz to operate properly. Therefore, the number of slots per
frame must be set to 2 (network mode) although actually
only one slot (slot 0) is used. The codec and the audio interface will put their data transmit pins in TRI-STATE mode after the PCM data word has been transferred. The required
bit clock rate fbit can be calculated by the following equation:
fbit = n × fSample × Data Length = 2 × 8 kHz × 16 = 256 kHz
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RX FIFO Overrun - ASCR.RXEIP = 1
RX FIFO Almost Full (Warning Level) - ASCR.RXIP = 1
TX FIFO Under run - ASCR.TXEIP = 1
TX FIFO Almost Empty (Warning Level) - ASCR.TXIP=1
In addition to the dedicated input to the ICU for handling
these interrupt sources, the Serial Frame Sync (SFS) signal
is an input to the MIWU (see Section 13.0), which can be
programmed to generate edge-triggered interrupts.
from the FIFO to ATSR is performed (while the FIFO is already empty), a transmit FIFO underrun occurs. In this
event, the read pointer (TRP) will be decremented by 1 (incremented by 15) and the previous data word will be transmitted again. A transmit FIFO underrun is indicated by the
TXU bit in the Audio Interface Transmit Status and Control
Register (ATSCR). Also, no transmit interrupt will be generated (even if enabled).
RXIE
RXIP = 1
RXEIE
When the TRP is equal to the TWP and the last access to
the FIFO was a write operation (to the ATFR), the FIFO is
full. If an additional write to ATFR is performed, a transmit
FIFO overrun occurs. This error condition is not prevented
by hardware. Software must ensure that no transmit overrun
occurs.
AAI
Interrupt
RXEIP = 1
TXIE
TXIP = 1
The transmit frame synchronization pulse on the SFS pin
and the transmit shift clock on the SCK pin may be generated internally, or they can be supplied by an external source.
TXEIE
TXEIP = 1
At the receiver, the received data on the SRD pin is shifted
into ARSR on the negative edge of SRCLK (or SCK in synchronous mode), following the receive frame sync pulse,
SRFS (or SFS in synchronous mode).
Figure 22. AAI Interrupt Structure
16.5.3
Normal Mode
Transmit
DMA Operation
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In normal mode, each frame sync signal marks the beginning of a new frame and also the beginning of a new slot,
since each frame only consists of one slot. All 16 receive
and transmit FIFO locations hold data for the same (and
only) slot of a frame. If 8-bit data are transferred, only the
low byte of each 16-bit FIFO location holds valid data.
16.5.4
Receive
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16.5.5
DS155
bs
Once the interface has been enabled, transmit transfers are
initiated automatically at the beginning of every frame. The
beginning of a new frame is identified by a frame sync pulse.
Following the frame sync pulse, the data is shifted out from
the ATSR to the STD pin on the positive edge of the transmit
data shift clock (SCK).
When a complete data word has been received through the
SRD pin, the new data word is copied to the receive DMA
register 0 (ARDR0). A DMA request is asserted when the
ARDR0 register is full. If a new data word is received while
the ARDR0 register is still full, the ARDR0 register will be
overwritten with the new data.
FIFO Operation
When a complete word has been received, it is transferred
to the receive FIFO at the current location of the Receive
FIFO Write Pointer (RWP). Then, the RWP is automatically
incremented by 1.
A read from the Audio Receive FIFO Register (ARFR) results in a read from the receive FIFO at the current location
When a complete data word has been transmitted through of the Receive FIFO Read Pointer (RRP). After every read
the STD pin, a new data word is reloaded from the transmit operation from the receive FIFO, the RRP is automatically
DMA register 0 (ATDR0). A DMA request is asserted when incremented by 1.
the ATDR0 register is empty. If a new data word must be
When the RRP is equal to the RWP and the last access to
transmitted while the ATDR0 register is still empty, the prethe FIFO was a copy operation from the ARFR, the receive
vious data will be re-transmitted.
FIFO is full. When a new complete data word has been shifted into ARSR while the receive FIFO was already full, the
FIFO Operation
shift register overruns. In this case, the new data in the
When a complete data word has been transmitted through
ARSR will not be copied into the FIFO and the RWP will not
the STD pin, a new data word is loaded from the transmit
be incremented. A receive FIFO overrun is indicated by the
FIFO from the current location of the Transmit FIFO Read
RXO bit in the Audio Interface Receive Status and Control
Pointer (TRP). After that, the TRP is automatically increRegister (ARSCR). No receive interrupt will be generated
mented by 1.
(even if enabled).
A write to the Audio Transmit FIFO Register (ATFR) results
When the RWP is equal to the TWP and the last access to
in a write to the transmit FIFO at the current location of the
the receive FIFO was a read from the ARFR, a receive FIFO
Transmit FIFO Write Pointer (TWP). After every write operunderrun has occurred. This error condition is not prevented
ation to the transmit FIFO, TWP is automatically incrementby hardware. Software must ensure that no receive undered by 1.
run occurs.
When the TRP is equal to the TWP and the last access to
The receive frame synchronization pulse on the SRFS pin
the FIFO was a read operation (a transfer to the ATSR), the
(or SFS in synchronous mode) and the receive shift clock on
transmit FIFO is empty. When an additional read operation
the SRCLK (or SCK in synchronous mode) may be gener-
O
DMA Operation
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CP3UB17
Figure 22 shows the interrupt structure of the AAI.
CP3UB17
ated internally, or they can be supplied by an external
source.
16.5.6
ferred to the receive FIFO or DMA receive register which
were received during the assigned time slots. A receive interrupt or DMA request is initiated when this occurs.
Network Mode
DMA Operation
In network mode, each frame sync signal marks the beginning of new frame. Each frame can consist of up to four
slots. The audio interface operates in a similar way to normal mode, however, in network mode the transmitter and receiver can be assigned to specific slots within each frame as
described below.
16.5.7
When a complete data word has been received through the
SRD pin in a slot n, the new data word is transferred to the
corresponding receive DMA register n (ARDRn). A DMA request is asserted when the ARDRn register is full. If a new
slot n data word is received while the ARDRn register is still
full, the ARDRn register will be overwritten with the new data.
Transmit
The transmitter only shifts out data during the assigned slot.
During all other slots the STD output is in TRI-STATE mode.
FIFO Operation
When a complete word has been received, it is transferred
to the receive FIFO at the current location of the Receive
FIFO Write Pointer (RWP). After that, the RWP is automatically incremented by 1. Therefore, data received in the next
slot is copied to the next higher FIFO location.
DMA Operation
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When a complete data word has been transmitted through
the STD pin, a new data word is reloaded from the corresponding transmit DMA register n (ATDRn). A DMA request
is asserted when ATDRn is empty. If a new data word must A read from the Audio Receive FIFO Register (ARFR) rebe transmitted in a slot n while ATDRn is still empty, the pre- sults in a read from the receive FIFO at the current location
vious slot n data will be retransmitted.
of the Receive FIFO Read Pointer (RRP). After every read
operation from the receive FIFO, the RRP is automatically
FIFO Operation
incremented by 1.
When a complete data word has been transmitted through
the STD pin, a new data word is reloaded from the transmit When the RRP is equal to the RWP and the last access to
FIFO from the current location of the Transmit FIFO Read the FIFO was a transfer to the ARFR, the receive FIFO is
Pointer (TRP). After that, the TRP is automatically incre- full. When a new complete data word has been shifted into
mented by 1. Therefore, the audio data to be transmitted in the ARSR while the receive FIFO was already full, the shift
the next slot of the frame is read from the next FIFO loca- register overruns. In this case, the new data in the ARSR will
not be transferred to the FIFO and the RWP will not be intion.
cremented. A receive FIFO overrun is indicated by the RXO
A write to the Audio Transmit FIFO Register (ATFR) results
bit in the Audio Interface Receive Status and Control Regisin a write to the transmit FIFO at the current location of the
ter (ARSCR). No receive interrupt will be generated (even if
Transmit FIFO Write Pointer (TWP). After every write operenabled).
ation to the transmit FIFO, the TWP is automatically increWhen the current RWP is equal to the TWP and the last acmented by 1.
cess to the receive FIFO was a read from ARFR, a receive
When the TRP is equal to the TWP and the last access to
FIFO underrun has occurred. This error condition is not prethe FIFO was a read operation (transfer to the ATSR), the
vented by hardware. Software must ensure that no receive
transmit FIFO is empty. When an additional read operation
underrun occurs.
from the FIFO to the ATSR is performed (while the FIFO is
already empty), a transmit FIFO underrun occurs. In this The receive frame synchronization pulse on the SRFS pin
case, the read pointer (TRP) will be decremented by 1 (in- (or SFS in synchronous mode) and the receive shift clock on
cremented by 15) and the previous data word will be trans- the SRCLK (or SCK in synchronous mode) may be genermitted again. A transmit FIFO underrun is indicated by the ated internally, or they can be supplied by an external
TXU bit in the Audio Interface Transmit Status and Control source.
Register (ATSCR). No transmit interrupt will be generated
16.6
COMMUNICATION OPTIONS
(even if enabled).
If the current TRP is equal to the TWP and the last access 16.6.1 Data Word Length
to the FIFO was a write operation (to the ATFR), the FIFO is
full. If an additional write to the ATFR is performed, a transmit FIFO overrun occurs. This error condition is not prevented by hardware. Software must ensure that no transmit
overrun occurs.
The word length of the audio data can be selected to be either 8 or 16 bits. In 16-bit mode, all 16 bits of the transmit
and receive shift registers (ATSR and ARSR) are used. In 8bit mode, only the lower 8 bits of the transmit and receive
shift registers (ATSR and ARSR) are used.
The transmit frame synchronization pulse on the SFS pin 16.6.2 Frame Sync Signal
and the transmit shift clock on the SCK pin may be generated internally, or they can be supplied by an external source. The audio interface can be configured to use either long or
short frame sync signals to mark the beginning of a new
16.5.8 Receive
data frame. If the corresponding Frame Sync Select (FSS)
The receive shift register (ARSR) receives data words of all bit in the Audio Control and Status register is clear, the reslots in the frame, regardless of the slot assignment of the ceive and/or transmit path generates or recognizes short
interface. However, only those ARSR contents are trans- frame sync pulses with a length of one bit shift clock period.
When these short frame sync pulses are used, the transfer
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92
Some codecs require an inverted frame sync signal. This is
available by setting the Inverted Frame Sync bit in the
AGCR register.
If the corresponding Frame Sync Select (FSS) bit in the Audio Control and Status register is set, the receive and/or
transmit path generates or recognizes long frame sync pulses. For 8-bit data, the frame sync pulse generated will be 6
bit shift clock periods long, and for 16-bit data the frame
sync pulse can be configured to be 13, 14, 15, or 16 bit shift
clock periods long. When receiving frame sync, it should be
active on the first bit of data and stay active for a least two
bit clock periods. It must go low for at least one bit clock period before starting a new frame. When long frame sync
pulses are used, the transfer of the first word (first slot) begins at the first positive edge of the bit shift clock after the
positive edge of the frame sync pulse. Figure 23 shows examples of short and long frame sync pulses.
16.6.3
D1
D2
D3
D4
D5
D6
D7
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D0
The audio interface provides the option to fill a 16-bit slot
with up to three data bits if only 13, 14, or 15 PCM data bits
are transmitted. These additional bits are called audio control data and are appended to the PCM data stream. The
AAI can be configured to append either 1, 2, or 3 audio control bits to the PCM data stream. The number of audio data
bits to be used is specified by the 2-bit Audio Control On
(ADMACR. ACO[1:0]) field. If the ACO field is not equal to
0, the specified number of bits are taken from the Audio
Control Data field (ADMACR. ACD[2:0]) and appended to
the data stream during every transmit operation. The
ADC[0] bit is the first bit added to the transmit data stream
after the last PCM data bit. Typically, these bits are used for
gain control, if this feature is supported by the external PCM
codec.Figure 24 shows a 16-bit slot comprising a 13-bit
PCM data word plus three audio control bits.
te
Bit Shift Clock
(SCK/SRCLK)
Shift Data
(STD/SRD)
Audio Control Data
Short Frame
Sync Pulse
Long Frame
Sync Pulse
DS156
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Figure 23. Short and Long Frame Sync Pulses
SCK
SFS
D0
D1
O
STD
D2
D3
D4
D5
D6
D7
D8
D9
D10 D11
D12 ACD2 ACD1 ACD0
13-bit PCM Data Word
Audio
Control
Bits
16-bit Slot
DS161
Figure 24. Audio Slot with Audio Control Data
93
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CP3UB17
of the first data bit or the first slot begins at the first positive
edge of the shift clock after the negative edge on the frame
sync pulse.
CP3UB17
16.6.4
IOM-2 Mode
The IOM-2 interface has the following properties:
Bit clock of 1536 kHz (output from the ISDN controller)
Frame repetition rate of 8 ksps (output from the ISDN
controller)
Double-speed bit clock (one data bit is two bit clocks
wide)
B1 and B2 data use 8-bit log PCM format
Long frame sync pulse
The AAI can operate in a special IOM-2 compatible mode to
allow to connect to an external ISDN controller device. In
this IOM-2 mode, the AAI can only operate as a slave, i.e.
the bit clock and frame sync signal is provided by the ISDN
controller. The AAI only supports the B1 and B2 data of the
IOM-2 channel 0, but ignores the other two IOM-2 channels.
The AAI handles the B1 and B2 data as one 16-bit data
word.
Figure 25 shows the structure of an IOM-2 Frame.
SFS
B1
B2
M
C
IC1
IC2
M
IOM-2 Channel 1
IOM-2 Channel 0
C
C
IOM-2 Channel 2
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STD/SRD
IOM-2 Frame (125 µs)
DS162
Figure 25. IOM-2 Frame Structure
SCK
SFS
CP3UB17
Bit Clock
Frame Sync
ISDN Controller
Data In
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STD
Data Out
A[7:0]
Address
D[7:0]
Data
SELIO
Chip Select
O
SRD
RD
Output Enable
DS160
Figure 26. CP3UB17/ISDN Controller Connections
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To connect the AAI to an ISDN controller through an IOM-2
compatible interface, the AAI needs to be configured in this
way:
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Figure 26 shows the connections between an ISDN controller and a CP3UB17 using a standard IOM-2 interface for the
B1/B2 data communication and the external bus interface
(IO Expansion) for controlling the ISDN controller.
94
The AAI must be in IOM-2 Mode (AGCR.IOM2 = 1).
The AAI operates in synchronous mode (AGCR.ASS =
0).
The AAI operates as a slave, therefore the bit clock and
frame sync source selection must be set to external
(ACGR.IEFS = 1, ACGR.IEBC = 1).
The frame sync length must be set to long frame sync
(ACGR.FSS = 1).
The data word length must be set to 16-bit (AGCR.DWL
= 1).
The AAI must be set to normal mode (AGCR.SCS[1:0] =
0).
The internal frame rate must be 8 ksps (ACCR = 00BE).
16.6.5
Loopback Mode
In loopback mode, the STD and SRD pins are internally
connected together, so data shifted out through the ATSR
register will be shifted into the ARSR register. This mode
may be used for development, but it also allows testing the
transmit and receive path without external circuitry, for example during Built-In-Self-Test (BIST).
16.7
Freeze Mode
The audio interface provides a FREEZE input, which allows
to freeze the status of the audio interface while a development system examines the contents of the FIFOs and registers.
Table 39 Audio Interface Registers
Address
Description
ARFR
FF FD40h
Audio Receive FIFO
Register
ARDR0
FF FD42h
Audio Receive DMA
Register 0
ARDR1
FF FD44h
Audio Receive DMA
Register 1
ARDR2
FF FD46h
Audio Receive DMA
Register 2
ARDR3
FF FD48h
Audio Receive DMA
Register 3
ATFR
FF FD4Ah
Audio Transmit FIFO
Register
ATDR0
FF FD4Ch
Audio Transmit DMA
Register 0
ATDR1
FF FD4Eh
Audio Transmit DMA
Register 1
ATDR2
FF FD50h
Audio Transmit DMA
Register 2
ATDR3
FF FD52h
Audio Transmit DMA
Register 3
AGCR
FF FD54h
Audio Global
Configuration Register
AISCR
FF FD56h
Audio Interrupt Status
and Control Register
ARSCR
FF FD58h
Audio Receive Status
and Control Register
ATSCR
FF FD5Ah
Audio Transmit Status
and Control Register
ACCR
FF FD5Ch
Audio Clock Control
Register
ADMACR
FF FD5Eh
Audio DMA Control
Register
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The time at which these registers are frozen will vary because they operate from a different clock than the one used
to generate the freeze signal.
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When the FREEZE input is asserted, the audio interface behaves as follows:
The receive FIFO or receive DMA registers are not updated with new data.
The receive status bits (RXO, RXE, RXF, and RXAF) are
not changed, even though the receive FIFO or receive
DMA registers are read.
The transmit shift register (ATSR) is not updated with
new data from the transmit FIFO or transmit DMA registers.
The transmit status bits (TXU, TXF, TXE, and TXAE) are
not changed, even though the transmit FIFO or transmit
DMA registers are written.
AUDIO INTERFACE REGISTERS
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CP3UB17
16.6.6
CP3UB17
16.7.1
Audio Receive FIFO Register (ARFR)
16.7.3
The Audio Receive FIFO register shows the receive FIFO
location currently addressed by the Receive FIFO Read
Pointer (RRP). The receive FIFO receives 8-bit or 16-bit
data from the Audio Receive Shift Register (ARSR), when
the ARSR is full.
The ATFR register shows the transmit FIFO location currently addressed by the Transmit FIFO Write Pointer (TWP).
The Audio Transmit Shift Register (ATSR) receives 8-bit or
16-bit data from the transmit FIFO, when the ATSR is empty.
In 8-bit mode, only the lower 8-bit portion of the ATSR is
used, and the upper byte is ignored (not transferred into the
ATSR). In 16-bit mode, a 16-bit word is copied from the
transmit FIFO into the ATSR. The CPU bus master has
write-only access to the transmit FIFO, represented by the
ATFR register. After reset, the transmit FIFO (ATFR) contains undefined data.
In 8-bit mode, only the lower byte of the ARFR is used, and
the upper byte contains undefined data. In 16-bit mode, a
16-bit word is copied from ARSR into the receive FIFO. The
CPU bus master has read-only access to the receive FIFO,
represented by the ARFR register. After reset, the receive
FIFO (ARFR) contains undefined data.
7
Audio Transmit FIFO Register (ATFR)
7
0
0
ATFL
ARFL
15
8
ATFH
ARFH
ARFH
16.7.2
The Audio Receive FIFO Low Byte shows the
lower byte of the receive FIFO location currently addressed by the Receive FIFO Read
Pointer (RRP).
The Audio Receive FIFO High Byte shows the
upper byte of the receive FIFO location currently addressed by the Receive FIFO Read
Pointer (RRP). In 8-bit mode, ARFH contains
undefined data.
bs
O
ATFH
16.7.4
Audio Receive DMA Register n (ARDRn)
The ARDRn register contains the data received within slot
n, assigned for DMA support. In 8-bit mode, only the lower
8-bit portion of the ARDRn register is used, and the upper
byte contains undefined data. In 16-bit mode, a 16-bit word
is transferred from the Audio Receive Shift Register (ARSR)
into the ARDRn register. The CPU bus master, typically a
DMA controller, has read-only access to the receive DMA
registers. After reset, these registers are clear.
7
ATFL
0
15
7
15
8
8
ATDH
The Audio Receive DMA Low Byte field receives the lower byte of the audio data copied
from the ARSR.
In 16-bit mode, the Audio Receive DMA High
Byte field receives the upper byte of the audio
data word copied from ARSR. In 8-bit mode,
the ARDH register holds undefined data.
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0
ATDL
ARDH
ARDH
Audio Transmit DMA Register n (ATDRn)
The ATDRn register contains the data to be transmitted in
slot n, assigned for DMA support. In 8-bit mode, only the
lower 8-bit portion of the ATDRn register is used, and the
upper byte is ignored (not transferred into the ATSR). In 16bit mode, the whole 16-bit word is transferred into the ATSR.
The CPU bus master, typically a DMA controller, has writeonly access to the transmit DMA registers. After reset, these
registers are clear.
ARDL
ARDL
The Audio Transmit Low Byte field represents
the lower byte of the transmit FIFO location
currently addressed by the Transmit FIFO
Write Pointer (TWP).
In 16-bit mode, the Audio Transmit FIFO High
Byte field represents the upper byte of the
transmit FIFO location currently addressed by
the Transmit FIFO Write Pointer (TWP). In 8bit mode, the ATFH field is not used.
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ATDL
ATDH
The Audio Transmit DMA Low Byte field holds
the lower byte of the audio data.
In 16-bit mode, the Audio Transmit DMA High
Byte field holds the upper byte of the audio
data word. In 8-bit mode, the ATDH field is ignored.
Audio Global Configuration Register (AGCR)
IEFS
The AGCR register controls the basic operation of the interface. The CPU bus master has read/write access to the
AGCR register. After reset, this register is clear.
7
6
5
4
IEBC
FSS
IEFS
3
SCS
2
1
0
LPB
DWL
ASS
10
9
8
CTF
CRF
FSS
14
13
CLKEN AAIEN IOM2
DWL
LPB
IFS
FSL
The Asynchronous/Synchronous Mode Select bit controls whether the audio interface
operates in Asynchronous or in Synchronous
mode. After reset the ASS bit is clear, so the
Synchronous mode is selected by default.
0 – Synchronous mode.
1 – Asynchronous mode.
The Data Word Length bit controls whether
the transferred data word has a length of 8 or
16 bits. After reset, the DWL bit is clear, so 8bit data words are used by default.
0 – 8-bit data word length.
1 – 16-bit data word length.
The Loop Back bit enables the loop back
mode. In this mode, the SRD and STD pins
are internally connected. After reset the LPB
bit is clear, so by default the loop back mode
is disabled.
0 – Loop back mode disabled.
1 – Loop back mode enabled.
The Slot Count Select field specifies the number of slots within each frame. If the number of
slots per frame is equal to 1, the audio interface operates in normal mode. If the number
of slots per frame is greater than 1, the interface operates in network mode. After reset all
SCS bits are cleared, so by default the audio
interface operates in normal mode.
O
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SCS
11
IEBC
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ASS
12
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15
The Internal/External Frame Sync bit controls,
whether the frame sync signal for the receiver
and transmitter are generated internally or
provided from an external source. After reset,
the IEFS bit is clear, so the frame synchronization signals are generated internally by default.
0 – Internal frame synchronization signal.
1 – External frame synchronization signal.
The Frame Sync Select bit controls whether
the interface (receiver and transmitter) uses
long or short frame synchronization signals.
After reset the FSS bit is clear, so short frame
synchronization signals are used by default.
0 – Short (bit length) frame synchronization
signal.
1 – Long (word length) frame synchronization
signal.
The Internal/External Bit Clock bit controls
whether the bit clocks for receiver and transmitter are generated internally or provided
from an external source. After reset, the IEBC
bit is clear, so the bit clocks are generated internally by default.
0 – Internal bit clock.
1 – External bit clock.
The Clear Receive FIFO bit is used to clear
the receive FIFO. When this bit is written with
a 1, all pointers of the receive FIFO are set to
their reset state. After updating the pointers,
the CRF bit will automatically be cleared
again.
0 – Writing 0 has no effect.
1 – Writing 1 clears the receive FIFO.
The Clear Transmit FIFO bit is used to clear
the transmit FIFO. When this bit is written with
a 1, all pointers of the transmit FIFO are set to
their reset state. After updating the pointers,
the CTF bit will automatically be cleared
again.
0 – Writing 0 has no effect.
1 – Writing 1 clears the transmit FIFO.
The Frame Sync Length field specifies the
length of the frame synchronization signal,
when a long frame sync signal (FSS = 1) and
a 16-bit data word length (DWL = 1) are used.
If an 8-bit data word length is used, long frame
syncs are always 6 bit clocks in length.
CRF
CTF
FSL
SCS
Number of
Slots per
Frame
Mode
00
1
Normal mode
01
2
Network mode
FSL
Frame Sync Length
10
3
Network mode
00
13 bit clocks
11
4
Network mode
01
14 bit clocks
10
15 bit clocks
11
16 bit clocks
IFS
97
The Inverted Frame Sync bit controls the polarity of the frame sync signal.
0 – Active-high frame sync signal.
1 – Active-low frame sync signal.
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CP3UB17
16.7.5
The IOM-2 Mode bit selects the normal PCM
interface mode or a special IOM-2 mode used
to connect to external ISDN controller devices. The AAI can only operate as a slave in the
IOM-2 mode, i.e. the bit clock and frame sync
signals are provided by the ISDN controller. If
the IOM2 bit is clear, the AAI operates in the
normal PCM interface mode used to connect
to external PCM codecs and other PCM audio
devices.
0 – IOM-2 mode disabled.
1 – IOM-2 mode enabled.
The AAI Enable bit controls whether the Advanced Audio Interface is enabled. All AAI
registers provide read/write access while
(CLKEN = 1) AAIEN is clear. The AAIEN bit is
clear after reset.
0 – AAI module disabled.
1 – AAI module enabled.
The Clock Enable bit controls whether the Advanced Audio Interface clock is enabled. The
CLKEN bit must be set to allow access to any
AAI register. It must also be set before any
other bit of the AGCR can be set. The CLKEN
bit is clear after reset.
0 – AAI module clock disabled.
1 – AAI module clock enabled.
AAIEN
16.7.6
TXEIE
RXIP
RXEIP
Audio Interrupt Status and Control Register
(AISCR)
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The ASCR register is used to specify the source and the
conditions, when the audio interface interrupt is asserted to TXIP
the Interrupt Control Unit. It also holds the interrupt pending
bits and the corresponding interrupt clear bits for each audio
interface interrupt source. The CPU bus master has read/
write access to the ASCR register. After reset, this register
is clear.
7
6
5
4
3
2
1
0
TXEIP
TXEIP TXIP RXEIP RXIP TXEIE TXIE RXEIE RXIE
12
11
10
9
8
O
15
Reserved
RXIE
RXEIE
The Transmit Interrupt Enable bit controls
whether transmit interrupts are generated.
Setting this bit enables a transmit interrupt,
when the Transmit Buffer Almost Empty (TXAE) bit is set. If the TXIE bit is clear, no interrupt will be generated.
0 – Transmit interrupt disabled.
1 – Transmit interrupt enabled.
The Transmit Error Interrupt Enable bit controls whether transmit error interrupts are generated. Setting this bit to 1 enables a transmit
error interrupt, when the Transmit Buffer Underrun (TXUR) bit is set. If the TXEIE bit is
clear, no transmit error interrupt will be generated.
0 – Transmit error interrupt disabled.
1 – Transmit error interrupt enabled.
The Receive Interrupt Pending bit indicates
that a receive interrupt is currently pending.
The RXIP bit is cleared by writing a 1 to the
RXIC bit. The RXIP bit provides read-only access.
0 – No receive interrupt pending.
1 – Receive interrupt pending.
The Receive Error Interrupt Pending bit indicates that a receive error interrupt is currently
pending. The RXEIP bit is cleared by writing a
1 to the RXEIC bit. The RXEIP bit provides
read-only access.
0 – No receive error interrupt pending.
1 – Receive error interrupt pending.
The Transmit Interrupt Pending bit indicates
that a transmit interrupt is currently pending.
The TXIP bit is cleared by writing a 1 to the
TXIC bit. The TXIP bit provides read-only access.
0 – No transmit interrupt pending.
1 – Transmit interrupt pending.
Transmit Error Interrupt Pending. This bit indicates that a transmit error interrupt is currently
pending. The TXEIP bit is cleared by software
by writing a 1 to the TXEIC bit. The TXEIP bit
provides read-only access.
0 – No transmit error interrupt pending.
1 – Transmit error interrupt pending.
The Receive Interrupt Clear bit is used to
clear the RXIP bit.
0 – Writing a 0 to the RXIC bit is ignored.
1 – Writing a 1 clears the RXIP bit.
The Receive Error Interrupt Clear bit is used
to clear the RXEIP bit.
0 – Writing a 0 to the RXEIC bit is ignored.
1 – Writing a 1 clears the RXEIP bit.
The Transmit Interrupt Clear bit is used to
clear the TXIP bit.
0 – Writing a 0 to the TXIC bit is ignored.
1 – Writing a 1 clears the TXIP bit.
The Transmit Error Interrupt Clear bit is used
to clear the TXEIP bit.
0 – Writing a 0 to the TXEIC bit is ignored.
1 – Writing a 1 clears the TXEIP bit.
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CLKEN
TXIE
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CP3UB17
IOM2
TXEIC TXIC RXEIC RXIC
RXIC
The Receive Interrupt Enable bit controls
whether receive interrupts are generated. If
the RXIE bit is clear, no receive interrupt will RXEIC
be generated.
0 – Receive interrupt disabled.
1 – Receive interrupt enabled.
The Receive Error Interrupt Enable bit con- TXIC
trols whether receive error interrupts are generated. Setting this bit enables a receive error
interrupt, when the Receive Buffer Overrun
(RXOR) bit is set. If the RXEIE bit is clear, no TXEIC
receive error interrupt will be generated.
0 – Receive error interrupt disabled.
1 – Receive error interrupt enabled.
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98
Audio Receive Status and Control Register
(ARSCR)
The following table shows the slot assignment
scheme.
The ARSCR register is used to control the operation of the
receiver path of the audio interface. It also holds bits which
report the current status of the receive FIFO. The CPU bus
master has read/write access to the ASCR register. At reset, this register is loaded with 0004h.
7
4
RXSA
15
12
3
2
RXO
RXE
RXE
RXDSA
RXDSA
O
RXSA
RXSA0
0
RXSA1
1
RXSA2
2
RXSA3
3
After reset the RXSA field is clear, so software
must load the correct slot assignment.
The Receive DMA Slot Assignment field specifies which slots (audio channels) are supported by DMA. If the RXDSA bit is set for an
assigned slot n (RXSAn = 1), the data received within this slot will not be transferred
into the receive FIFO, but will instead be written into the corresponding Receive DMA data
register (ARDRn). A DMA request n is asserted, when the ARDRn is full and if the RMA bit
n is set. If the RXSD bit for a slot is clear, the
RXDSA bit is ignored. The following table
shows the DMA slot assignment scheme.
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The Receive Buffer Almost Full bit is set when
the number of data bytes/words in the receive
buffer is equal to the specified warning limit.
0 – Receive FIFO below warning limit.
1 – Receive FIFO is almost full.
The Receive Buffer Full bit is set when the receive buffer is full. The RXF bit is set when the
RWP is equal to the RRP and the last access
was a write to the FIFO.
0 – Receive FIFO is not full.
1 – Receive FIFO full.
The Receive Buffer Empty bit is set when the
the RRP is equal to the RWP and the last access to the FIFO was a read operation (read
from ARDR).
0 – Receive FIFO is not empty.
1 – Receive FIFO is empty.
The Receive Overflow bit indicates that a receive shift register has overrun. This occurs,
when a completed data word has been shifted
RXFWL
into ARSR, while the receive FIFO was already full (the RXF bit was set). In this case,
the new data in ARSR will not be copied into
the FIFO and the RWP will not be incremented. Also, no receive interrupt and DMA request will generated (even if enabled).
0 – No overflow has occurred.
1 – Overflow has occurred.
The Receive Slot Assignment field specifies
which slots are recognized by the receiver of
the audio interface. Multiple slots may be enabled. If the frame consists of less than 4
slots, the RXSA bits for unused slots are ignored. For example, if a frame only consists of
2 slots, RXSA bits 2 and 3 are ignored.
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RXO
8
Slots Enabled
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RXF
0
RXF RXAF
11
RXFWL
RXAF
1
RXSA Bit
99
RXDSA Bit
Slots Enabled
for DMA
RXDSA0
0
RXDSA1
1
RXDSA2
2
RXDSA3
3
The Receive FIFO Warning Level field specifies when a receive interrupt is asserted. A receive interrupt is asserted, when the number
of bytes/words in the receive FIFO is greater
than the warning level value. An RXFWL value
of 0 means that a receive interrupt is asserted
if one or more bytes/words are in the RX
FIFO. After reset, the RXFWL bit is clear.
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CP3UB17
16.7.7
CP3UB17
16.7.8
Audio Transmit Status and Control Register
(ATSCR)
The ASCR register controls the basic operation of the interface. It also holds bits which report the current status of the
audio communication. The CPU bus master has read/write
access to the ASCR register. At reset, this register is loaded
with F003h.
7
4
TXSA
15
12
3
2
TXU
TXF
TXDSA
TXSA
0
TXSA1
1
TXSA2
2
TXSA3
3
After reset, the TXSA field is clear, so software must load the correct slot assignment.
The Transmit DMA Slot Assignment field
specifies which slots (audio channels) are
supported by DMA. If the TXDSA bit is set for
an assigned slot n (TXSAn = 1), the data to be
transmitted within this slot will not be read
from the transmit FIFO, but will instead be
read from the corresponding Transmit DMA
data register (ATDRn). A DMA request n is asserted when the ATDRn is empty. If the TSA
bit for a slot is clear, the TXDSA bit is ignored.
The following table shows the DMA slot assignment scheme.
te
The Transmit FIFO Almost Empty bit is set
when the number of data bytes/words in
transmit buffer is equal to the specified warning limit.
0 – Transmit FIFO above warning limit.
1 – Transmit FIFO at or below warning limit.
The Transmit FIFO Empty bit is set when the
transmit buffer is empty. The TXE bit is set to
one every time the TRP is equal to the TWP
and the last access to the FIFO was read operation (into ATSR).
0 – Transmit FIFO not empty.
1 – Transmit FIFO empty.
The Transmit FIFO Full bit is set when the
TWP is equal to the TRP and the last access
to the FIFO was write operation (write to ATDR).
0 – Transmit FIFO not full.
1 – Transmit FIFO full.
The Transmit Underflow bit indicates that the TFWL
transmit shift register (ATSR) has underrun.
This occurs when the transmit FIFO was already empty and a complete data word has
been transferred. In this case, the TRP will be
decremented by 1 and the previous data will
be retransmitted. No transmit interrupt and no
DMA request will be generated (even if enabled).
0 – Transmit underrun occurred.
1 – Transmit underrun did not occur.
The Transmit Slot Assignment field specifies
during which slots the transmitter is active and
drives data through the STD pin. The STD pin
is in high impedance state during all other
slots. If the frame consists of less than 4 slots,
the TXSA bits for unused slots are ignored.
For example, if a frame only consists of 2
slots, TXSA bits 2 and 3 are ignored. The following table shows the slot assignment
scheme.
O
TXU
TXSA0
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TXF
8
TXDSA
bs
TXE
0
Slots Enabled
TXE TXAE
11
TXFWL
TXAE
1
TXSA Bit
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100
TXDSA Bit
Slots Enabled
for DMA
TXDSA0
0
TXDSA1
1
TXDSA2
2
TXDSA3
3
The Transmit FIFO Warning Level field specifies when a transmit interrupt is asserted. A
transmit interrupt is asserted when the number of bytes or words in the transmit FIFO is
equal or less than the warning level value. A
TXFWL value of Fh means that a transmit interrupt is asserted if one or more bytes or
words are available in the transmit FIFO. At
reset, the TXFWL field is loaded with Fh.
Audio Clock Control Register (ACCR)
ignored. The following table shows the receive
DMA request scheme.
The ACCR register is used to control the bit timing of the audio interface. After reset, this register is clear.
7
1
FCPRS
15
RMD
DMA Request Condition
0
0000
None
CSS
0001
ARDR0 full
0010
ARDR1 full
0011
ARDR0 full or ARDR1 full
x1xx
Not supported on
CP3UB17
8
BCPRS
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BCPRS
16.7.10 Audio DMA Control Register (ADMACR)
The ADMACR register is used to control the DMA support
of the audio interface. In addition, it is used to configure the
automatic transmission of the audio control bits. After reset,
this register is clear.
4
O
7
3
TMD
15
13
Reserved
RMD
The Transmit Master DMA field specifies
which slots (audio channels) are supported by
DMA, i.e. when a DMA request is asserted to
the DMA controller. If the TMD bit is set for an
assigned slot n (TXDSAn = 1), a DMA request
n is asserted, when the ATDRn register is
empty. If the TXDSA bit for a slot is clear, the
TMD bit is ignored. The following table shows
the transmit DMA request scheme.
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FCPRS
The Clock Source Select bit selects one out of
two possible clock sources for the audio interTMD
face. After reset, the CSS bit is clear.
0 – The Aux1 clock is used to clock the Audio
Interface.
1 – The 48-MHz USB clock is used to clock
the Audio Interface.
The Frame Clock Prescaler is used to divide
the bit clock to generate the frame clock for
the receive and transmit operations. The bit
clock is divided by (FCPRS + 1). After reset,
the FCPRS field is clear. The maximum allowed bit clock rate to achieve an 8 kHz frame
clock is 1024 kHz. This value must be set correctly even if the frame sync is generated externally.
The Bit Clock Prescaler is used to divide the
audio interface clock (selected by the CSS bit)
to generate the bit clock for the receive and
transmit operations. The audio interface input
clock is divided by (BCPRS + 1). After reset,
the BCPRS[7:0] bits are clear.
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CSS
1xxx
12
11
ACO
ACD
ACO
RMD
8
ACD
16.8
The Receive Master DMA field specify which
slots (audio channels) are supported by DMA,
i.e. when a DMA request is asserted to the
DMA controller. If the RMDn bit is set for an
assigned slot n (RXDSAn = 1), a DMA request
n is asserted, when the ARDRn is full. If the
RXDSAn bit for a slot is clear, the RMDn bit is
DMA Request Condition
0000
None
0001
ATDR0 empty
0010
ATDR1 empty
0011
ATDR0 empty or
ATDR1 empty
x1xx
1xxx
0
10
TMD
Not supported on
CP3UB17
The Audio Control Data field is used to fill the
remaining bits of a 16-bit slot if only 13, 14, or
15 bits of PCM audio data are transmitted.
The Audio Control Output field controls the
number of control bits appended to the PCM
data word.
00 – No Audio Control bits are appended.
01 – Append ACD0.
10 – Append ACD1:0.
11 – Append ACD2:0.
USAGE HINTS
When the Advanced Audio Interface is active, it can lock up
if the receive FIFO is cleared by writing 1 to the AGCR.CRF
bit, the transmit FIFO is cleared by writing 1 to the
AGCR.CTF bit, or the module is disabled by clearing the
AGCR.AAIEN bit.
Follow this procedure to disable the Advanced Audio Interface:
101
1. Clear the ARSCR.RXSA and ATSCR.TXSA fields.
2. Wait at least 10 receive/transmit clock cycles.
3. Clear the AGCR.AAIEN bit.
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CP3UB17
16.7.9
CP3UB17
17.0 CVSD/PCM Conversion Module
The CVSD/PCM module performs conversion between
CVSD data and PCM data, in which the CVSD encoding is
as defined in the Bluetooth specification and the PCM encoding may be 8-bit µ-Law, 8-bit A-Law, or 13-bit to 16-bit
Linear.
is a read and a write FIFO allowing up to 8 words of data to
be read or written at the same time. On the PCM side, there
is a double-buffered register requiring data to be read and
written every 125 µs. The intended use is to move CVSD
data into the module with a CVSD interrupt handler, and to
move PCM data with DMA. Figure 27 shows a block diagram of the CVSD to PCM module.
The CVSD conversion module operates at a fixed rate of
125 µs (8 kHz) per PCM sample. On the CVSD side, there
2 MHz
Clock Input
Interrupt
DMA
16-Bit 8 kHz
16-Bit
64 kHz
u/A-Law
16-Bit Shift Reg
Filter
Engine
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16-Bit 8 kHz
1-Bit 64 kHz
CVSD
Encoder
16-Bit
u/A-Law
64 kHz
1-Bit 64 kHz
CVSD
Decoder
16-Bit Shift Reg
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Peripheral Bus
DS058
Figure 27. CVSD/PCM Converter Block Diagram
17.1
OPERATION
bs
The Aux2 clock (generated by the Clock module described
in Section 11.8) must be configured, because it drives the
CVSD module. Software must set its prescaler to provide a
2 MHz input clock based upon the System Clock (usually
12 MHz). This is done by writing an appropriate divisor to
the ACDIV2 field of the PRSAC register. Software must also
enable the Aux2 clock by setting the ACE2 bit within the
CRCTRL register. For example:
Inside the module, a filter engine receives the 8 kHz stream
of 16-bit samples and interpolates to generate a 64 kHz
stream of 16-bit samples. This goes into a CVSD encoder
which converts the data into a single-bit delta stream using
the CVSD parameters as defined by the Bluetooth specification. There is a similar path that reverses this process
converting the CVSD 64 kHz bit stream into a 64 kHz 16-bit
data stream. The filter engine then decimates this stream
into an 8 kHz, 16-bit data stream.
PRSAC &= 0x0f;
17.2
// Set Aux2 prescaler to generate
During conversion between CVSD and PCM, any PCM format changes are done automatically depending on whether
the PCM data is µ-Law, A-Law, or Linear. In addition to this,
a separate function can be used to convert between the various PCM formats as required. Conversion is performed by
setting up the control bit CVCTL1.PCMCONV to define the
conversion and then writing to the LOGIN and LINEARIN
registers and reading from the LOGOUT and LINEAROUT
registers. There is no delay in the conversion operation and
it does not have to operate at a fixed rate. It will only convert
between µ-Law/A-Law and linear, not directly between µLaw and A-Law. (This could easily be achieved by converting between µ-Law and linear and between linear and ALaw.)
// 2 MHz (Fsys = 12 MHz)
PRSAC |= 0x50;
O
CRCTRL |= ACE2; // Enable Aux2 clk
The module converts between PCM data and CVSD data at
a fixed rate of 8 kHz per PCM sample. Due to compression,
the data rate on the CVSD side is only 4 kHz per CVSD
sample.
PCM CONVERSIONS
If PCM interrupts are enabled (PCMINT is set) every 125 µs
(8 kHz) an interrupt will occur and the interrupt handler can
operate on some or all of the four audio streams CVSD in,
CVSD out, PCM in, and PCM out. Alternatively, a DMA request is issued every 125 µs and the DMA controller is used If a conversion is performed between linear and µ-Law log
to move the PCM data between the CVSD/PCM module PCM data, the linear PCM data are treated in the leftand the audio interface.
aligned 14-bit linear data format with the two LSBs unused.
If CVSD interrupts are enabled, an interrupt is issued when If a conversion is performed between linear and A-Law log
either one of the CVSD FIFOs is almost empty or almost full. PCM data, the linear PCM data are treated in the leftOn the PCM data side there is double buffering, and on the aligned 13-bit linear data format with the three LSBs unCVSD side there is an eight word (8 × 16-bit) FIFO for the used.
read and write paths.
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If the resolution is not set properly, the audio signal may be 8 × 16 bit (8 words). The warning limits for the two FIFOs is
set at 5 words. (The CVSD In FIFO interrupt will occur when
clipped or have reduced attenuation.
there are 3 words left in the FIFO, and the CVSD Out FIFO
17.4
PCM TO CVSD CONVERSION
interrupt will occur when there are 3 or less empty words left
The converter core reads out the double-buffered PCMIN in the FIFO.) The limit is set to 5 words because Bluetooth
register every 125 µs and writes a new 16-bit CVSD data audio data is transferred in packages composed of 10 or
stream into the CVSD Out FIFO every 250 µs. If the PCMIN multiples of 10 bytes.
buffer has not been updated with a new PCM sample beDMA SUPPORT
tween two reads from the CVSD core, the old PCM data is 17.7
used again to maintain a fixed conversion rate. Once a new The CVSD module can operate with any of four DMA chan16-bit CVSD data stream has been calculated, it is copied nels. Four DMA channels are required for processor independent operation. Both receive and transmit for CVSD
into the 8 × 16-bit wide CVSD Out FIFO.
If there are only three empty words (16-bit) left in the FIFO, data and PCM data can be enabled individually. The CVSD/
the nearly full bit (CVNF) is set, and, if enabled PCM module asserts a DMA request to the on-chip DMA
controller under the following conditions:
(CVSDINT = 1), an interrupt request is asserted.
If the CVSD Out FIFO is full, the full bit (CVF) is set, and, if The DMAPO bit is set and the PCMOUT register is full,
because it has been updated by the converter core with
enabled (CVSDERRINT = 1), an interrupt request is asserta new PCM sample. (The DMA controller can read out
ed. In this case, the CVSD Out FIFO remains unchanged.
one PCM data word from the PCMOUT register.)
Within the interrupt handler, the CPU can read out the new The DMAPI bit is set and the PCMIN register is empty,
CVSD data. If the CPU reads from an already empty CVSD
because it has been read by the converter core. (The
Out FIFO, a lockup of the FIFO logic may occur which perDMA controller can write one new PCM data word into
sists until the next reset. Software must check the
the PCMIN register.)
CVOUTST field of the CVSTAT register to read the number The DMACO bit is set and a new 16-bit CVSD data
of valid words in the FIFO. Software must not use the CVNF
stream has been copied into the CVSD Out FIFO. (The
bit as an indication of the number of valid words in the FIFO.
DMA controller can read out one 16-bit CVSD data word
from the CVSD Out FIFO.)
17.5
CVSD TO PCM CONVERSION
The DMACI bit is set and a 16-bit CVSD data stream has
The converter core reads from the CVSD In FIFO every
been read from the CVSD In FIFO. (The DMA controller
250 µs and writes a new PCM sample into the PCMOUT
can write one new 16-bit CVSD data word into the CVSD
buffer every 125 µs. If the previous PCM data has not yet
In FIFO.)
103
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CP3UB17
If the module is only used for PCM conversions, the CVSD been transferred to the audio interface, it will be overwritten
clock can be disabled by clearing the CVSD Clock Enable with the new PCM sample.
bit (CLKEN) in the control register.
If there are only three unread words left, the CVSD In Nearly
Empty bit (CVNE) is set and, if enabled (CVSDINT = 1), an
17.3
CVSD CONVERSION
interrupt request is generated.
The CVSD/PCM converter module transforms either 8-bit
logarithmic or 13- to 16-bit linear PCM samples at a fixed If the CVSD In FIFO is empty, the CVSD In Empty bit (CVE)
rate of 8 ksps. The CVSD to PCM conversion format must is set and, if enabled (CVSDERRINT = 1), an interrupt rebe specified by the CVSDCONV control bits in the CVSD quest is generated. If the converter core reads from an already empty CVSD In FIFO, the FIFO automatically returns
Control register (CVCTRL).
a checkerboard pattern to guarantee a minimum level of disThe CVSD algorithm is designed for 2’s complement 16-bit tortion of the audio stream.
data and is tuned for best performance with typical voice daINTERRUPT GENERATION
ta. Mild distortion will occur for peak signals greater than -6 17.6
dB. The Bluetooth CVSD standard is designed for best per- An interrupt is generated in any of the following cases:
formace with typical voice signals: nominaly -6dB with occasional peaks to 0dB rather than full-scale inputs. Distortion When a new PCM sample has been written into the
PCMOUT register and the CVCTRL.PCMINT bit is set.
of signals greater than -6dB is not considered detrimental to
subjective quality tests for voice-band applications and al- When a new PCM sample has been read from the
PCMIN register and the CVCTRL.PCMINT bit is set.
lows for greater clarity for signals below -6dB. The gain of
When the CVSD In FIFO is nearly empty
the input device should be tuned with this in mind.
(CVSTAT.CVNE = 1) and the CVCTRL.CVSDINT bit is
If required, the RESOLUTION field of the CVCTRL register
set.
can be used to optimize the level of the 16-bit linear input When the CVSD Out FIFO is nearly full
data by providing attenuations (right-shifts with sign exten(CVSTAT.CVNF = 1) and the CVCTRL.CVSDINT bit is
tion) of 1, 2, or 3 bits.
set.
Log data is always 8 bit, but to perform the CVSD conver- When the CVSD In FIFO is empty (CVSTAT.CVE = 1)
and the CVCTRL.CVSDERRINT bit is set.
sion, the log data is first converted to 16-bit 2’s complement
linear data. A-law and u-law conversion can also slightly af- When the CVSD Out FIFO is full (CVSTAT.CVF = 1) and
the CVCTRL.CVSDERRINT bit is set.
fect the optimum gain of the input data. The CVCTRL.RESOLUTION field can be used to attenuate the data if required. Both the CVSD In and CVSD Out FIFOs have a size of
Table 40 CVSD/PCM Registers
Name
Address
Description
The trigger for DMA may also trigger an interrupt if the corresponding enable bits in the CVCTRL register is set.
Therefore care must be taken when setting the desired interrupt and DMA enable bits. The following conditions must
be avoided:
LINEAROUT
FF FC2Eh
Linear PCM
Data Output Register
CVCTRL
FF FC30h
CVSD Control Register
Setting the PCMINT bit and either of the DMAPO or
DMAPI bits.
Setting the CVSDINT bit and either of the DMACO or
DMACI bits.
CVSTAT
FF FC32h
CVSD Status Register
17.8
15
0
CVSDIN
17.9.2
CVSD Data Output Register (CVSDOUT)
The CVSDOUT register is a 16-bit wide read-only register.
It is used to read the CVSD data from the PCM to CVSD
converter. The FIFO is 8 words deep. Reading the CVSDOUT register after reset returns undefined data.
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CVSD In FIFO will not have data removed by the converter core.
CVSD Out FIFO will not have data added by the converter core.
PCM Out buffer will not be updated by the converter
core.
The Clear-on-Read function of the following status bits in
the CVSTAT register is disabled:
PCMINT
CVE
CVF
CVSD Data Input Register (CVSDIN)
The CVSDIN register is a 16-bit wide, write-only register. It
is used to write CVSD data into the CVSD to PCM converter
FIFO. The FIFO is 8 words deep. The CVSDIN bit 15 represents the CVSD data bit at t = t0, CVSDIN bit 0 represents
the CVSD data bit at t = t0 - 250 ms.
FREEZE
The CVSD/PCM module provides support for an In-SystemEmulator by means of a special FREEZE input. While
FREEZE is asserted the module will exhibit the following behavior:
17.9
17.9.1
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CP3UB17
The CVSD/PCM module only supports indirect DMA transfers. Therefore, transferring PCM data between the CVSD/
PCM module and another on-chip module requires two bus
cycles.
15
CVSD/PCM CONVERTER REGISTERS
0
CVSDOUT
Table 40 lists the CVSD/PCM registers.
Table 40 CVSD/PCM Registers
bs
17.9.3
Address
Description
CVSDIN
FF FC20h
CVSD Data Input
Register
CVSDOUT
FF FC22h
CVSD Data Output
Register
O
Name
PCMIN
FF FC24h
PCM Data Input
Register
PCMOUT
FF FC26h
PCM Data Output
Register
LOGIN
FF FC28h
Logarithmic PCM
Data Input Register
LOGOUT
FF FC2Ah
Logarithmic PCM
Data Output Register
LINEARIN
FF FC2Ch
Linear PCM
Data Input Register
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PCM Data Input Register (PCMIN)
The PCMIN register is a 16-bit wide write-only register. It is
used to write PCM data to the PCM to CVSD converter via
the peripheral bus. It is double-buffered, providing a 125 µs
period for an interrupt or DMA request to respond.
15
0
PCMIN
17.9.4
PCM Data Output Register (PCMOUT)
The PCMOUT register is a 16-bit wide read-only register. It
is used to read PCM data from the CVSD to PCM converter.
It is double-buffered, providing a 125 µs period for an interrupt or DMA request to respond. After reset the PCMOUT
register is clear.
15
0
PCMOUT
104
Logarithmic PCM Data Input Register (LOGIN)
The Module Enable bit enables or disables the
CVSD conversion module interface. When the
The LOGIN register is an 8-bit wide write-only register. It is
bit is set, the interface is enabled which allows
used to receive 8-bit logarithmic PCM data from the periphread and write operations to the rest of the
eral bus and convert it into 13-bit linear PCM data.
module. When the bit is clear, the module is
disabled. When the module is disabled the
7
0
status register CVSTAT will be cleared to its
reset state.
LOGIN
0 – CVSD module enabled.
1 – CVSD module disabled.
CLKEN
The CVSD Clock Enable bit enables the 217.9.6 Logarithmic PCM Data Output Register
MHz clock to the filter engine and CVSD en(LOGOUT)
coders and decoders.
The LOGOUT register is an 8-bit wide read-only register. It
0 – CVSD module clock disabled.
holds logarithmic PCM data that has been converted from
1 – CVSD module clock enabled.
linear PCM data. After reset, the LOGOUT register is clear.
PCMINT
The PCM Interrupt Enable bit controls generation of the PCM interrupt. If set, this bit enables the PCM interrupt. If the PCMINT bit is
7
0
clear, the PCM interrupt is disabled. After reLOGOUT
set, this bit is clear.
0 – PCM interrupt disabled.
1 – PCM interrupt enabled.
17.9.7 Linear PCM Data Input Register (LINEARIN)
CVSDINT
The CVSD FIFO Interrupt Enable bit controls
The LINEARIN register is a 16-bit wide write-only register.
generation of the CVSD interrupt. If set, this
The data is left-aligned. When converting to A-law, bits 2:0
bit enables the CVSD interrupt that occurs if
are ignored. When converting to µ-law, bits 1:0 are ignored.
the CVSD In FIFO is nearly empty or the
CVSD Out FIFO is nearly full. If the CVSDINT
bit is clear, the CVSD nearly full/nearly empty
15
0
interrupt is disabled. After reset, this bit is
LINEARIN
clear.
0 – CVSD interrupt disabled.
1 – CVSD interrupt enabled.
17.9.8 Linear PCM Data Output Register
CVSDERRINT The CVSD FIFO Error Interrupt Enable bit
(LINEAROUT)
controls generation of the CVSD error interThe LINEAROUT register is a 16-bit wide read-only register.
rupt. If set, this bit enables an interrupt to ocThe data is left-aligned. When converting from A-law, bits
cur when the CVSD Out FIFO is full or the
2:0 are clear. When converting from µ-law, bits 1:0 are clear.
CVSD In FIFO is empty. If the CVSDERRORAfter reset, this register is clear.
INT bit is clear, the CVSD full/empty interrupt
is disabled. After reset, this bit is clear.
0 – CVSD error interrupt disabled.
15
0
1 – CVSD error interrupt enabled.
LINEAROUT
DMACO
The DMA Enable for CVSD Out bit enables
hardware DMA control for reading CVSD data
from the CVSD Out FIFO. If clear, DMA sup17.9.9 CVSD Control Register (CVCTRL)
port is disabled. After reset, this bit is clear.
0 – CVSD output DMA disabled.
The CVCTRL register is a 16-bit wide, read/write register
1 – CVSD output DMA enabled.
that controls the mode of operation and of the module’s inDMACI
The DMA Enable for CVSD In bit enables
terrupts. At reset, all implemented bits are cleared.
hardware DMA control for writing CVSD data
into the CVSD In FIFO. If clear, DMA support
7
6
5
4
3
2
1
0
is disabled. After reset, this bit is clear.
CVSD
0 – CVSD input DMA disabled.
DMA DMA DMA
CVSD PCM CLK
CVEN
ERR1 – CVSD input DMA enabled.
PO
CI
CO
INT
INT
EN
INT
DMAPO
The DMA Enable for PCM Out bit enables
hardware DMA control for reading PCM data
from the PCMOUT register. If clear, DMA sup15 14 13
12
11
10
9
8
port is disabled. After reset, this bit is clear.
0 – PCM output DMA disabled.
Res. RESOLUTION PCMCONV CVSDCONV DMAPI
1 – PCM output DMA enabled.
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CVEN
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CP3UB17
17.9.5
The DMA Enable for PCM In bit enables hard- CVNF
ware DMA control for writing PCM data into
the PCMIN register. If cleared, DMA support
is disabled. After reset, this bit is clear.
0 – PCM input DMA disabled.
1 – PCM input DMA enabled.
CVSDCONV The CVSD to PCM Conversion Format field
specifies the PCM format for CVSD/PCM conversions. After reset, this field is clear.
00 – CVSD 8-bit µ-Law PCM.
01 – CVSD 8-bit A-Law PCM.
10 – CVSD Linear PCM.
11 – Reserved.
PCMCONV The PCM to PCM Conversion Format bit selects the PCM format for PCM/PCM conversions.
PCMINT
0 – Linear PCM 8-bit µ-Law PCM
1 – Linear PCM 8-bit A-Law PCM
RESOLUTION The Linear PCM Resolution field specifies the
attenuation of the PCM data for the linear
PCM to CVSD conversions by right shifting
and sign extending the data. This affects the
log PCM data as well as the linear PCM data.
The log data is converted to either left-justified CVE
zero-stuffed 13-bit (A-law) or 14-bit (u-law).
The RESOLUTION field can be used to compensate for any change in average levels resulting from this conversion. After reset, these
two bits are clear.
00 – No shift.
01 – 1-bit attentuation.
10 – 2-bit attentuation.
11 – 3-bit attentuation.
The CVSD Out FIFO Nearly Full bit indicates
when only three empty word locations are left
in the CVSD Out FIFO, so the CVSD Out
FIFO should be read. If the CVSDINT bit is
set, an interrupt will be asserted when the
CVNF bit is set. If the DMACO bit is set, a
DMA request will be asserted when this bit is
set. Software must not rely on the CVNF bit as
an indicator of the number of valid words in
the FIFO. Software must check the CVOUTST
field to read the number of valid words in the
FIFO. The CVNF bit is cleared when the
CVSTAT register is read.
0 – CVSD Out FIFO is not nearly full.
1 – CVSD Out FIFO is nearly full.
The PCM Interrupt bit set indicates that the
PCMOUT register is full and needs to be read
or the PCMIN register is empty and needs to
be loaded with new PCM data. The PCMINT
bit is cleared when the CVSTAT register is
read, unless the device is in FREEZE mode.
0 – PCM does not require service.
1 – PCM requires loading or unloading.
The CVSD In FIFO Empty bit indicates when
the CVSD In FIFO has been read by the
CVSD converter while the FIFO was already
empty. If the CVSDERRORINT bit is set, an
interrupt will be asserted when the CVE bit is
set. The CVE bit is cleared when the CVSTAT
register is read, unless the device is in
FREEZE mode.
0 – CVSD In FIFO has not been read while
empty.
1 – CVSD In FIFO has been read while empty.
The CVSD Out FIFO Full bit set indicates
whether the CVSD Out FIFO has been written
by the CVSD converter while the FIFO was already full. If the CVSDERRORINT bit is set,
an interrupt will be asserted when the CVF bit
is set. The CVF bit is cleared when the
CVSTAT register is read, unless the device is
in FREEZE mode.
0 – CVSD Out FIFO has not been written
while full.
1 – CVSD Out FIFO has been written while
full.
The CVSD In FIFO Status field reports the
current number of empty 16-bit word locations
in the CVSD In FIFO. When the FIFO is empty, the CVINST field will read as 111b. When
the FIFO holds 7 or 8 words of data, the
CVINST field will read as 000b.
CVSD Out FIFO Status field reports the current number of valid 16-bit CVSD data words
in the CVSD Out FIFO. When the FIFO is
empty, the CVOUTST field will read as 000b.
When the FIFO holds 7 or 8 words of data, the
CVOUTST field will read as 111b.
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DMAPI
17.9.10 CVSD Status Register (CVSTAT)
7
bs
The CVSTAT register is a 16-bit wide, read-only register that CVF
holds the status information of the CVSD/PCM module. At
reset, and if the CVCTL1.CVEN bit is clear, all implemented
bits are cleared.
5
CVF
3
2
15
11
Reserved
CVNE
1
0
CVE PCMINT CVNF CVNE
O
CVINST
4
10
8
CVOUTST
CVINST
The CVSD In FIFO Nearly Empty bit indicates
when only three CVSD data words are left in
the CVSD In FIFO, so new CVSD data should
be written into the CVSD In FIFO. If the CVSDINT bit is set, an interrupt will be asserted CVOUTST
when the CVNE bit is set. If the DMACI bit is
set, a DMA request will be asserted when this
bit is set. The CVNE bit is cleared when the
CVSTAT register is read.
0 – CVSD In FIFO is not nearly empty.
1 – CVSD In FIFO is nearly empty.
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106
The UART module is a full-duplex Universal Asynchronous
Receiver/Transmitter that supports a wide range of software-programmable baud rates and data formats. It handles automatic parity generation and several error detection
schemes.
of data from the UART, it de-asserts the clear-to-send (CTS)
signal which causes the UART to pause after sending the
current frame (if any). The UART asserts the ready-to-send
(RTS) signal to the peripheral when it is ready to send a
character.
The UART module offers the following features:
18.2
Full-duplex double-buffered receiver/transmitter
Programmable baud rate
Programmable framing formats: 7, 8, or 9 data bits; even,
odd, or no parity; one or two stop bits (mark or space)
Hardware parity generation for data transmission and
parity check for data reception
Interrupts on “transmit ready” and “receive ready” conditions, separately enabled
Software-controlled break transmission and detection
Internal diagnostic capability
Automatic detection of parity, framing, and overrun errors
Hardware flow control (CTS and RTS signals)
DMA capability
UART OPERATION
The UART normally operates in asynchronous mode. There
are two special-purpose modes, called attention and diagnostic. This section describes the operating modes of the
UART.
18.2.1
Asynchronous Mode
The asynchronous mode of the UART enables the device to
communicate with other devices using just two communication signals: transmit and receive.
bs
ol
e
te
In asynchronous mode, the transmit shift register (TSFT)
and the transmit buffer (UTBUF) double-buffer the data for
transmission. To transmit a character, a data byte is loaded
in the UTBUF register. The data is then transferred to the
TSFT register. While the TSFT register is shifting out the
18.1
FUNCTIONAL OVERVIEW
current character (LSB first) on the TXD pin, the UTBUF
Figure 28 is a block diagram of the UART module showing
register is loaded by software with the next byte to be transthe basic functional units in the UART:
mitted. When TSFT finishes transmission of the last stop bit
Transmitter
of the current frame, the contents of UTBUF are transferred
Receiver
to the TSFT register and the Transmit Buffer Empty bit (UT Baud Rate Generator
BE) is set. The UTBE bit is automatically cleared by the
Control and Error Detection
UART when software loads a new character into the UTBUF
The Transmitter block consists of an 8-bit transmit shift reg- register. During transmission, the UXMIP bit is set high by
ister and an 8-bit transmit buffer. Data bytes are loaded in the UART. This bit is reset only after the UART has sent the
parallel from the buffer into the shift register and then shifted last stop bit of the current character and the UTBUF register
is empty. The UTBUF register is a read/write register. The
out serially on the TXD pin.
TSFT register is not software accessible.
The Receiver block consists of an 8-bit receive shift register
and an 8-bit receive buffer. Data is received serially on the In asynchronous mode, the input frequency to the UART is
RXD pin and shifted into the shift register. Once eight bits 16 times the baud rate. In other words, there are 16 clock
have been received, the contents of the shift register are cycles per bit time. In asynchronous mode, the baud rate
generator is always the UART clock source.
transferred in parallel to the receive buffer.
The receive shift register (RSFT) and the receive buffer
(URBUF) double buffer the data being received. The UART
receiver continuously monitors the signal on the RXD pin for
a low level to detect the beginning of a start bit. On sensing
The Baud Rate Generator generates the bit shift clock. It
this low level, the UART waits for seven input clock cycles
consists of two registers and a two-stage counter. The regand samples again three times. If all three samples still inisters are used to specify a prescaler value and a baud rate
dicate a valid low, then the receiver considers this to be a
divisor. The first stage of the counter divides the UART clock
valid start bit, and the remaining bits in the character frame
based on the value of the programmed prescaler to create
are each sampled three times, around the mid-bit position.
a slower clock. The second stage of the counter creates the
For any bit following the start bit, the logic value is found by
baud rate clock by dividing the output of the first stage
majority voting, i.e. the two samples with the same value debased on the programmed baud rate divisor.
fine the value of the data bit. Figure 29 illustrates the proThe Control and Error Detection block contains the UART cess of start bit detection and bit sampling.
control registers, control logic, error detection circuit, parity
Data bits are sensed by taking a majority vote of three samgenerator/checker, and interrupt generation logic. The conples latched near the midpoint of each baud (bit time). Nortrol registers and control logic determine the data format,
mally, the position of the samples within the baud is
mode of operation, clock source, and type of parity used.
determined automatically, but software can override the auThe error detection circuit generates parity bits and checks
tomatic selection by setting the USMD bit in the UMDSL2
for parity, framing, and overrun errors.
register and programming the USPOS register.
The Flow Control Logic block provides the capability for
Serial data input on the RXD pin is shifted into the RSFT
hardware handshaking between the UART and a peripheral
register. On receiving the complete character, the contents
device. When the peripheral device needs to stop the flow
O
The Transmitter and Receiver blocks both contain extensions for 9-bit data transfers, as required by the 9-bit and
loopback operating modes.
107
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CP3UB17
18.0 UART Module
CP3UB17
of the RSFT register are copied into the URBUF register from the URBUF register. The RSFT register is not software
and the Receive Buffer Full bit (URBF) is set. The URBF bit accessible.
is automatically reset when software reads the character
Transmitter
TXD
Baud Clock
RTS
Flow Control
Logic
System Clock
Internal Bus
CTS
Control and
Error Detection
Baud Rate
Generator
te
Parity
Generator/Checker
Baud Clock
Receiver
RXD
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DS163
Figure 28.
16
1
2
3
4
5
6
UART Block Diagram
7
8
9
11
12
13
14
15
2
O
1
18.2.2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
1
Sample
DATABIT
DS061
Figure 29.
UART Asynchronous Communication
Attention Mode
The Attention mode is available for networking this device
with other processors. This mode requires the 9-bit data format with no parity. The number of start bits and number of
stop bits are programmable. In this mode, two types of 9-bit
characters are sent on the network: address characters
consisting of 8 address bits and a 1 in the ninth bit position
and data characters consisting of 8 data bits and a 0 in the
ninth bit position.
While in Attention mode, the UART receiver monitors the
communication flow but ignores all characters until an address character is received. On receiving an address charwww.national.com
1
DATA (LSB)
STARTBIT
16
16
Sample
bs
Sample
10
acter, the contents of the receive shift register are copied to
the receive buffer. The URBF bit is set and an interrupt (if
enabled) is generated. The UATN bit is automatically
cleared, and the UART begins receiving all subsequent
characters. Software must examine the contents of the URBUF register and respond by accepting the subsequent
characters (by leaving the UATN bit reset) or waiting for the
next address character (by setting the UATN bit again).
The operation of the UART transmitter is not affected by the
selection of this mode. The value of the ninth bit to be transmitted is programmed by setting or clearing the UXB9 bit in
108
18.2.3
the control registers, called UXB9 and URB9. Parity is not
generated or verified in this mode.
Diagnostic Mode
The Diagnostic mode is available for testing of the UART. In
this mode, the TXD and RXD pins are internally connected
together, and data shifted out of the transmit shift register is
immediately transferred to the receive shift register. This
mode supports only the 9-bit data format with no parity. The
number of start and stop bits is programmable.
18.2.4
3a
Start
Bit
9-Bit Data
1a
Start
Bit
7-Bit Data
1b
Start
Bit
7-Bit Data
Start
Bit
7-Bit Data
18.2.5
1S
The relationship between the 5-bit prescaler select (UPSC)
setting and the prescaler factors is shown in Table 41.
Table 41 Prescaler Factors
2S
PA
1S
PA
2S
7-Bit Data Frame Options
bs
The format shown in Figure 31 consists of one start bit,
eight data bits (excluding parity), and one or two stop bits. If
parity bit generation is enabled by setting the UPEN bit, a
parity bit is generated and transmitted following the eight
data bits.
Start
Bit
8-Bit Data
1S
8-Bit Data
O
Start
Bit
2S
2b
Start
Bit
8-Bit Data
PA
2c
Start
Bit
8-Bit Data
PA
Figure 31.
Baud Rate Generator
The Baud Rate Generator creates the basic baud clock from
the System Clock. The System Clock is passed through a
two-stage divider chain consisting of a 5-bit baud rate prescaler (UPSC) and an 11-bit baud rate divisor (UDIV).
DS063
Figure 30.
2S
te
7-Bit Data
1S
Figure 32. 9-bit Data Frame Options
Prescaler Select
Prescaler Factor
00000
No clock
ol
e
Start
Bit
2a
9-Bit Data
Frame Format Selection
1
2
Start
Bit
DS065
The format shown in Figure 30 consists of a start bit, seven
data bits (excluding parity), and one or two stop bits. If parity
bit generation is enabled by setting the UPEN bit, a parity bit
is generated and transmitted following the seven data bits.
1c
3
1S
2S
DS064
8-Bit Data Frame Options
The format shown in Figure 32 consists of one start bit, nine
data bits, and one or two stop bits. This format also supports
the UART attention feature. When operating in this format,
all eight bits of UTBUF and URBUF are used for data. The
ninth data bit is transmitted and received using two bits in
109
00001
1
00010
1.5
00011
2
00100
2.5
00101
3
00110
3.5
00111
4
01000
4.5
01001
5
01010
5.5
01011
6
01100
6.5
01101
7
01110
7.5
01111
8
10000
8.5
10001
9
10010
9.5
10011
10
10100
10.5
10101
11
10110
11.5
10111
12
11000
12.5
11001
13
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CP3UB17
the UART Frame Select register. The value of the ninth bit
received is read from URB9 in the UART Status Register.
CP3UB17
In asynchronous mode, the baud rate is calculated by:
Table 41 Prescaler Factors (Continued)
Prescaler Select
Prescaler Factor
11010
13.5
11011
14
11100
14.5
11101
15
11110
15.5
11111
16
SYS_CLKBR = ----------------------------(O × N × P)
where BR is the baud rate, SYS_CLK is the System Clock
frequency, O is the oversample rate, N is the value of the
baud rate divisor + 1, and P is the prescaler divide factor selected by the value in the UPSR register.
18.2.6
Interrupts
The UART is capable of generating interrupts on:
Receive Buffer Full
Receive Error
Transmit Buffer Empty
A prescaler factor of zero corresponds to “no clock.” The “no
clock” condition is the UART power down mode, in which the
UART clock is turned off to reduce power consumption.
Software must select the “no clock” condition before entering a new baud rate. Otherwise, it could cause incorrect
data to be received or transmitted.
te
Figure 33 shows a diagram of the interrupt sources and associated enable bits.
UEEI
UFE
UDOE
UERR
RX
Interrupt
UPE
ol
e
UERI
URBF
UETI
UTBE
TX
Interrupt
bs
UEFCI
UDCTS
Figure 33.
FC
Interrupt
DS066
UART Interrupts
The interrupts can be individually enabled or disabled using
the Enable Transmit Interrupt (UETI), Enable Receive Interrupt (UERI), and Enable Receive Error Interrupt (UEER)
bits in the UICTRL register.
bit or read the UICTRL register (which clears the UDCTS
bit).
O
In addition to the dedicated inputs to the ICU for UART interrupts, the UART receive (RXD) and Clear To Send (CTS)
A transmit interrupt is generated when both the UTBE and signals are inputs to the MIWU (see Section 13.0), which
UETI bits are set. To remove this interrupt, software must ei- can be programmed to generate edge-triggered interrupts.
ther disable the interrupt by clearing the UETI bit or write to
18.2.7 DMA Support
the UTBUF register (which clears the UTBE bit).
The UART can operate with one or two DMA channels. Two
A receive interrupt is generated on these conditions:
DMA channels must be used for processor-independent
Both the URBF and UERI bits are set. To remove this in- full-duplex operation. Both receive and transmit DMA can
terrupt, software must either disable the interrupt by be enabled simultaneously.
clearing the UERI bit or read from the URBUF register
If transmit DMA is enabled (the UETD bit is set), the UART
(which clears the URBF bit).
generates a DMA request when the UTBE bit changes state
Both the UERR and the UEEI bits are set. To remove this
from clear to set. Enabling transmit DMA automatically disinterrupt, software must either disable the interrupt by
ables transmit interrupts, without regard to the state of the
clearing the UEEI bit or read the USTAT register (which
UETI bit.
clears the UERR bit).
If receive DMA is enabled (the UERD bit is set), the UART
A flow control interrupt is generated when both the UDCTS
generates a DMA request when the URBF bit changes state
and the UEFCI bits are set. To remove this interrupt, softfrom clear to set. Enabling receive DMA automatically disware must either disable the interrupt by clearing the UEFCI
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110
18.2.8
18.3.1
UART Receive Data Buffer (URBUF)
The URBUF register is a byte-wide, read/write register used
to receive each data byte.
Break Generation and Detection
7
0
A line break is generated when the UBRK bit is set in the
UMDSL1 register. The TXD line remains low until the program resets the UBRK bit.
URBUF
A line break is detected if RXD remains low for 10 bit times 18.3.2 UART Transmit Data Buffer (UTBUF)
or longer after a missing stop bit is detected.
The UTBUF register is a byte-wide, read/write register used
to transmit each data byte.
18.2.9 Parity Generation and Detection
te
Parity is only generated or checked with the 7-bit and 8-bit
7
0
data formats. It is not generated or checked in the diagnostic
loopback mode, the attention mode, or in normal mode with
UTBUF
the 9-bit data format. Parity generation and checking are enabled and disabled using the PEN bit in the UFRS register.
The UPSEL bits in the UFRS register are used to select 18.3.3 UART Baud Rate Prescaler (UPSR)
odd, even, or no parity.
The UPSR register is a byte-wide, read/write register that
contains the 5-bit clock prescaler and the upper three bits of
18.3
UART REGISTERS
the baud rate divisor. This register is cleared upon reset.
Software interacts with the UART by accessing the UART
The register format is shown below.
registers. There are eight registers, as listed in Table 42.
Table 42 UART Registers
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Address
URBUF
FF FE42h
UTBUF
FF FE40h
UPSR
FF FE4Eh
Description
UART Receive Data
Buffer
UPSC
UART Transmit Data
Buffer
UART Baud Rate
Prescaler
UDIV10:8
bs
Name
FF FE4Ch
UART Baud Rate
Divisor
UFRS
FF FE48h
UART Frame Select
Register
UMDSL1
FF FE4Ah
UART Mode Select
Register 1
O
UBAUD
3
UPSC
USTAT
FF FE46h
UART Status Register
UICTRL
FF FE44h
UART Interrupt Control
Register
UOVR
FF FE50h
UART Oversample
Rate Register
UMDSL2
FF FE52h
UART Mode Select
Register 2
USPOS
FF FE54h
UART Sample
Position Register
18.3.4
2
0
UDIV10:8
The Prescaler field specifies the prescaler value used for dividing the System Clock in the
first stage of the two-stage divider chain. For
the prescaler factors corresponding to each 5bit value, see Table 41.
The Baud Rate Divisor field holds the three
most significant bits (bits 10, 9, and 8) of the
UART baud rate divisor used in the second
stage of the two-stage divider chain. The remaining bits of the baud rate divisor are held
in the UBAUD register.
UART Baud Rate Divisor (UBAUD)
The UBAUD register is a byte-wide, read/write register that
contains the lower eight bits of the baud rate divisor. The
register contents are unknown at power-up and are left unchanged by a reset operation. The register format is shown
below.
7
0
UDIV7:0
UDIV7:0
111
The Baud Rate Divisor field holds the eight
lowest-order bits of the UART baud rate divisor used in the second stage of the two-stage
divider chain. The three most significant bits
are held in the UPSR register. The divisor value used is (UDIV[10:0] + 1).
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CP3UB17
ables receive interrupts, without regard to the state of the
UERI bit. However, receive error interrupts should be enabled (the UEEI bit is set) to allow detection of receive errors
when DMA is used.
CP3UB17
18.3.5
UART Frame Select Register (UFRS)
18.3.6
The UFRS register is a byte-wide, read/write register that
controls the frame format, including the number of data bits,
number of stop bits, and parity type. This register is cleared
upon reset. The register format is shown below.
7
6
Reserved UPEN
5
4
UPSEL
3
2
UXB9
USTP
1
UART Mode Select Register 1 (UMDSL1)
The UMDSL1 register is a byte-wide, read/write register that
selects the clock source, synchronization mode, attention
mode, and line break generation. This register is cleared at
reset. When software writes to this register, the reserved
bits must be written with 0 for proper operation. The register
format is shown below.
0
UCHAR
7
6
5
4
3
2
1
URTS UFCE UERD UETD Res. UBRK UATN
UPSEL
O
UPEN
UBRK
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UETD
UERD
UFCE
URTS
112
Res.
The Attention Mode bit is used to enable Attention mode. When set, this bit selects the attention mode of operation for the UART. When
clear, the attention mode is disabled. The
hardware clears this bit after an address
frame is received. An address frame is a 9-bit
character with a 1 in the ninth bit position.
0 – Attention mode disabled.
1 – Attention mode enabled.
The Force Transmission Break bit is used to
force the TXD output low. Setting this bit to 1
causes the TXD pin to go low. TXD remains
low until the UBRK bit is cleared by software.
0 – Normal operation.
1 – TXD pin forced low.
The Enable Transmit DMA bit controls whether DMA is used for UART transmit operations.
Enabling transmit DMA automatically disables
transmit interrupts, without regard to the state
of the UETI bit.
0 – Transmit DMA disabled.
1 – Transmit DMA enabled.
The Enable Receive DMA bit controls whether
DMA is used for UART receive operations.
Enabling receive DMA automatically disables
receive interrupts, without regard to the state
of the UERI bit. Receive error interrupts are
unaffected by the UERD bit.
0 – Receive DMA disabled.
1 – Receive DMA enabled.
The Flow Control Enable bit controls whether
flow control interrupts are enabled.
0 – Flow control interrupts disabled.
1 – Flow control interrupts enabled.
The Ready To Send bit directly controls the
state of the RTS output.
0 – RTS output is high.
1 – RTS output is low.
te
UXB9
UATN
ol
e
USTP
The Character Frame Format field selects the
number of data bits per frame, not including
the parity bit, as follows:
00 – 8 data bits per frame.
01 – 7 data bits per frame.
10 – 9 data bits per frame.
11 – Loop-back mode, 9 data bits per frame.
The Stop Bits bit specifies the number of stop
bits transmitted in each frame. If this bit is 0,
one stop bit is transmitted. If this bit is 1, two
stop bits are transmitted.
0 – One stop bit per frame.
1 – Two stop bits per frame.
The Transmit 9th Data Bit holds the value of
the ninth data bit, either 0 or 1, transmitted
when the UART is configured to transmit nine
data bits per frame. It has no effect when the
UART is configured to transmit seven or eight
data bits per frame.
The Parity Select field selects the treatment of
the parity bit. When the UART is configured to
transmit nine data bits per frame, the parity bit
is omitted and the UPSEL field is ignored.
00 – Odd parity.
01 – Even parity.
10 – No parity, transmit 1 (mark).
11 – No parity, transmit 0 (space).
The Parity Enable bit enables or disables parity generation and parity checking. When the
UART is configured to transmit nine data bits
per frame, there is no parity bit and the UPEN
bit is ignored.
0 – Parity generation and checking disabled.
1 – Parity generation and checking enabled.
bs
UCHAR
0
UART Status Register (USTAT)
UXMIP
The USTAT register is a byte-wide, read-only register that
contains the receive and transmit status bits. This register is
cleared upon reset. Any attempt by software to write to this
register is ignored. The register format is shown below.
UFE
UDOE
UERR
3
2
1
0
18.3.8
UXMIP URB9 UBKD UERR UDOE UFE UPE
UART Interrupt Control Register (UICTRL)
The UICTRL register is a byte-wide register that contains
the receive and transmit interrupt status bits (read-only bits)
The Parity Error bit indicates whether a parity and the interrupt enable bits (read/write bits). The register is
error is detected within a received character. initialized to 01h at reset. The register format is shown beThis bit is automatically cleared by the hard- low.
ware when the USTAT register is read.
0 – No parity error occurred.
7
6
5
4
3
2
1
0
1 – Parity error occurred.
UEEI UERI UETI UEFCI UCTS UDCTS URBF UTBE
The Framing Error bit indicates whether the
UART fails to receive a valid stop bit at the end
of a frame. This bit is automatically cleared by
UTBE
The Transmit Buffer Empty bit is set by hardthe hardware when the USTAT register is
ware when the UART transfers data from the
read.
UTBUF register to the transmit shift register
0 – No framing error occurred.
for transmission. It is automatically cleared by
1 – Framing error occurred.
the hardware on the next write to the UTBUF
The Data Overrun Error bit is set when a new
register.
character is received and transferred to the
0 – Transmit buffer is loaded.
URBUF register before software has read the
1 – Transmit buffer is empty.
previous character from the URBUF register.
URBF
The Receive Buffer Full bit is set by hardware
This bit is automatically cleared by the hardwhen the UART has received a complete data
ware when the USTAT register is read.
frame and has transferred the data from the
0 – No receive overrun error occurred.
receive shift register to the URBUF register. It
1 – Receive overrun error occurred.
is automatically cleared by the hardware
The Error Status bit indicates when a parity,
when the URBUF register is read.
framing, or overrun error occurs (any time that
0 – Receive buffer is empty.
the UPE, UFE, or UDOE bit is set). It is auto1 – Receive buffer is loaded.
matically cleared by the hardware when the
UDCTS
The Delta Clear To Send bit indicates whether
UPE, UFE, and UDOE bits are all 0.
the CTS input has changed state since the
0 – No receive error occurred.
CPU last read this register.
1 – Receive error occurred.
0 – No change since last read.
The Break Detect bit indicates when a line
1 – State has changed since last read.
break condition occurs. This condition is deUCTS
The Clear To Send bit indicates the state on
tected if RXD remains low for at least ten bit
the CTS input.
times after a missing stop bit has been detect0 – CTS input is high.
ed at the end of a frame. The hardware auto1 – CTS input is low.
matically clears the UBKD bit upon read of the
UEFCI
The Enable Flow Control Interrupt bit controls
USTAT register, but only if the break condition
whether a flow control interrupt is generated
on RXD no longer exists. If reading the USTAT
when the UDCTS bit changes from clear to
register does not clear the UBKD bit because
set.
the break is still actively driven on the line, the
0 – Flow control interrupt disabled.
hardware clears the bit as soon as the break
1 – Flow control interrupt enabled.
condition no longer exists (when the RXD inUETI
The Enable Transmitter Interrupt bit, when
put returns to a high level).
set, enables generation of an interrupt when
0 – No break condition occurred.
the hardware sets the UTBE bit.
1 – Break condition occurred.
0 – Transmit buffer empty interrupt disabled.
The Received 9th Data Bit holds the ninth
1 – Transmit buffer empty interrupt enabled.
data bit, when the UART is configured to opUERI
The Enable Receiver Interrupt bit, when set,
erate in the 9-bit data format.
enables generation of an interrupt when the
hardware sets the URBF bit.
0 – Receive buffer full interrupt disabled.
1 – Receive buffer full interrupt enabled.
O
UBKD
4
te
UPE
5
ol
e
Res.
6
bs
7
The Transmit In Progress bit indicates when
the UART is transmitting. The hardware sets
this bit when the UART is transmitting data
and clears the bit at the end of the last frame
bit.
0 – UART is not transmitting.
1 – UART is transmitting.
URB9
113
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CP3UB17
18.3.7
CP3UB17
UEEI
18.3.9
The Enable Receive Error Interrupt bit, when
set, enables generation of an interrupt when
the hardware sets the UERR bit in the USTAT
register.
0 – Receive error interrupt disabled.
1 – Receive error interrupt enabled.
18.3.11 UART Sample Position Register (USPOS)
The USPOS register is a byte-wide, read/write register that
specifies the sample position when the USMD bit in the
UMDSL2 register is set. At reset, the USPOS register is initialized to 06h. The register format is shown below.
UART Oversample Rate Register (UOVR)
7
The UOVR register is a byte-wide, read/write register that
specifies the oversample rate. At reset, the UOVR register
is cleared. The register format is shown below.
4
3
UOVSR
The Oversampling Rate field specifies the
oversampling rate, as given in the following table.
UOVSR3:0
Oversampling Rate
0000–0110
16
0111
7
1000
1001
1010
1011
1100
Sample Position
2
3
7
2
3
4
9
8
2
3
4
10
9
3
4
5
11
10
3
4
5
12
11
4
5
6
13
12
4
5
6
1110
14
13
5
6
7
1111
15
14
5
6
7
15
6
7
8
16
6
7
8
O
The UMDSL2 register is a byte-wide, read/write register that
controls the sample mode used to recover asynchronous
data. At reset, the UOVR register is cleared. The register
format is shown below.
7
Reserved
1
0
USMD
The USMD bit controls the sample mode for
asynchronous transmission.
0 – UART determines the sample position automatically.
1 – The USPOS register determines the sample position.
www.national.com
1
8
18.3.10 UART Mode Select Register 2 (UMDSL2)
USMD
The Sample Position field specifies the oversample clock period at which to take the first
of three samples for sensing the value of data
bits. The clocks are numbered starting at 0
and may range up to 15 for 16× oversampling.
The maximum value for this field is (oversampling rate - 3). The table below shows the
clock period at which each of the three samples is taken, when automatic sampling is enabled (UMDSL2.USMD = 0).
Oversampling Rate
bs
1101
USAMP
ol
e
UOVSR
0
0
te
Reserved
3
Reserved
USAMP
7
4
114
The USAMP field may be used to override the
automatic selection, to choose any other clock
period at which to start taking the three samples.
BAUD RATE CALCULATIONS
The N × P term is then divided by each Prescaler Factor
from Table 41 to obtain a value closest to an integer. The
factor for this example is 6.5.
The UART baud rate is determined by the System Clock frequency and the values in the UOVR, UPSR, and UBAUD
registers. Unless the System Clock is an exact multiple of
the baud rate, there will be a small amount of error in the resulting baud rate. The equation to calculate the baud rate is:
N = 32.552
------------------ = 5.008 (N = 5)
6.5
The baud rate register is programmed with a baud rate divisor of 4 (N = baud rate divisor + 1). This produces a baud
clock of:
SYS_CLKBR = ----------------------------(O × N × P)
where BR is the baud rate, SYS_CLK is the System Clock,
O is the oversample rate, N is the baud rate divisor + 1, and
P is the prescaler divisor selected by the UPSR register.
6
( 5 ×10 )
= 9615.385
BR = ----------------------------------( 16 × 5 × 6.5 )
9615.385 – 9600 )- = 0.16
%error = (-----------------------------------------------9600
Assuming a System Clock of 5 MHz, a desired baud rate of
9600, and an oversample rate of 16, the N × P term according to the equation above is:
Note that the percent error is much lower than would be possible without the non-integer prescaler factor. Error greater
than 3% is marginal and may result in unreliable operation.
Refer to Table 43 below for more examples.
6
te
( 5 ×10 ) - = 32.552
N × P = -----------------------------( 16 × 9600 )
Table 43 Baud Rate Programming
SYS_CLK = 48 MHz
SYS_CLK = 24 MHz
SYS_CLK = 12 MHz
SYS_CLK = 10 MHz
O
N
P
%err
O
N
P
%err
O
N
P
%err
O
N
P
%err
300
16
2000
5.0
0.00
16
2000
2.5
0.00
16
1250
2.0
0.00
13
1282
2.0
0.00
600
16
2000
2.5
0.00
16
1250
2.0
0.00
16
1250
1.0
0.00
13
1282
1.0
0.00
1200
16
1250
2.0
0.00
16
1250
1.0
0.00
16
625
1.0
0.00
13
641
1.0
0.00
1800
7
401
9.5
0.00
8
1111
1.5
0.01
12
101
5.5
0.01
12
463
1.0
0.01
2000
16
1500
1.0
0.00
16
750
1.0
0.00
16
250
1.5
0.00
16
125
2.5
0.00
2400
16
1250
1.0
0.00
16
625
1.0
0.00
16
125
2.5
0.00
9
463
1.0
0.01
3600
8
1111
1.5
0.01
12
101
5.5
0.01
11
202
1.5
0.01
11
101
2.5
0.01
4800
16
625
1.0
0.00
16
125
2.5
0.00
10
250
1.0
0.00
7
119
2.5
0.04
7200
12
101
5.5
0.01
11
303
1.0
0.01
11
101
1.5
0.01
10
139
1.0
0.08
9600
16
125
2.5
0.00
10
250
1.0
0.00
10
125
1.0
0.00
7
149
1.0
0.13
14400
11
202
1.5
0.01
11
101
1.5
0.01
14
17
3.5
0.04
14
33
1.5
0.21
19200
10
250
1.0
0.00
10
125
1.0
0.00
10
25
2.5
0.00
16
13
2.5
0.16
38400
10
125
1.0
0.00
10
25
2.5
0.00
16
13
1.5
0.16
8
13
2.5
0.16
56000
7
49
2.5
0.04
13
33
1.0
0.10
13
11
1.5
0.10
7
17
1.5
0.04
115200
7
17
3.5
0.04
13
16
1.0
0.16
13
8
1.0
0.16
7
5
2.5
0.79
128000
15
25
1.0
0.00
15
5
2.5
0.00
11
1
8.5
0.27
12
1
6.5
0.16
230400
13
16
1.0
0.16
13
8
1.0
0.16
13
4
1.0
0.16
11
4
1.0
1.36
345600
9
1
15.5 0.44
10
7
1.0
0.79
10
1
3.5
0.79
460800
13
8
1.0
0.16
13
4
1.0
0.16
13
2
1.0
0.16
11
2
1.0
1.36
576000
8
7
1.5
0.79
12
1
3.5
0.79
14
1
1.5
0.79
7
1
2.5
0.79
691200
10
7
1.0
0.79
10
1
3.5
0.79
7
1
2.5
0.79
806400
7
1
8.5
0.04
15
2
1.0
0.79
10
1
1.5
0.79
921600
13
4
1.0
0.16
13
2
1.0
0.16
13
1
1.0
0.16
1105920
11
4
1.0
1.36
11
2
1.0
1.36
9
1
1.0
0.47
1382400
10
1
3.5
0.79
7
1
2.5
0.79
1536000
9
1
3.5
0.79
8
2
1.0
2.34
O
bs
ol
e
Baud
Rate
115
www.national.com
CP3UB17
18.4
SYS_CLK = 8 MHz
SYS_CLK = 6 MHz
SYS_CLK = 5 MHz
SYS_CLK = 4 MHz
O
N
P
%err
O
N
P
%err
O
N
P
%err
O
N
P
%err
300
7
401
9.5
0.00
16
1250
1.0
0.00
11
202
7.5
0.01
12
202
5.5
0.01
600
12
1111
1.0
0.01
16
625
1.0
0.00
11
101
7.5
0.01
12
101
5.5
0.01
1200
12
101
5.5
0.01
16
125
2.5
0.00
10
119
3.5
0.04
11
202
1.5
0.01
1800
8
101
5.5
0.01
11
303
1.0
0.01
11
101
2.5
0.01
11
202
1.0
0.01
2000
16
250
1.0
0.00
16
125
1.5
0.00
10
250
1.0
0.00
16
125
1.0
0.00
2400
11
303
1.0
0.01
10
250
1.0
0.00
7
119
2.5
0.04
11
101
1.5
0.01
3600
11
202
1.0
0.01
11
101
1.5
0.01
10
139
1.0
0.08
11
101
1.0
0.01
4800
11
101
1.5
0.01
10
125
1.0
0.00
7
149
1.0
0.13
14
17
3.5
0.04
7200
11
101
1.0
0.01
14
17
3.5
0.04
14
33
1.5
0.21
15
37
1.0
0.10
9600
14
17
3.5
0.04
10
25
2.5
0.00
16
13
2.5
0.16
7
17
3.5
0.04
14400
15
37
1.0
0.10
7
17
3.5
0.04
7
33
1.5
0.21
9
31
1.0
0.44
19200
7
17
3.5
0.04
16
13
1.5
0.16
8
13
2.5
0.16
16
13
1.0
0.16
38400
16
13
1.0
0.16
8
13
1.5
0.16
13
10
1.0
0.16
16
1
6.5
0.16
56000
13
11
1.0
0.10
9
12
1.0
0.79
15
6
1.0
0.79
13
1
5.5
0.10
115200
10
7
1.0
0.79
13
4
1.0
0.16
11
4
1.0
1.36
10
1
3.5
0.79
128000
9
7
1.0
0.79
16
3
1.0
2.34
13
3
1.0
0.16
9
1
3.5
0.79
230400
10
1
3.5
0.79
13
2
1.0
0.16
11
2
1.0
1.36
7
1
2.5
0.79
345600
15
1
1.5
2.88
7
1
2.5
0.79
460800
7
1
2.5
0.79
13
1
1.0
0.16
576000
7
2
1.0
0.79
7
1
1.5
0.79
ol
e
te
Baud
Rate
SYS_CLK = 3 MHz
SYS_CLK = 2 MHz
SYS_CLK = 1 MHz
SYS_CLK = 500 kHz
O
N
P
%err
O
N
P
%err
O
N
P
%err
O
N
P
%err
300
16
250
2.5
0.00
12
101
5.5
0.01
11
202
1.5
0.01
11
101
1.5
0.01
600
16
125
2.5
0.00
11
202
1.5
0.01
11
101
1.5
0.01
14
17
3.5
0.04
1200
10
250
1.0
0.00
11
101
1.5
0.01
14
17
3.5
0.04
7
17
3.5
0.04
1800
11
101
1.5
0.01
11
101
1.0
0.01
15
37
1.0
0.10
9
31
1.0
0.44
bs
Baud
Rate
O
CP3UB17
Table 44 Baud Rate Programming
2000
15
100
1.0
0.00
16
25
2.5
0.00
10
50
1.0
0.00
10
25
1.0
0.00
2400
10
125
1.0
0.00
14
17
3.5
0.04
7
17
3.5
0.04
16
13
1.0
0.16
3600
14
17
3.5
0.04
15
37
1.0
0.10
9
31
1.0
0.44
9
1
15.5 0.44
4800
10
25
2.5
0.00
7
17
3.5
0.04
16
13
1.0
0.16
16
1
6.5
0.16
7200
7
17
3.5
0.04
9
31
1.0
0.44
9
1
15.5 0.44
10
7
1.0
0.79
9600
16
13
1.5
0.16
16
13
1.0
0.16
16
1
6.5
0.16
8
1
6.5
0.16
14400
13
16
1.0
0.16
9
1
15.5 0.44
10
7
1.0
0.79
10
1
3.5
0.79
19200
8
13
1.5
0.16
16
1
6.5
0.16
8
1
6.5
0.16
13
2
1.0
0.16
38400
13
6
1.0
0.16
8
1
6.5
0.16
13
2
1.0
0.16
13
1
1.0
0.16
56000
9
6
1.0
0.79
9
4
1.0
0.79
9
2
1.0
0.79
115200
13
2
1.0
0.16
7
1
2.5
0.79
128000
16
1
1.5
2.34
8
2
1.0
2.34
230400
13
1
1.0
0.16
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116
Microwire/Plus is a synchronous serial communications
protocol, originally implemented in National Semiconductor's COP8® and HPC families of microcontrollers to minimize the number of connections, and therefore the cost, of
communicating with peripherals.
The CP3UB17 has an enhanced Microwire/SPI interface
module (MWSPI) that can communicate with all peripherals
that conform to Microwire or Serial Peripheral Interface
(SPI) specifications. This enhanced Microwire interface is
capable of operating as either a master or slave and in 8- or
16-bit mode. Figure 34 shows a typical enhanced Microwire
interface application.
MWCS
GPIO
Master
DO
CS
CS
CS
8-Bit
A/D
1K Bit
EEPROM
LCD
Display
Driver
VF
Display
Driver
SK
DI
DO
SK
DI
SK
MDIDO
ol
e
MSK
DS067
bs
Programmable operation as a Master or Slave
Programmable shift-clock frequency (master only)
Programmable 8- or 16-bit mode of operation
8- or 16-bit serial I/O data shift register
Two modes of clocking data
Serial clock can be low or high when idle
16-bit read buffer
Busy bit, Read Buffer Full bit, and Overrun bit for polling
and as interrupt sources
Supports multiple masters
Maximum bit rate of 10M bits/second (master mode) 5M
bits/second (slave mode) at 20 MHz System Clock
Supports very low-end slaves with the Slave Ready output
Echo back enable/disable (Slave only)
The three-wire system includes: the serial data in signal
(MDIDO for master mode, MDODI for slave mode), the serial data out signal (MDODI for master mode, MDIDO for
slave mode), and the serial clock (MSK).
In slave mode, an optional fourth signal (MWCS) may be
used to enable the slave transmit. At any given time, only
one slave can respond to the master. Each slave device has
its own chip select signal (MWCS) for this purpose.
Figure 35 shows a block diagram of the enhanced Microwire
serial interface in the device.
O
DI
Microwire Interface
The enhanced Microwire interface module includes the following features:
SK
MDODI
Figure 34.
DI
I/O
Lines
MDIDO
MDODI
MSK
Slave
te
I/O
Lines
CS
19.1
MICROWIRE OPERATION
The Microwire interface allows several devices to be connected on one three-wire system. At any given time, one of
these devices operates as the master while all other devices
operate as slaves. The Microwire interface allows the device
to operate either as a master or slave transferring 8- or 16bits of data.
The master device supplies the synchronous clock (MSK)
for the serial interface and initiates the data transfer. The
slave devices respond by sending (or receiving) the requested data. Each slave device uses the master’s clock for
serially shifting data out (or in), while the master shifts the
data in (or out).
117
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CP3UB17
19.0 Microwire/SPI Interface
CP3UB17
Interrupt
Request
Control + Status
Write
Data
MWCS
16-BIt Read Buffer
Write
Data
8
8 MWDAT
16-BIt Shift Register
Data Out
Slave
Master
te
MDODI
Slave
Data In
Master
MDIDO
MSK
ol
e
System
Clock
Clock Prescaler + Select
Master
Figure 35.
19.1.1
Shifting
MSK
Microwire Block Diagram
bs
The Microwire interface is a full duplex transmitter/receiver.
A 16-bit shifter, which can be split into a low and high byte,
is used for both transmitting and receiving. In 8-bit mode,
only the lower 8-bits are used to transfer data. The transmitted data is shifted out through MDODI pin (master mode) or
MDIDO pin (slave mode), starting with the most significant
bit. At the same time, the received data is shifted in through
MDIDO pin (master mode) or MDODI pin (slave mode), also
starting with the most significant bit first.
O
The shift in and shift out are controlled by the MSK clock. In
each clock cycle of MSK, one bit of data is transmitted/received. The 16-bit shifter is accessible as the MWDAT register. Reading the MWDAT register returns the value in the
read buffer. Writing to the MWDAT register updates the 16bit shifter.
19.1.2
Reading
DS068
The “Receive Buffer Full” (RBF) bit indicates if the MWDAT
register holds valid data. The OVR bit indicates that an overrun condition has occurred.
19.1.3
Writing
The “Microwire Busy” (BSY) bit indicates whether the MWDAT register can be written. All write operations to the MWDAT register update the shifter while the data contained in the
read buffer is not affected. Undefined results will occur if the
MWDAT register is written to while the BSY bit is set.
19.1.4
Clocking Modes
Two clocking modes are supported: the normal mode and
the alternate mode.
In the normal mode, the output data, which is transmitted on
the MDODI pin (master mode) or the MDIDO pin (slave
mode), is clocked out on the falling edge of the shift clock
MSK. The input data, which is received via the MDIDO pin
(master mode) or the MDODI pin (slave mode), is sampled
on the rising edge of MSK.
The enhanced Microwire interface implements a double
buffer on read. As illustrated in Figure 35, the double read
buffer consists of the 16-bit shifter and a buffer, called the In the alternate mode, the output data is shifted out on the
rising edge of MSK on the MDODI pin (master mode) or
read buffer.
MDIDO pin (slave mode). The input data, which is received
The 16-bit shifter loads the read buffer with new data when
via MDIDO pin (master mode) or MDODI pin (slave mode),
the data transfer sequence is completed and previous data
is sampled on the falling edge of MSK.
in the read buffer has been read. In master mode, an Overrun error occurs when the read buffer is full, the 16-bit shifter The clocking modes are selected with the MSKM bit. The
SCIDL bit allows selection of the value of MSK when it is idle
is full and a new data transfer sequence starts.
(when there is no data being transferred). Various MSK
When 8-bit mode is selected, the lower byte of the shift regclock frequencies can be programmed via the MCDV bits.
ister is loaded into the lower byte of the read buffer and the
Figures 27, 28, 29, and 30 show the data transfer timing for
read buffer’s higher byte remains unchanged.
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118
MASTER MODE
In Master mode, the MSK pin is an output for the shift clock,
MSK. When data is written to the (MWDAT register), eight
or sixteen MSK clocks, depending on the mode selected,
are generated to shift the 8 or 16 bits of data and then MSK
goes idle again. The MSK idle state can be either high or
low, depending on the SCIDL bit.
Note that when data is shifted out on MDODI (master mode)
or MDIDO (slave mode) on the leading edge of the MSK
clock, bit 14 (16-bit mode) is shifted out on the second leading edge of the MSK clock. When data are shifted out on
MDODI (master mode) or MDIDO (slave mode) on the trailing edge of MSK, bit 14 (16-bit mode) is shifted out on the
first trailing edge of MSK.
End of Transfer
MSK
Shift
Out
Data Out
MSB
MSB - 1
MSB - 2
MSB - 1
MSB - 2
MSB
te
Sample
Point
Data In
Bit 0
(LSB)
Bit 1
Bit 0
(LSB)
Bit 1
DS069
MSK
Shift
Out
MSB
Data Out
Normal Mode (SCIDL = 0)
ol
e
Figure 36.
MSB - 1
MSB - 2
End of Transfer
Bit 1
Bit 0
(LSB)
Bit 1
Bit 0
(LSB)
bs
Sample
Point
MSB
Data In
MSB - 1
O
Figure 37.
MSB - 2
DS070
Normal Mode (SCIDL = 1)
End of Transfer
MSK
Shift
Out
Data Out
MSB
MSB - 1
MSB - 2
Bit 1
Bit 0
(LSB)
MSB - 1
MSB - 2
Bit 1
Bit 0
(LSB)
Sample
Point
Data In
MSB
DS071
Figure 38. Alternate Mode (SCIDL = 0)
119
www.national.com
CP3UB17
19.2
the normal and the alternate modes with the SCIDL bit
equal to 0 and equal to 1.
CP3UB17
End of Transfer
MSK
Shift
Out
Data Out
MSB
MSB - 1
MSB - 2
Bit 1
Bit 0
(LSB)
MSB - 1
MSB - 2
Bit 1
Bit 0
(LSB)
Sample
Point
Data In
MSB
DS072
Figure 39. Alternate Mode (SCIDL = 1)
SLAVE MODE
In Slave mode, the MSK pin is an input for the shift clock
MSK. MDIDO is placed in TRI-STATE mode when MWCS is
inactive. Data transfer is enabled when MWCS is active.
EIO
OVR = 1
EIR
ol
e
The slave starts driving MDIDO when MWCS is activated.
The most significant bit (lower byte in 8-bit mode or upper
byte in 16-bit mode) is output onto the MDIDO pin first. After
eight or sixteen clocks (depending on the selected mode),
the data transfer is completed.
Figure 40 illustrates the various interrupt capabilities of this
module.
te
19.3
19.4
bs
If a new shift process starts before MWDAT was written, i.e.,
while MWDAT does not contain any valid data, and the
“Echo Enable” (ECHO) bit is set, the data received from
MDODI is transmitted on MDIDO in addition to being shifted
to MWDAT. If the ECHO bit is clear, the data transmitted on
MDIDO is the data held in the MWDAT register, regardless
of its validity. The master may negate the MWCS signal to
synchronize the bit count between the master and the slave.
In the case that the slave is the only slave in the system,
MWCS can be tied to VSS.
19.5
INTERRUPT GENERATION
An interrupt is generated in any of the following cases:
MWSPI
Interrupt
RBF = 1
EIW
BSY = 0
Figure 40.
DS073
MWSPI Interrupts
MICROWIRE INTERFACE REGISTERS
Software interacts with the Microwire interface by accessing
the Microwire registers. There are three such registers:
Table 45 Microwire Interface Registers
O
When the read buffer is full (RBF = 1) and the “Enable Interrupt for Read” bit is set (EIR = 1).
Whenever the shifter is not busy, i.e. the BSY bit is clear
(BSY = 0) and the “Enable Interrupt for Write” bit is set
(EIW = 1).
When an overrun condition occurs (OVR is set) and the
“Enable Interrupt on Overrun” bit is set (MEIO = 1). This
usage is restricted to master mode.
In addition, MWCS is an input to the MIWU (see
Section 13.0), which can be programmed to generate an
edge-triggered interrupt.
Name
Address
Description
MWDAT
FF FE60h
Microwire Data
Register
MWCTL1
FF FE62h
Microwire Control
Register
MWSTAT
FF FE64h
Microwire Status
Register
19.5.1
Microwire Data Register (MWDAT)
The MWDAT register is a word-wide, read/write register
used to transmit and receive data through the MDODI and
MDIDO pins. Figure 41 shows the hardware structure of the
register.
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120
CP3UB17
MWDAT
Write
Shifter
(Low Byte)
DIN
Shifter
(High Byte)
1
DOUT
0
Read Buffer
(Low Byte)
Read Buffer
(High Byte)
MOD
Read
DS074
19.5.2
MWDAT Register
Microwire Control Register (MWCTL1)
MNS
7
6
5
4
EIW
EIR
EIO
15
2
1
MOD
0
MNS MWEN
8
ECHO
bs
SCIDL
The Microwire Enable bit controls whether the
Microwire interface module is enabled.
0 – Microwire module disabled.
1 – Microwire module enabled.
Clearing this bit disables the module, clears
the status bits in the Microwire status register
(the BSY, RBF, and OVR bits in MWSTAT),
and places the Microwire interface pins in the
states described below.
O
MWEN
3
ECHO MOD
9
SCDV
Pin
MSK
The Master/Slave Select bit controls whether
the CP3UB17 is a master or slave. When
clear, the device operates as a slave. When
set, the device operates as the master.
0 – CP3UB17 is slave.
1 – CP3UB17 is master.
The Mode Select bit controls whether 8- or 16bit mode is used. When clear, the device operates in 8-bit mode. When set, the device operates in 16-bit mode. This bit must only be
changed when the module is disabled or idle
(MWSTAT.BSY = 0).
0 – 8-bit mode.
1 – 16-bit mode.
The Echo Back bit controls whether the echo
back function is enabled in slave mode. This
bit must be written only when the Microwire interface is idle (MWSTAT.BSY=0). The ECHO
bit is ignored in master mode. The MWDAT
register is valid from the time the register has
been written until the end of the transfer. In the
echo back mode, MDODI is transmitted (echoed back) on MDIDO if the MWDAT register
does not contain any valid data. With the echo
back function disabled, the data held in the
MWDAT register is transmitted on MDIDO,
whether or not the data is valid.
0 – Echo back disabled.
1 – Echo back enabled.
The Enable Interrupt on Overrun bit enables
or disables the overrun error interrupt. When
set, an interrupt is generated when the Receive Overrun Error bit (MWSTAT.OVR) is set.
Otherwise, no interrupt is generated when an
overrun error occurs. This bit must only be enabled in master mode.
0 – Disable overrun error interrupts.
1 – Enable overrun error interrupts.
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The MWCTL1 register is a word-wide, read/write register
used to control the Microwire module. To avoid clock glitches, the MWEN bit must be clear while changing the states
of any other bits in the register. At reset, all non-reserved
bits are cleared. The register format is shown below.
SCM
te
Figure 41.
State When Disabled
Master – SCIDL Bit
Slave – Input
MWCS
Input
MDIDO
Master – Input
Slave – TRI-STATE
MDODI
Master – Known value
Slave – Input
EIO
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SCIDL
O
SCDV
Microwire Status Register (MWSTAT)
The MWSTAT register is a word-wide, read-only register
that shows the current status of the Microwire interface
module. At reset, all non-reserved bits are clear. The register format is shown below.
15
3
Reserved
BSY
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2
1
0
OVR
RBF
BSY
The Busy bit, when set, indicates that the Microwire shifter is busy. In master mode, the
BSY bit is set when the MWDAT register is
written. In slave mode, the bit is set on the first
leading edge of MSK when MWCS is asserted or when the MWDAT register is written,
whichever occurs first. In both master and
slave modes, this bit is cleared when the Microwire data transfer sequence is completed
and the read buffer is ready to receive the new
data; in other words, when the previous data
held in the read buffer has already been read.
If the previous data in the read buffer has not
been read and new data has been received
into the shift register, the BSY bit will not be
cleared, as the transfer could not be completed because the contents of the shift register
could not be transferred into the read buffer.
0 – Microwire shifter is not busy.
1 – Microwire shifter is busy.
The Read Buffer Full bit, when set, indicates
that the Microwire read buffer is full and ready
to be read by software. It is set when the
shifter loads the read buffer, which occurs
upon completion of a transfer sequence if the
read buffer is empty. The RBF bit is updated
when the MWDAT register is read. At that
time, the RBF bit is cleared if the shifter does
not contain any new data (in other words, the
shifter is not receiving data or has not yet received a full byte of data). The RBF bit remains set if the shifter already holds new data
at the time that MWDAT is read. In that case,
MWDAT is immediately reloaded with the new
data and is ready to be read by software.
0 – Microwire read buffer is not full.
1 – Microwire read buffer is full.
The Receive Overrun Error bit, when set in
master mode, indicates that a receive overrun
error has occurred. This error occurs when
the read buffer is full, the 8-bit shifter is full,
and a new data transfer sequence starts. This
bit is undefined in slave mode. The OVR bit,
once set, remains set until cleared by software. Software clears this bit by writing a 1 to
its bit position. Writing a 0 to this bit position
has no effect. No other bits in the MWSTAT
register are affected by a write operation to
the register.
0 – No receive overrun error has occurred.
1 – Receive overrun error has occurred.
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SCM
19.5.3
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EIW
The Enable Interrupt for Read bit controls
whether an interrupt is generated when the
read buffer becomes full. When set, an interrupt is generated when the Read Buffer Full
bit (MWSTAT.RBF) is set. Otherwise, no interrupt is generated when the read buffer is full.
0 – No read buffer full interrupt.
1 – Interrupt when read buffer becomes full.
The Enable Interrupt for Write bit controls
whether an interrupt is generated when the
Busy bit (MWSTAT.BSY) is cleared, which indicates that a data transfer sequence has
been completed and the read buffer is ready
to receive the new data. Otherwise, no interrupt is generated when the Busy bit is cleared.
0 – No interrupt on data transfer complete.
1 – Interrupt on data transfer complete.
The Shift Clock Mode bit selects between the
normal clocking mode and the alternate clocking mode. In the normal mode, the output data
is clocked out on the falling edge of MSK and
the input data is sampled on the rising edge of
MSK. In the alternate mode, the output data is
clocked out on the rising edge of MSK and the
input data is sampled on the falling edge of
MSK.
0 – Normal clocking mode.
1 – Alternate clocking mode.
The Shift Clock Idle bit controls the value of
the MSK output when the Microwire module is
idle. This bit must be changed only when the
Microwire module is disabled (MWEN = 0) or
when no bus transaction is in progress (MWSTAT.BSY = 0).
0 – MSK is low when idle.
1 – MSK is high when idle
The Shift Clock Divider Value field specifies
the divisor used for generating the MSK shift
clock from the System Clock. The divisor is 2
× (MCDV[6:0] + 1). Valid values are 0000001b
to 1111111b, so the division ratio may range
from 3 to 256. This field is ignored in slave
mode (MWCTL1.MMNS=0).
RBF
bs
CP3UB17
EIR
OVR
122
The ACCESS.bus interface module (ACB) is a two-wire se- mand/control information and data using the synchronous
rial interface compatible with the ACCESS.bus physical lay- serial clock.
er. It permits easy interfacing to a wide range of low-cost
memories and I/O devices, including: EEPROMs, SRAMs,
timers, A/D converters, D/A converters, clock chips, and peSDA
ripheral drivers. It is compatible with Intel’s SMBus and Philips’ I2C bus. The module can be configured as a bus master
or slave, and can maintain bidirectional communications
SCL
with both multiple master and slave devices.
This section presents an overview of the bus protocol, and
its implementation by the module.
Data Line
Stable:
Data Valid
ACCESS.bus master and slave
Supports polling and interrupt-controlled operation
Generate a wake-up signal on detection of a Start Condition, while in power-down mode
Optional internal pull-up on SDA and SCL pins
ACB PROTOCOL OVERVIEW
The ACCESS.bus protocol uses a two-wire interface for bidirectional communication between the devices connected
to the bus. The two interface signals are the Serial Data Line
(SDA) and the Serial Clock Line (SCL). These signals
should be connected to the positive supply, through pull-up
resistors, to keep the signals high when the bus is idle.
DS075
Figure 42. Bit Transfer
Each data transaction is composed of a Start Condition, a
number of byte transfers (programmed by software), and a
Stop Condition to terminate the transaction. Each byte is
transferred with the most significant bit first, and after each
byte, an Acknowledge signal must follow.
te
20.1
Change
of Data
Allowed
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At each clock cycle, the slave can stall the master while it
handles the previous data, or prepares new data. This can
be performed for each bit transferred or on a byte boundary
by the slave holding SCL low to extend the clock-low period.
Typically, slaves extend the first clock cycle of a transfer if a
The ACCESS.bus protocol supports multiple master and byte read has not yet been stored, or if the next byte to be
slave transmitters and receivers. Each bus device has a transmitted is not yet ready. Some microcontrollers with limunique address and can operate as a transmitter or a re- ited hardware support for ACCESS.bus extend the access
after each bit, to allow software time to handle this bit.
ceiver (though some peripherals are only receivers).
20.1.1
bs
During data transactions, the master device initiates the
transaction, generates the clock signal, and terminates the
transaction. For example, when the ACB initiates a data
transaction with an ACCESS.bus peripheral, the ACB becomes the master. When the peripheral responds and
transmits data to the ACB, their master/slave (data transaction initiator and clock generator) relationship is unchanged,
even though their transmitter/receiver functions are reversed.
Start and Stop
The ACCESS.bus master generates Start and Stop Conditions (control codes). After a Start Condition is generated,
the bus is considered busy and it retains this status until a
certain time after a Stop Condition is generated. A high-tolow transition of the data line (SDA) while the clock (SCL) is
high indicates a Start Condition. A low-to-high transition of
the SDA line while the SCL is high indicates a Stop Condition (Figure 43).
Data Transactions
O
One data bit is transferred during each clock period. Data is
sampled during the high phase of the serial clock (SCL).
Consequently, throughout the clock high phase, the data
must remain stable (see Figure 42). Any change on the SDA
signal during the high phase of the SCL clock and in the
middle of a transaction aborts the current transaction. New
data must be driven during the low phase of the SCL clock.
This protocol permits a single data line to transfer both com-
SDA
SCL
P
S
Start
Condition
Stop
Condition
DS076
Figure 43. Start and Stop Conditions
In addition to the first Start Condition, a repeated Start Condition can be generated in the middle of a transaction. This
allows another device to be accessed, or a change in the direction of the data transfer.
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CP3UB17
20.0 ACCESS.bus Interface
CP3UB17
Acknowledge Cycle
Addressing Transfer Formats
The Acknowledge Cycle consists of two signals: the acknowledge clock pulse the master sends with each byte
transferred, and the acknowledge signal sent by the receiving device (Figure 44).
Each device on the bus has a unique address. Before any
data is transmitted, the master transmits the address of the
slave being addressed. The slave device should send an
acknowledge signal on the SDA signal, once it recognizes
its address.
Acknowledgment
Signal from Receiver
The address is the first seven bits after a Start Condition.
The direction of the data transfer (R/W) depends on the bit
sent after the address (the eighth bit). A low-to-high transition during a SCL high period indicates the Stop Condition,
and ends the transaction (Figure 46).
SDA
MSB
SCL
1
2
3-6
7
8
S
Start
Condition
9
ACK
1
2
3-8
9
ACK
P
Stop
Condition
Clock Line Held
Low by Receiver
While Interrupt
is Serviced
Byte Complete
Interrupt Within
Receiver
SDA
DS077
SCL
1-7
8
9
1-7
8
9
1-7
8
9
S
ACCESS.bus Data Transaction
P
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Figure 44.
Address
R/W ACK
Data
ACK
Data
ACK
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Start
Stop
The master generates the acknowledge clock pulse on the
Condition
Condition
ninth clock pulse of the byte transfer. The transmitter releasDS079
es the SDA line (permits it to go high) to allow the receiver
to send the acknowledge signal. The receiver must pull
down the SDA line during the acknowledge clock pulse,
which signals the correct reception of the last data byte, and Figure 46. A Complete ACCESS.bus Data Transaction
its readiness to receive the next byte. Figure 45 illustrates
When the address is sent, each device in the system comthe acknowledge cycle.
pares this address with its own. If there is a match, the device considers itself addressed and sends an acknowledge
Data Output
signal. Depending upon the state of the R/W bit (1 = read,
by Transmitter
Transmitter Stays Off
0 = write), the device acts as a transmitter or a receiver.
the Bus During the
Acknowledgment Clock
Data Output
by Receiver
bs
Acknowledgment
Signal from Receiver
SCL
1
2
3-6
S
Start
Condition
7
8
9
DS078
Figure 45. ACCESS.bus Acknowledge Cycle
O
The master generates an acknowledge clock pulse after
each byte transfer. The receiver sends an acknowledge signal after every byte received. There are two exceptions to
the “acknowledge after every byte” rule.
When the master is the receiver, it must indicate to the
transmitter an end-of-data condition by not-acknowledging (“negative acknowledge”) the last byte clocked out of
the slave. This “negative acknowledge” still includes the
acknowledge clock pulse (generated by the master), but
the SDA line is not pulled down.
When the receiver is full, otherwise occupied, or a problem has occurred, it sends a negative acknowledge to indicate that it cannot accept additional data bytes.
The ACCESS.bus protocol allows sending a general call address to all slaves connected to the bus. The first byte sent
specifies the general call address (00h) and the second byte
specifies the meaning of the general call (for example,
“Write slave address by software only”). Those slaves that
require the data acknowledge the call and become slave receivers; the other slaves ignore the call.
Arbitration on the Bus
Arbitration is required when multiple master devices attempt
to gain control of the bus simultaneously. Control of the bus
is initially determined according to address bits and clock
cycle. If the masters are trying to address the same bus device, data comparisons determine the outcome of this arbitration. In master mode, the device immediately aborts a
transaction if the value sampled on the SDA lines differs
from the value driven by the device. (Exceptions to this rule
are SDA while receiving data; in these cases the lines may
be driven low by the slave without causing an abort.)
The SCL signal is monitored for clock synchronization and
allows the slave to stall the bus. The actual clock period will
be the one set by the master with the longest clock period
or by the slave stall period. The clock high period is determined by the master with the shortest clock high period.
When an abort occurs during the address transmission, the
master that identifies the conflict should give up the bus,
switch to slave mode, and continue to sample SDA to see if
it is being addressed by the winning master on the ACCESS.bus.
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124
ACB FUNCTIONAL DESCRIPTION
4. If the requested direction is transmit, and the start
transaction was completed successfully (i.e., neither
the ACBST.NEGACK nor ACBST.BER bit is set, and no
other master has accessed the device), the ACBST.SDAST bit is set to indicate that the module is waiting for service.
5. If the requested direction is receive, the start transaction was completed successfully, and the
ACBCTL1.STASTRE bit is clear, the module starts receiving the first byte automatically.
6. Check that both the ACBST.BER and ACBST.NEGACK
bits are clear. If the ACBCTL1.INTEN bit is set, an interrupt is generated when either the ACBST.BER or
ACBST.NEGACK bit is set.
The ACB module provides the physical layer for an ACCESS.bus compliant serial interface. The module is configurable as either a master or slave device. As a slave, the
ACB module may issue a request to become the bus master.
20.2.1
Master Mode
An ACCESS.bus transaction starts with a master device requesting bus mastership. It sends a Start Condition, followed by the address of the device it wants to access. If this
transaction is successfully completed, software can assume
that the device has become the bus master.
For a device to become the bus master, software should
perform the following steps:
Sending the Address Byte
te
After becoming the bus master, the device can start transmitting data on the ACCESS.bus. To transmit a byte, software must:
1. Check that the BER and NEGACK bits in the ACBST
register are clear and the ACBST.SDAST bit is set. Also, if the ACBCTL1.STASTRE bit is set, check that the
ACBST.STASTR bit is clear.
2. Write the data byte to be transmitted to the ACBSDA
register.
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1. Set the ACBCTL1.START bit, and configure the
ACBCTL1.INTEN bit to the desired operation mode
(Polling or Interrupt). This causes the ACB to issue a
Start Condition on the ACCESS.bus, as soon as the
ACCESS.bus is free (ACBCST.BB=0). It then stalls the
bus by holding SCL low.
2. If a bus conflict is detected, (i.e., some other device
pulls down the SCL signal before this device does), the
ACBST.BER bit is set.
3. If there is no bus conflict, the ACBST.MASTER and
ACBST.SDAST bits are set.
4. If the ACBCTL1.INTEN bit is set, and either the ACBST.BER bit or the ACBST.SDAST bit is set, an interrupt
is sent to the ICU.
Master Transmit
When the slave responds with a negative acknowledge, the
ACBST.NEGACK bit is set and the ACBST.SDAST bit remains cleared. In this case, if the ACBCTL1.INTEN bit is
set, an interrupt is sent to the core.
Master Receive
O
bs
After becoming the bus master, the device can start receivOnce this device is the active master of the ACCESS.bus
ing data on the ACCESS.bus. To receive a byte, software
(ACBST.MASTER = 1), it can send the address on the bus.
must:
The address should not be this device’s own address as
specified in the ACBADDR.ADDR field if the ACBAD- 1. Check that the ACBST.SDAST bit is set and the ACBST.BER bit is clear. Also, if the ACBCTL1.STASTRE bit
DR.SAEN bit is set or the ACBADDR2.ADDR field if the
is set, check that the ACBST.STASTR bit is clear.
ACBADDR2.SAEN bit is set, nor should it be the global call
2. Set the ACBCTL1.ACK bit, if the next byte is the last
address if the ACBST.GCMTCH bit is set.
byte that should be read. This causes a negative acTo send the address byte use the following sequence:
knowledge to be sent.
1. Configure the ACBCTL1.INTEN bit according to the de- 3. Read the data byte from the ACBSDA register.
sired operation mode. For a receive transaction where
software wants only one byte of data, it should set the Master Stop
ACBCTL1.ACK bit. If only an address needs to be sent, A Stop Condition may be issued only when this device is the
set the ACBCTL1.STASTRE bit.
active bus master (ACBST.MASTRER = 1). To end a trans2. Write the address byte (7-bit target device address), action, set the ACBCTL1.STOP bit before clearing the curand the direction bit, to the ACBSDA register. This rent stall bit (i.e., the ACBST.SDAST, ACBST.NEGACK, or
causes the module to generate a transaction. At the ACBST.STASTR bit). This causes the module to send a
end of this transaction, the acknowledge bit received is Stop Condition immediately, and clear the ACBCTL1.STOP
copied to the ACBST.NEGACK bit. During the transac- bit.
tion, the SDA and SCL signals are continuously
checked for conflict with other devices. If a conflict is Master Bus Stall
detected, the transaction is aborted, the ACBST.BER The ACB module can stall the ACCESS.bus between transbit is set, and the ACBST.MASTER bit is cleared.
fers while waiting for the core’s response. The ACCESS.bus
3. If the ACBCTL1.STASTRE bit is set, and the transac- is stalled by holding the SCL signal low after the acknowltion was successfully completed (i.e., both the ACB- edge cycle. Note that this is interpreted as the beginning of
ST.BER and ACBST.NEGACK bits are cleared), the the following bus operation. Software must make sure that
ACBST.STASTR bit is set. In this case, the ACB stalls the next operation is prepared before the bit that causes the
any further ACCESS.bus operations (i.e., holds SCL bus stall is cleared.
low). If the ACBCTL1.INTE bit is set, it also sends an
interrupt to the ICU.
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CP3UB17
20.2
20.2.2
Slave Mode
Negative acknowledge after sending a byte
A slave device waits in Idle mode for a master to initiate a
(ACBSTNEGACK = 1).
bus transaction. Whenever the ACB is enabled, and it is not
ACBST.SDAST bit is set.
acting as a master (i.e., ACBST.MASTER = 0), it acts as a
If the ACBCTL1.STASTRE bit is set, after a successful slave device.
start (ACBST.STASTR = 1).
Once a Start Condition on the bus is detected, this device
checks whether the address sent by the current master
Repeated Start
matches either:
A repeated start is performed when this device is already
the bus master (ACBST.MASTER = 1). In this case, the AC- The ACBADDR.ADDR value if the ACBADDR.SAEN bit
is set.
CESS.bus is stalled and the ACB waits for the core handling
due to: negative acknowledge (ACBST.NEGACK = 1), emp- The ACBADDR2.ADDR value if the ACBADDR2.SAEN
bit is set.
ty buffer (ACBST.SDAST = 1), or a stop-after-start (ACB The general call address if the ACBCTL1.GCM bit is set.
ST.STASTR = 1).
This match is checked even when the ACBST.MASTER bit
For a repeated start:
is set. If a bus conflict (on SDA or SCL) is detected, the
1. Set the ACBCTL1.START bit.
ACBST.BER bit is set, the ACBST.MASTER bit is cleared,
2. In master receive mode, read the last data item from
and this device continues to search the received message
the ACBSDA register.
for a match. If an address match, or a global match, is de3. Follow the address send sequence, as described in
tected:
“Sending the Address Byte” on page 125.
4. If the ACB was waiting for handling due to ACB- 1. This device asserts its data pin during the acknowledge
cycle.
ST.STASTR = 1, clear it only after writing the requested
2.
The ACBCST.MATCH, ACBCST.MATCHAF (or
address and direction to the ACBSDA register.
ACBCST.GCMTCH if it is a global call address match,
Master Error Detections
or ACBCST.ARPMATCH if it is an ARP address) and
ACBST.NMATCH in the ACBCST register are set. If the
The ACB detects illegal Start or Stop Conditions (i.e., a
ACBST.XMIT bit is set (i.e., slave transmit mode), the
Start or Stop Condition within the data transfer, or the acACBST.SDAST bit is set to indicate that the buffer is
knowledge cycle) and a conflict on the data lines of the ACempty.
CESS.bus. If an illegal action is detected, the BER bit is set,
and the MASTER mode is exited (the MASTER bit is 3. If the ACBCTL1.INTEN bit is set, an interrupt is generated if both the INTEN and NMINTE bits in the
cleared).
ACBCTL1 register are set.
Bus Idle Error Recovery
4. Software then reads the ACBST.XMIT bit to identify the
When a request to become the active bus master or a redirection requested by the master device. It clears the
start operation fails, the ACBST.BER bit is set to indicate the
ACBST.NMATCH bit so future byte transfers are identierror. In some cases, both this device and the other device
fied as data bytes.
may identify the failure and leave the bus idle. In this case,
Slave Receive and Transmit
the start sequence may not be completed and the ACSlave Receive and Transmit are performed after a match is
CESS.bus may remain deadlocked.
detected and the data transfer direction is identified. After a
To recover from deadlock, use the following sequence:
byte transfer, the ACB extends the acknowledge clock until
1. Clear the ACBST.BER and ACBCST.BB bits.
software reads or writes the ACBSDA register. The receive
2. Wait for a time-out period to check that there is no other and transmit sequence are identical to those used in the
active master on the bus (i.e., the ACBCST.BB bit re- master routine.
mains clear).
3. Disable, and re-enable the ACB to put it in the non-ad- Slave Bus Stall
dressed slave mode.
When operating as a slave, this device stalls the AC4. At this point, some of the slaves may not identify the CESS.bus by extending the first clock cycle of a transaction
bus error. To recover, the ACB becomes the bus master in the following cases:
by issuing a Start Condition and sends an address
— The ACBST.SDAST bit is set.
field; then issue a Stop Condition to synchronize all the
— The ACBST.NMATCH, and ACBCTL1.NMINTE bits
slaves.
are set.
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CP3UB17
The bits that can cause a stall in master mode are:
Slave Error Detections
The ACB detects illegal Start and Stop Conditions on the
ACCESS.bus (i.e., a Start or Stop Condition within the data
transfer or the acknowledge cycle). When an illegal Start or
Stop Condition is detected, the BER bit is set and the
MATCH and GMATCH bits are cleared, causing the module
to be an unaddressed slave.
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126
ACCESS.BUS INTERFACE REGISTERS
When this device is in Power Save, Idle, or Halt mode, the The ACCESS.bus interface uses the registers listed in
ACB module is not active but retains its status. If the ACB is Table 46.
enabled (ACBCTL2.ENABLE = 1) on detection of a Start
Table 46 ACCESS.bus Interface Registers
Condition, a wake-up signal is issued to the MIWU module
(see Section 13.0). Use this signal to switch this device to
Name
Address
Description
Active mode.
The ACB module cannot check the address byte for a match
following the start condition that caused the wake-up event
for this device. The ACB responds with a negative acknowledge, and the device should resend both the Start Condition
and the address after this device has had time to wake up.
Check that the ACBCST.BUSY bit is inactive before entering
Power Save, Idle, or Halt mode. This guarantees that the device does not acknowledge an address sent and stop responding later.
SDA and SCL Pins Configuration
The SDA and SCL pins are driven as open-drain signals.
For more information, see the I/O configuration section.
ACB Serial Data
Register
ACBST
FF FEC2h
ACB Status Register
ACBCST
FF FEC4h
ACB Control Status
Register
ACBCTL1
FF FEC6h
ACB Control
Register 1
ACBCTL2
FF FECAh
ACB Control
Register 2
ACBCTL3
ACB Control
Register 3
FF FECEh
ACB Clock Frequency Configuration
ACB Own Address
The ACB module permits software to set the clock frequenACBADDR1
FF FEC8h
Register 1
cy used for the ACCESS.bus clock. The clock is set by the
ACBCTL2.SCLFRQ field. This field determines the SCL
ACB Own Address
ACBADDR2
FF FECCh
clock period used by this device. This clock low period may
Register 2
be extended by stall periods initiated by the ACB module or
by another ACCESS.bus device. In case of a conflict with
20.3.1 ACB Serial Data Register (ACBSDA)
another bus master, a shorter clock high period may be
forced by the other bus master until the conflict is resolved. The ACBSDA register is a byte-wide, read/write shift register used to transmit and receive data. The most significant
bit is transmitted (received) first and the least significant bit
is transmitted (received) last. Reading or writing to the ACBSDA register is allowed when ACBST.SDAST is set; or for
repeated starts after setting the START bit. An attempt to
access the register in other cases produces unpredictable
results.
O
bs
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20.2.4
FF FEC0h
te
20.2.3
ACBSDA
7
0
DATA
20.3.2
ACB Status Register (ACBST)
The ACBST register is a byte-wide, read-only register that
maintains current ACB status. At reset, and when the module is disabled, ACBST is cleared.
7
6
5
4
3
2
1
0
SLVSTP SDAST BER NEGACK STASTR NMATCH MASTER XMIT
XMIT
127
The Direction Bit bit is set when the ACB module is currently in master/slave transmit mode.
Otherwise it is cleared.
0 – Receive mode.
1 – Transmit mode.
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CP3UB17
20.3
Power Down
STASTR
20.3.3
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The SDA Status bit indicates that the SDA
data register is waiting for data (transmit, as
master or slave) or holds data that should be
read (receive, as master or slave). This bit is
cleared when reading from the ACBSDA register during a receive, or when written to during a transmit. When the ACBCTL1.START bit
is set, reading the ACBSDA register does not
clear the SDAST bit. This enables the ACB to
send a repeated start in master receive mode.
0 – ACB module is not waiting for data transfer.
1 – ACB module is waiting for data to be loaded or unloaded.
The Slave Stop bit indicates that a Stop Condition was detected after a slave transfer (i.e.,
after a slave transfer in which MATCH or
GCMATCH is set). Writing 1 to SLVSTP clears
it. It is also cleared when the module is disabled. Writing 0 to SLVSTP is ignored.
0 – No stop condition after slave transfer occurred.
1 – Stop condition after slave transfer occurred.
ACB Control Status Register (ACBCST)
The ACBCST register is a byte-wide, read/write register that
maintains current ACB status. At reset and when the module is disabled, the non-reserved bits of ACBCST are
cleared.
7
6
5
4
3
2
1
0
Reserved TGSCL TSDA GCMTCH MATCH BB BUSY
BUSY
O
BER
SLVSTP
bs
NEGACK
SDAST
te
NMATCH
The Master bit indicates that the module is
currently in master mode. It is set when a request for bus mastership succeeds. It is
cleared upon arbitration loss (BER is set) or
the recognition of a Stop Condition.
0 – Slave mode.
1 – Master mode.
The New match bit is set when the address
byte following a Start Condition, or repeated
starts, causes a match or a global-call match.
The NMATCH bit is cleared when written with
1. Writing 0 to NMATCH is ignored. If the
ACBCTL1.INTEN bit is set, an interrupt is sent
when this bit is set.
0 – No match.
1 – Match or global-call match.
The Stall After Start bit is set by the successful
completion of an address sending (i.e., a Start
Condition sent without a bus error, or negative
acknowledge), if the ACBCTL1.STASTRE bit
is set. This bit is ignored in slave mode. When
the STASTR bit is set, it stalls the bus by pulling down the SCL line, and suspends any other action on the bus (e.g., receives first byte in
master receive mode). In addition, if the
ACBCTL1.INTEN bit is set, it also sends an
interrupt to the ICU. Writing 1 to the STASTR
bit clears it. It is also cleared when the module
is disabled. Writing 0 to the STASTR bit has
no effect.
0 – No stall after start condition.
1 – Stall after successful start.
The Negative Acknowledge bit is set by hardware when a transmission is not acknowledged on the ninth clock. (In this case, the
SDAST bit is not set.) Writing 1 to NEGACK
clears it. It is also cleared when the module is
disabled. Writing 0 to the NEGACK bit is ignored.
0 – No transmission not acknowledged condition.
1 – Transmission not acknowledged.
The Bus Error bit is set by the hardware when
a Start or Stop Condition is detected during
data transfer (i.e., Start or Stop Condition during the transfer of bits 2 through 8 and acknowledge cycle), or when an arbitration
problem is detected. Writing 1 to the BER bit
clears it. It is also cleared when the module is
disabled. Writing 0 to the BER bit is ignored.
0 – No bus error occurred.
1 – Bus error occurred.
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CP3UB17
MASTER
128
The BUSY bit indicates that the ACB module
is:
Generating a Start Condition
In Master mode (ACBST.MASTER is set)
In Slave mode (ACBCST.MATCH or
ACBCST.GCMTCH is set)
In the period between detecting a Start
and completing the reception of the address byte. After this, the ACB either becomes not busy or enters slave mode.
The BUSY bit is cleared by the completion of
any of the above states, and by disabling the
module. BUSY is a read only bit. It must always be written with 0.
0 – ACB module is not busy.
1 – ACB module is busy.
TSDA
7
6
5
4
3
2
1
0
STASTRE NMINTE GCMEN ACK Res. INTEN STOP START
The Start bit is set to generate a Start Condition on the ACCESS.bus. The START bit is
cleared when the Start Condition is sent, or
upon
detection
of
a
Bus
Error
(ACBST.BER = 1). This bit should be set only
when in Master mode, or when requesting
Master mode. If this device is not the active
master of the bus (ACBST.MASTER = 0), setting the START bit generates a Start Condition
as soon as the ACCESS.bus is free
(ACBCST.BB = 0). An address send sequence should then be performed. If this device is the active master of the bus
(ACBST.MASTER = 1), when the START bit is
set, a write to the ACBSDA register generates
a Start Condition, then the ACBSDA data is
transmitted as the slave’s address and the requested transfer direction. This case is a repeated Start Condition. It may be used to
switch the direction of the data flow between
the master and the slave, or to choose another slave device without using a Stop Condition
in between.
0 – Writing 0 has no effect.
1 – Writing 1 generates a Start condition.
The Stop bit in master mode generates a Stop
Condition that completes or aborts the current
message transfer. This bit clears itself after
the Stop condition is issued.
0 – Writing 0 has no effect.
1 – Writing 1 generates a Stop condition.
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START
STOP
O
TGSCL
ACB Control Register 1 (ACBCTL1)
The ACBCTL1 register is a byte-wide, read/write register
that configures and controls the ACB module. At reset and
while the module is disabled (ACBCTL2.ENABLE = 0), the
ACBCTL1 register is cleared.
bs
GCMTCH
20.3.4
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MATCH
The Bus Busy bit indicates the bus is busy. It
is set when the bus is active (i.e., a low level
on either SDA or SCL) or by a Start Condition.
It is cleared when the module is disabled, on
detection of a Stop Condition, or when writing
1 to this bit. See “Usage Hints” on page 131
for a description of the use of this bit. This bit
should be set when either the SDA or SCL signals are low. This is done by sampling the
SDA and SCL signals continuously and setting the bit if one of them is low. The bit remains set until cleared by a STOP condition or
written with 1.
0 – Bus is not busy.
1 – Bus is busy.
The Address Match bit indicates in slave
mode when ACBADDR.SAEN is set and the
first seven bits of the address byte (the first
byte transferred after a Start Condition)
matches the 7-bit address in the ACBADDR
register, or when ACBADDR2.SAEN is set
and the first seven bits of the address byte
matches the 7-bit address in the ACBADDR2
register. It is cleared by Start Condition or repeated Start and Stop Condition (including illegal Start or Stop Condition).
0 – No address match occurred.
1 – Address match occurred.
The Global Call Match bit is set in slave mode
when the ACBCTL1.GCMEN bit is set and the
address byte (the first byte transferred after a
Start Condition) is 00h. It is cleared by a Start
Condition or repeated Start and Stop Condition (including illegal Start or Stop Condition).
0 – No global call match occurred.
1 – Global call match occurred.
The Test SDA bit samples the state of the SDA
signal. This bit can be used while recovering
from an error condition in which the SDA signal is constantly pulled low by a slave that
went out of sync. This bit is a read-only bit.
Data written to it is ignored.
The Toggle SCL bit enables toggling the SCL
signal during error recovery. When the SDA
signal is low, writing 1 to this bit drives the SCL
signal high for one cycle. Writing 1 to TGSCL
when the SDA signal is high is ignored. The bit
is cleared when the clock toggle is completed.
0 – Writing 0 has no effect.
1 – Writing 1 toggles the SDA signal high for
one cycle.
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CP3UB17
BB
20.3.5
ACB Control Register 2 (ACBCTL2)
The ACBCTL2 register is a byte-wide, read/write register
that controls the module and selects the ACB clock rate. At
reset, the ACBCTL2 register is cleared.
7
1
ENABLE
bs
GCMEN
O
NMINTE
STASTRE
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0
SCLFRQ6:0
ENABLE
The Enable bit controls the ACB module.
When this bit is set, the ACB module is enabled. When the Enable bit is clear, the ACB
module is disabled, the ACBCTL1, ACBST,
and ACBCST registers are cleared, and the
clocks are halted.
0 – ACB module disabled.
1 – ACB module enabled.
The SCL Frequency field specifies the SCL
period (low time and high time) in master
mode. The clock low time and high time are
defined as follows:
tSCLl = tSCLh = 2 × SCLFRQ × tCLK
Where tCLK is this device’s clock period when
in Active mode. The SCLFRQ field may be
programmed to values in the range of
0001000b through 1111111b. Using any other
value has unpredictable results.
SCLFRQ
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ACK
The Interrupt Enable bit controls generating
ACB interrupts. When the INTEN bit is cleared
ACB interrupt is disabled. When the INTEN bit
is set, interrupts are enabled.
0 – ACB interrupts disabled.
1 – ACB interrupts enabled.
An interrupt is generated (the interrupt signal
to the ICU is high) on any of the following
events:
An address MATCH is detected (ACBST.NMATCH = 1) and the NMINTE bit is
set.
A Bus Error occurs (ACBST.BERR = 1).
Negative acknowledge after sending a
byte (ACBST.NEGACK = 1).
An interrupt is generated on acknowledge
of each transaction (same as hardware
setting the ACBST.SDAST bit).
If ACBCTL1.STASTRE = 1, in master
mode
after
a
successful
start
(ACBST.STASTR = 1).
Detection of a Stop Condition while in
slave receive mode (ACBST.SLVSTP = 1).
The Acknowledge bit holds the value this device sends in master or slave mode during the
next acknowledge cycle. Setting this bit to 1
instructs the transmitting device to stop sending data, since the receiver either does not
need, or cannot receive, any more data. This
bit is cleared after the first acknowledge cycle.
This bit is ignored when in transmit mode.
The Global Call Match Enable bit enables the
match of an incoming address byte to the general call address (Start Condition followed by
address byte of 00h) while the ACB is in slave
mode. When cleared, the ACB does not respond to a global call.
0 – Global call matching disabled.
1 – Global call matching enabled.
The New Match Interrupt Enable controls
whether ACB interrupts are generated on new
matches. Set the NMINTE bit to enable the interrupt on a new match (i.e., when ACBST.NMATCH is set). The interrupt is issued
only if the ACBCTL1.INTEN bit is set.
0 – New match interrupts disabled.
1 – New match interrupts enabled.
The Stall After Start Enable bit enables the
stall after start mechanism. When enabled,
the ACB is stalled after the address byte.
When the STASTRE bit is clear, the ACBST.STASTR bit is always clear.
0 – No stall after start.
1 – Stall-after-start enabled.
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CP3UB17
INTEN
20.3.6
ACB Control Register 3 (ACBCTL3)
The ACBCTL3 register is a byte-wide, read/write register
that expands the clock prescaler field and enables ARP
matches. At reset, the ACBCTL3 register is cleared.
7
Reserved
ARPMEN
SCLFRQ
130
3
2
ARPMEN
1
0
SCLFRQ8:7
The ARP Match Enable bit enables the
matching of an incoming address byte to the
SMBus ARP address 110 0001b general call
address (Start condition followed by address
byte of 00h), while the ACB is in slave mode.
0 – ACB does not respond to ARP addresses.
1 – ARP address matching enabled.
The SCL Frequency field specifies the SCL
period (low time and high time) in master
mode. The ACBCTL3 register provides a 2-bit
expansion of this field, with the remaining 7
bits being held in the ACBCTL2 register.
20.4
ACB Own Address Register 1 (ACBADDR1)
The ACBADDR1 register is a byte-wide, read/write register
that holds the module’s first ACCESS.bus address. After reset, its value is undefined.
6
ADDR
ADDR
The Own Address field holds the first 7-bit ACCESS.bus address of this device. When in
slave mode, the first 7 bits received after a
Start Condition are compared to this field (first
bit received to bit 6, and the last to bit 0). If the
address field matches the received data and
the SAEN bit is set, a match is detected.
The Slave Address Enable bit controls whether address matching is performed in slave
mode. When set, the SAEN bit indicates that
the ADDR field holds a valid address and enables the match of ADDR to an incoming address byte. When cleared, the ACB does not
check for an address match.
0 – Address matching disabled.
1 – Address matching enabled.
SAEN
20.3.8
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SAEN
0
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7
ACB Own Address Register 2 (ACBADDR2)
The ACBADDR2 register is a byte-wide, read/write register
that holds the module’s second ACCESS.bus address. After
reset, its value is undefined.
SAEN
0
ADDR
The Own Address field holds the second 7-bit
ACCESS.bus address of this device. When in
slave mode, the first 7 bits received after a
Start Condition are compared to this field (first
bit received to bit 6, and the last to bit 0). If the
address field matches the received data and
the SAEN bit is set, a match is detected.
The Slave Address Enable bit controls whether address matching is performed in slave
mode. When set, the SAEN bit indicates that
the ADDR field holds a valid address and enables the match of ADDR to an incoming address byte. When cleared, the ACB does not
check for an address match.
0 – Address matching disabled.
1 – Address matching enabled.
O
ADDR
6
bs
7
SAEN
USAGE HINTS
When the ACB module is disabled, the ACBCST.BB bit is
cleared.
After
enabling
the
ACB
(ACBCTL2.ENABLE = 1) in systems with more than one
master, the bus may be in the middle of a transaction with
another device, which is not reflected in the BB bit. There
is a need to allow the ACB to synchronize to the bus activity status before issuing a request to become the bus
master, to prevent bus errors. Therefore, before issuing
a request to become the bus master for the first time,
software should check that there is no activity on the bus
by checking the BB bit after the bus allowed time-out period.
When waking up from power down, before checking the
ACBCST.MATCH bit, test the ACBCST.BUSY bit to make
sure that the address transaction has finished.
The BB bit is intended to solve a deadlock in which two,
or more, devices detect a usage conflict on the bus and
both devices cease being bus masters at the same time.
In this situation, the BB bits of both devices are active
(because each deduces that there is another master currently performing a transaction, while in fact no device is
executing a transaction), and the bus would stay locked
until some device sends a ACBCTL1.STOP condition.
The ACBCST.BB bit allows software to monitor bus usage, so it can avoid sending a STOP signal in the middle
of the transaction of some other device on the bus. This
bit detects whether the bus remains unused over a certain period, while the BB bit is set.
In some cases, the bus may get stuck with the SCL or
SDA lines active. A possible cause is an erroneous Start
or Stop Condition that occurs in the middle of a slave receive session. When the SCL signal is stuck active, there
is nothing that can be done, and it is the responsibility of
the module that holds the bus to release it. When the
SDA signal is stuck active, the ACB module enables the
release of the bus by using the following sequence. Note
that in normal cases, the SCL signal may be toggled only
by the bus master. This protocol is a recovery scheme
which is an exception that should be used only in the
case when there is no other master on the bus. The recovery scheme is as follows:
1. Disable and re-enable the module to set it into the not
addressed slave mode.
2. Set the ACBCTL1.START bit to make an attempt to
issue a Start Condition.
3. Check if the SDA signal is active (low) by reading
ACBCST.TSDA bit. If it is active, issue a single SCL
cycle by writing 1 to ACBCST.TGSCL bit. If the SDA
line is not active, continue from step 5.
4. Check if the ACBST.MASTER bit is set, which indicates that the Start Condition was sent. If not, repeat
step 3 and 4 until the SDA signal is released.
5. Clear the BB bit. This enables the START bit to be executed. Continue according to “Bus Idle Error Recovery” on page 126.
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CP3UB17
20.3.7
CP3UB17
21.0 Timing and Watchdog Module
The Timing and Watchdog Module (TWM) generates the Slow Clock period. The prescaled clock signal is called
clocks and interrupts used for timing periodic functions in T0IN.
the system; it also provides Watchdog protection over soft21.2
TIMER T0 OPERATION
ware execution.
The TWM is designed to provide flexibility in system design Timer T0 is a programmable 16-bit down counter that can
by configuring various clock ratios and by selecting the be used as the time base for real-time operations such as a
Watchdog clock source. After setting the TWM configura- periodic audible tick. It can also be used to drive the Watchtion, software can lock it for a higher level of protection dog circuit.
The timer starts counting from the value loaded into the
TWMT0 register and counts down on each rising edge of
T0IN. When the timer reaches zero, it is automatically reloaded from the TWMT0 register and continues counting
down from that value. Therefore, the frequency of the timer
is:
against erroneous software action. Once the TWM is
locked, only reset can release it.
21.1
TWM STRUCTURE
Figure 47 is a block diagram showing the internal structure
of the Timing and Watchdog module. There are two main
sections: the Real-Time Timer (T0) section at the top and
the Watchdog section on the bottom.
fSLCLK / [(TWMT0 + 1) × prescaler]
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When an external crystal oscillator is used as the SLCLK
All counting activities of the module are based on the Slow source or when the fast clock is divided accordingly, f
SLCLK
Clock (SLCLK). A prescaler counter divides this clock to is 32.768 kHz.
make a slower clock. The prescaler factor is defined by a 3bit field in the Timer and Watchdog Prescaler register, which The value stored in TWMT0 can range from 0001h to
selects either 1, 2, 4, 8, 16, or 32 as the divisor. Therefore, FFFFh.
the prescaled clock period can be 2, 4, 8, 16, or 32 times the
REAL TIME TIMER (T0)
Slow
Clock
5-Bit Prescaler Counter
(TWCP)
TWW/MT0 Register
T0IN
T0CSR Contrl. Reg.
T0LINT
(to ICU)
Restart
Underflow
WATCHDOG
Timer
Underflow
bs
16-Bit Timer
(Timer0)
T0OUT
(to Multi-InputWake-Up)
O
Restart
WDSDM
WATCHDOG
Service
Logic
WDCNT
Watchdog Error
WDERR
WATCHDOG
DS080
Figure 47. Timing and Watchdog Module Block Diagram
When the counter reaches zero, an internal timer signal
called T0OUT is set for one T0IN clock cycle. This signal
sets the TC bit in the TWMT0 Control and Status Register
(T0CSR). It also generates an interrupt (IRQ14), when enabled by the T0CSR.T0INTE bit. T0OUT is also an input to
the MIWU (see Section 13.0), so an edge-triggered interrupt is also available through this alternative mechanism.
If software loads the TWMT0 register with a new value, the
timer uses that value the next time that it reloads the 16-bit
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timer register (in other words, after reaching zero). Software
can restart the timer at any time (on the very next edge of
the T0IN clock) by setting the Restart (RST) bit in the
T0CSR register. The T0CSR.RST bit is cleared automatically upon restart of the 16-bit timer.
Note: If software wishes to switch to Power Save or Idle
mode after setting the T0CSR.RST bit, software must wait
for the reset operation to complete before performing the
switch.
132
WATCHDOG OPERATION
21.3.2
The Timer and Watchdog Module is active in both the Power
Save and Idle modes. The clocks and counters continue to
operate normally in these modes. The WDSDM register is
accessible in the Power Save and Idle modes, but the other
TWM registers are accessible only in the Active mode.
Therefore, Watchdog servicing must be carried out using
the WDSDM register in the Power Save or Idle mode.
The Watchdog is an 8-bit down counter that operates on the
rising edge of a specified clock source. At reset, the Watchdog is disabled; it does not count and no Watchdog signal is
generated. A write to either the Watchdog Count (WDCNT)
register or the Watchdog Service Data Match (WDSDM)
register starts the counter. The Watchdog counter counts
down from the value programmed in the WDCNT register.
Once started, only a reset can stop the Watchdog from operating.
In the Halt mode, the entire device is frozen, including the
Timer and Watchdog Module. On return to Active mode, operation of the module resumes at the point at which it was
stopped.
The Watchdog can be programmed to use either T0OUT or
T0IN as its clock source (the output and input of Timer T0,
respectively). The TWCFG.WDCT0I bit controls this clock
selection.
If the TWCFG.WDSDME bit is clear, the Watchdog is serviced by writing a value to the WDCNT register. The value
written to the register is reloaded into the Watchdog counter.
The counter then continues counting down from that value.
21.4
TWM REGISTERS
The TWM registers controls the operation of the Timing and
Watchdog Module. There are six such registers:
Table 47 TWM Registers
Name
Address
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If the TWCFG.WDSDME bit is set, the Watchdog is serviced by writing the value 5Ch to the Watchdog Service
Data Match (WDSDM) register. This reloads the Watchdog
counter with the value previously programmed into the WDCNT register. The counter then continues counting down
from that value.
Note: After a restart or Watchdog service through WDCNT,
do not enter Power Save mode for a period equivalent to 5
Slow Clock cycles.
te
Software must periodically “service” the Watchdog. There
are two ways to service the Watchdog, the choice depending on the programmed value of the WDSDME bit in the
Timer and Watchdog Configuration (TWCFG) register.
Power Save Mode Operation
A Watchdog error signal is generated by any of the following
events:
bs
The Watchdog serviced too late.
The Watchdog serviced too often.
The WDSDM register is written with a value other than
5Ch when WDSDM type servicing is enabled
(TWCFG.WDSDME = 1).
TWCFG
FF FF20h
Timer and Watchdog
Configuration Register
TWCP
FF FF22h
Timer and Watchdog
Clock Prescaler
Register
TWMT0
FF FF24h
TWM Timer 0 Register
T0CSR
FF FF26h
TWMT0 Control and
Status Register
WDCNT
FF FF28h
Watchdog Count
Register
WDSDM
FF FF2Ah
Watchdog Service
Data Match Register
A Watchdog error condition resets the device.
21.3.1
Register Locking
Description
O
The Timer and Watchdog Configuration (TWCFG) register
is used to set the Watchdog configuration. It controls the The WDSDM register is accessible in both Active and PowWatchdog clock source (T0IN or T0OUT), the type of er Save mode. The other TWM registers are accessible only
Watchdog servicing (using WDCNT or WDSDM), and the in Active mode.
locking state of the TWCFG, TWCPR, TIMER0, T0CSR,
and WDCNT registers. A register that is locked cannot be
read or written. A write operation is ignored and a read operation returns unpredictable results.
If the TWCFG register is itself locked, it remains locked until
the device is reset. Any other locked registers also remain
locked until the device is reset. This feature prevents a runaway program from tampering with the programmed Watchdog function.
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CP3UB17
21.3
CP3UB17
21.4.1
Timer and Watchdog Configuration Register
(TWCFG)
21.4.2
The TWCFG register is a byte-wide, read/write register that
selects the Watchdog clock input and service method, and
also allows the Watchdog registers to be selectively locked.
A locked register cannot be read or written; a read operation
returns unpredictable values and a write operation is ignored. Once a lock bit is set, that bit cannot be cleared until
the device is reset. At reset, the non-reserved bits of the
register are cleared. The register format is shown below.
Timer and Watchdog Clock Prescaler Register
(TWCP)
The TWCP register is a byte-wide, read/write register that
specifies the prescaler value used for dividing the low-frequency clock to generate the T0IN clock. At reset, the nonreserved bits of the register are cleared. The register format
is shown below.
7
3
2
Reserved
7 6
5
4
3
2
1
LTWMT0
O
WDCT0I
WDSDME
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Main Clock Divide. This 3-bit field defines the
prescaler factor used for dividing the low
speed device clock to create the T0IN clock.
The allowed 3-bit values and the corresponding clock divisors and clock rates are listed below.
te
bs
LWDCNT
The Lock TWCFG Register bit controls access to the TWCFG register. When clear, access to the TWCFG register is allowed. When
set, the TWCFG register is locked.
0 – TWCFG register unlocked.
1 – TWCFG register locked.
The Lock TWCP Register bit controls access
to the TWCP register. When clear, access to
the TWCP register is allowed. When set, the
TWCP register is locked.
0 – TWCP register unlocked.
1 – TWCP register locked.
The Lock TWMT0 Register bit controls access
to the TWMT0 register. When clear, access to
the TWMT0 and T0CSR registers are allowed. When set, the TWMT0 and T0CSR
registers are locked.
0 – TWMT0 register unlocked.
1 – TWMT0 register locked.
The Lock LDWCNT Register bit controls access to the LDWCNT register. When clear, access to the LDWCNT register is allowed.
When set, the LDWCNT register is locked.
0 – LDWCNT register unlocked.
1 – LDWCNT register locked.
The Watchdog Clock from T0IN bit selects the
clock source for the Watchdog timer. When
clear, the T0OUT signal (the output of Timer
T0) is used as the Watchdog clock. When set,
the T0IN signal (the prescaled Slow Clock) is
used as the Watchdog clock.
0 – Watchdog timer is clocked by T0OUT.
1 – Watchdog timer is clocked by T0IN.
The Watchdog Service Data Match Enable bit
controls which method is used to service the
Watchdog timer. When clear, Watchdog servicing is accomplished by writing a count value to the WDCNT register; write operations to
the Watchdog Service Data Match (WDSDM)
register are ignored. When set, Watchdog
servicing is accomplished by writing the value
5Ch to the WDSDM register.
0 – Write a count value to the WDCNT register to service the Watchdog timer.
1 – Write 5Ch to the WDSDM register to service the Watchdog timer.
MDIV
MDIV
Clock Divisor
(fSCLK = 32.768 kHz)
T0IN
Frequency
000
1
32.768 kHz
001
2
16.384 kHz
010
4
8.192 kHz
011
8
4.096 kHz
100
16
2.056 kHz
101
32
1.024 kHz
Other
Reserved
N/A
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LTWCP
MDIV
0
Res. WDSDME WDCT0I LWDCNT LTWMT0 LTWCP LTWCFG
LTWCFG
0
21.4.3
TWM Timer 0 Register (TWMT0)
The TWMT0 register is a word-wide, read/write register that
defines the T0OUT interrupt rate. At reset, TWMT0 register
is initialized to FFFFh. The register format is shown below.
15
0
PRESET
PRESET
134
The Timer T0 Preset field holds the value
used to reload Timer T0 on each underflow.
Therefore, the frequency of the Timer T0 interrupt is the frequency of T0IN divided by
(PRESET+1). The allowed values of PRESET
are 0001h through FFFFh.
TWMT0 Control and Status Register (T0CSR)
21.4.5
The T0CSR register is a byte-wide, read/write register that
controls Timer T0 and shows its current status. At reset, the
non-reserved bits of the register are cleared. The register
format is shown below.
7
5
Reserved
4
3
FRZT0E WDLTD
2
1
0
T0INTE
TC
RST
Watchdog Count Register (WDCNT)
The WDCNT register is a byte-wide, write-only register that
holds the value that is loaded into the Watchdog counter
each time the Watchdog is serviced. The Watchdog is started by the first write to this register. Each successive write to
this register restarts the Watchdog count with the written
value. At reset, this register is initialized to 0Fh.
7
0
PRESET
T0INTE
FRZT0E
Watchdog Service Data Match Register
(WDSDM)
te
The WSDSM register is a byte-wide, write-only register
used for servicing the Watchdog. When this type of servicing is enabled (TWCFG.WDSDME = 1), the Watchdog is
serviced by writing the value 5Ch to the WSDSM register.
Each such servicing reloads the Watchdog counter with the
value previously written to the WDCNT register. Writing any
data other than 5Ch triggers a Watchdog error. Writing to
the register more than once in one Watchdog clock cycle
also triggers a Watchdog error signal. If this type of servicing is disabled (TWCFG.WDSDME = 0), any write to the
WSDSM register is ignored.
7
0
RSTDATA
21.5
WATCHDOG PROGRAMMING
PROCEDURE
The highest level of protection against software errors is
achieved by programming and then locking the Watchdog
registers and using the WDSDM register for servicing. This
is the procedure:
O
WDLTD
21.4.6
ol
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TC
The Restart bit is used to reset Timer T0.
When this bit is set, it forces the timer to reload the value in the TWMT0 register on the
next rising edge of the selected input clock.
The RST bit is reset automatically by the hardware on the same rising edge of the selected
input clock. Writing a 0 to this bit position has
no effect. At reset, the non-reserved bits of the
register are cleared.
0 – Writing 0 has no effect.
1 – Writing 1 resets Timer T0.
The Terminal Count bit is set by hardware
when the Timer T0 count reaches zero and is
cleared when software reads the T0CSR register. It is a read-only bit. Any data written to
this bit position is ignored. The TC bit is not
cleared if FREEZE mode is asserted by an external debugging system.
0 – Timer T0 did not count down to 0.
1 – Timer T0 counted down to 0.
The Timer T0 Interrupt Enable bit enables an
interrupt to the CPU each time the Timer T0
count reaches zero. When this bit is clear,
Timer T0 interrupts are disabled.
0 – Timer T0 interrupts disabled.
1 – Timer T0 interrupts enabled.
The Watchdog Last Touch Delay bit is set
when either WDCNT or WDSDM is written
and the data transfer to the Watchdog is in
progress (see WDCNT and WDSDM register
description). When clear, it is safe to switch to
Power Save mode.
0 – No data transfer to the Watchdog is in
progress, safe to enter Power Save mode.
1 – Data transfer to the Watchdog in
progress.
The Freeze Timer0 Enable bit controls whether TImer 0 is stopped in FREEZE mode. If this
bit is set, the Timer 0 is frozen (stopped) when
the FREEZE input to the TWM is asserted. If
the FRZT0E bit is clear, only the Watchdog
timer is frozen by asserting the FREEZE input
signal. After reset, this bit is clear.
0 – Timer T0 unaffected by FREEZE mode.
1 – Timer T0 stopped in FREEZE mode.
bs
RST
135
1. Write the desired values into the TWM Clock Prescaler
register (TWCP) and the TWM Timer 0 register
(TWMT0) to control the T0IN and T0OUT clock rates.
The frequency of T0IN can be programmed to any of
six frequencies ranging from 1/32 × fSLCLK to fSLCLK.
The frequency of T0OUT is equal to the frequency of
T0IN divided by (1+ PRESET), in which PRESET is the
value written to the TWMT0 register.
2. Configure the Watchdog clock to use either T0IN or
T0OUT by setting or clearing the TWCFG.WDCT0I bit.
3. Write the initial value into the WDCNT register. This
starts operation of the Watchdog and specifies the
maximum allowed number of Watchdog clock cycles
between service operations.
4. Set the T0CSR.RST bit to restart the TWMT0 timer.
5. Lock the Watchdog registers and enable the Watchdog
Service Data Match Enable function by setting bits 0, 1,
2, 3, and 5 in the TWCFG register.
6. Service the Watchdog by periodically writing the value
5Ch to the WDSDM register at an appropriate rate.
Servicing must occur at least once per period programmed into the WDCNT register, but no more than
once in a single Watchdog input clock cycle.
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CP3UB17
21.4.4
Dual Independent Timer mode, which generates system
timing signals.
The Multi-Function Timer module contains a pair of 16-bit
timer/counters. Each timer/counter unit offers a choice of
clock sources for operation and can be configured to operate in any of the following modes:
The timer unit uses an I/O pin called TA, which is an alternate function of the PI7 port pin.
Processor-Independent Pulse Width Modulation (PWM)
mode, which generates pulses of a specified width and
duty cycle, and which also provides a general-purpose
timer/counter.
Input Capture mode, which measures the elapsed time
between occurrences of external events, and which also
provides a general-purpose timer/counter.
TIMER STRUCTURE
Figure 48 is a block diagram showing the internal structure
of the MFT. There are two main functional blocks: a Timer/
Counter and Action block and a Clock Source block. The
Timer/Counter and Action block contains two separate timer/counter units, called Timer/Counter 1 and Timer/Counter
2.
Timer/Counter
Clock Source
Action
Reload/Capture A
TCRA
te
Clock Prescaler/Selector
Timer/Counter 1
TCNT1
Reload/Capture B
TCRB
Timer/Counter 2
TCNT2
TA
Interrupt A
Interrupt B
ol
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System
Clock
22.1
Toggle/Capture/Interrupt
CP3UB17
22.0 Multi-Function Timer
External Event
PWM/Capture/Counter
Mode Select + Control
DS165
Figure 48. Multi-Function Timer Block Diagram
22.1.1
Timer/Counter Block
The Timer/Counter block contains the following functional
blocks:
O
bs
Two 16-bit counters, Timer/Counter 1 (TCNT1) and Timer/Counter 2 (TCNT2)
Two 16-bit reload/capture registers, TCRA and TCRB
Control logic necessary to configure the timer to operate
in any of the four operating modes
Interrupt control and I/O control logic
In a power-saving mode that uses the low-frequency
(32.768 kHz) clock as the System Clock, the synchronization circuit requires that the Slow Clock operate at no more
than one-fourth the speed of the 32.768 kHz System Clock.
22.1.2
Clock Source Block
The Clock Source block generates the signals used to clock
the two timer/counter registers. The internal structure of the
Clock Source block is shown in Figure 49.
No Clock
Counter 1
Clock
Select
Counter 1
Clock
Counter 2
Clock
Select
Counter 2
Clock
Prescaler Register
TPRSC
Reset
System
Clock
5-Bit
Prescaler Counter
DS164
Figure 49.
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Prescaled Clock
Multi-Function Timer Clock Source
136
TIMER OPERATING MODES
Slow Clock
ol
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The Slow Clock is generated by the Triple Clock and Reset
module. The clock source is either the divided fast clock or
the external 32.768 kHz crystal oscillator (if available and
selected). The Slow Clock can be used as the clock source
for the two 16-bit counters. Because the Slow Clock can be
asynchronous to the System Clock, a circuit is provided to
synchronize the clock signal to the high-frequency System
Clock before it is used for clocking the counters. The synchronization circuit requires that the Slow Clock operate at
no more than one-fourth the speed of the System Clock.
te
There are two clock source selectors that allow software to Each timer/counter unit can be configured to operate in any
independently select the clock source for each of the two of the following modes:
16-bit counters from any one of the following sources:
Processor-Independent Pulse Width Modulation (PWM)
No clock (which stops the counter)
mode
Prescaled System Clock
Input Capture mode
Slow Clock (derived from the low-frequency oscillator or Dual Independent Timer mode
divided from the high-speed oscillator)
At reset, the timers are disabled. To configure and start the
timers, software must write a set of values to the registers
Prescaler
that control the timers. The registers are described in
The 5-bit clock prescaler allows software to run the timer
Section 22.5.
with a prescaled clock signal. The prescaler consists of a 5bit read/write prescaler register (TPRSC) and a 5-bit down
counter. The System Clock is divided by the value contained
in the prescaler register plus 1. Therefore, the timer clock
period can be set to any value from 1 to 32 divisions of the
System Clock period. The prescaler register and down
counter are both cleared upon reset.
Limitations in Low-Power Modes
bs
The Power Save mode uses the Slow Clock as the System
Clock. In this mode, the Slow Clock cannot be used as a
clock source for the timers because that would drive both
clocks at the same frequency, and the clock ratio needed for
synchronization to the System Clock would not be maintained. However, the External Event Clock and Pulse Accumulate Mode will still work, as long as the external event
pulses are at least the size of the whole slow-clock period.
Using the prescaled System Clock will also work, but at a
much slower rate than the original System Clock.
O
Idle and Halt modes stop the System Clock (the high-frequency and/or low-frequency clock) completely. If the System Clock is stopped, the timer stops counting until the
System Clock resumes operation.
In the Idle or Halt mode, the System Clock stops completely,
which stops the operation of the timers. In that case, the timers stop counting until the System Clock resumes operation.
137
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CP3UB17
22.2
Counter Clock Source Select
CP3UB17
22.2.1
Mode 1: Processor-Independent PWM
functions as the time base for the PWM timer. It counts
down at the clock rate selected for the counter. When an underflow occurs, the timer register is reloaded alternately
from the TCRA and TCRB registers, and counting proceeds
downward from the loaded value.
Mode 1 is the Processor-Independent Pulse Width Modulation (PWM) mode, which generates pulses of a specified
width and duty cycle, and which also provides a separate
general-purpose timer/counter.
Figure 50 is a block diagram of the Multi-Function Timer
configured to operate in Mode 1. Timer/Counter 1 (TCNT1)
Reload A = Time 1
TCRA
TAPND
Timer
Interrupt A
Underflow
TAIEN
Timer 1
Clock
Timer/Counter 1
TCNT1
TA
TAEN
Underflow
te
Timer
Interrupt B
TBIEN
Timer 2
Clock
TBPND
ol
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Reload B = Time 2
TCRB
Timer/Counter 2
TCNT2
Timer
Interrupt D
TDIEN
TDPND
Figure 50.
Processor-Independent PWM Mode
bs
On the first underflow, the timer is loaded from the TCRA
register, then from the TCRB register on the next underflow,
then from the TCRA register again on the next underflow,
and so on. Every time the counter is stopped and restarted,
it always obtains its first reload value from the TCRA register. This is true whether the timer is restarted upon reset, after entering Mode 1 from another mode, or after stopping
and restarting the clock with the Timer/Counter 1 clock selector.
O
The timer can be configured to toggle the TA output bit on
each underflow. This generates a clock signal on the TA output with the width and duty cycle determined by the values
stored in the TCRA and TCRB registers. This is a “processor-independent” PWM clock because once the timer is set
up, no more action is required from the CPU to generate a
continuous PWM signal.
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DS166
The timer can be configured to generate separate interrupts
upon reload from the TCRA and TCRB registers. The interrupts can be enabled or disabled under software control.
The CPU can determine the cause of each interrupt by looking at the TAPND and TBPND bits, which are updated by
the hardware on each occurrence of a timer reload.
In Mode 1, Timer/Counter 2 (TCNT2) can be used either as
a simple system timer, an external event counter, or a pulseaccumulate counter. The clock counts down using the clock
selected with the Timer/Counter 2 clock selector. It generates an interrupt upon each underflow if the interrupt is enabled with the TDIEN bit.
138
Mode 2: Input Capture
ture timer depends on Timer/Counter 1, which counts down
using the clock selected with the Timer/Counter 1 clock selector. The TA pin functions as a capture input. A transition
received on the TA pin transfers the timer contents to the
TCRA register. The TA pin can be configured to sense either
rising or falling edges.
Mode 2 is the Input Capture mode, which measures the
elapsed time between occurrences of external events, and
which also provides a separate general-purpose timer/
counter.
Figure 51 is a block diagram of the Multi-Function Timer
configured to operate in Mode 2. The time base of the cap-
Timer
Interrupt 1
TAIEN
TAPND
Capture A
TCRA
TA
Preset
Timer/Counter 1
TCNT1
TCPND
te
TAEN
Timer 1
Clock
Underflow
Timer
Interrupt 1
TCIEN
TDPND
Timer/Counter 2
TnCNT2
Underflow
ol
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Timer 2
Clock
TDIEN
Timer
Interrupt 2
DS167
Figure 51. Input Capture Mode
In Mode 2, Timer/Counter 2 (TCNT2) can be used as a simple system timer. The clock counts down using the clock selected with the Timer/Counter 2 clock selector. It generates
an interrupt upon each underflow if the interrupt is enabled
with the TDIEN bit.
bs
The TA input can be configured to preset the counter to
FFFFh on reception of a valid capture event. In this case,
the current value of the counter is transferred to the corresponding capture register and then the counter is preset to
FFFFh. Using this approach allows software to determine
the on-time and off-time and period of an external signal
with a minimum of CPU overhead.
The values captured in the TCRA register at different times
reflect the elapsed time between transitions on the TA pin.
The input signal on the TA pin must have a pulse width equal
to or greater than one System Clock cycle.
O
There are two separate interrupts associated with the capture timer, each with its own enable bit and pending bit. The
interrupt events are reception of a transition on the TA pin
and underflow of the TCNT1 counter. The enable bits for
these events are TAIEN and TCIEN, respectively.
139
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CP3UB17
22.2.2
CP3UB17
22.2.3
Mode 3: Dual Independent Timer/Counter
Figure 52 is a block diagram of the Multi-Function Timer
configured to operate in Mode 3. The timer is configured to
operate as a dual independent system timer or dual external
event counter. In addition, Timer/Counter 1 can generate a
50% duty cycle PWM signal on the TA pin.
Mode 3 is the Dual Independent Timer mode, which generates system timing signals or counts occurrences of external events.
Reload A
TCRA
TAPND
Timer
Interrupt 1
Underflow
TAIEN
Timer 1
Clock
Timer/Counter 1
TCNT1
TA
TAEN
te
Reload B
TCRB
Timer
Interrupt 2
Underflow
TDIEN
Timer 2
Clock
Timer/Counter 2
TCNT2
TDPND
ol
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DS168
Figure 52. Dual-Independent Timer/Counter Mode
Timer/Counter 2 (TCNT2) counts down at the rate of the selected clock. On underflow, it is reloaded from the TCRB
register and counting proceeds down from the reloaded value. In addition, each underflow sets the TDPND interrupt
pending bit and generates an interrupt if the interrupt is enabled by the TDIEN bit.
bs
Timer/Counter 1 (TCNT1) counts down at the rate of the selected clock. On underflow, it is reloaded from the TCRA
register and counting proceeds down from the reloaded value. In addition, the TA pin is toggled on each underflow if this
function is enabled by the TAEN bit. The initial state of the
TA pin is software-programmable. When the TA pin is toggled from low to high, it sets the TCPND interrupt pending
bit and also generates an interrupt if enabled by the TAIEN
bit.
O
Because the TA pin toggles on every underflow, a 50% duty
cycle PWM signal can be generated on the TA pin without
any further action from the CPU.
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140
TIMER INTERRUPTS
22.4
Each Multi-Function Timer unit has four interrupt sources,
designated A, B, C, and D. Interrupt sources A, B, and C are
mapped into a single system interrupt called Timer Interrupt
1, while interrupt source D is mapped into a system interrupt
called Timer Interrupt 2. Each of the four interrupt sources
has its own enable bit and pending bit. The enable bits are
named TAIEN, TBIEN, TCIEN, and TDIEN. The pending
bits are named TAPND, TBPND, TCPND, and TDPND.
TIMER I/O FUNCTIONS
Table 49 shows the functions of the TA pin in each operating
mode, and for each combination of enable bit settings.
When the TA pin is configured to operate as a PWM output
(TAEN = 1), the state of the pin is toggled on each underflow
of the TCNT1 counter. In this case, the initial value on the
pin is determined by the TAOUT bit. For example, to start
with TA high, software must set the TAOUT bit before enabling the timer clock. This option is available only when the
timer is configured to operate in Mode 1 or 3 (in other words,
when TCRA is not used in Capture mode).
Timer Interrupts 1 and 2 are system interrupts TA and TB
(IRQ14 and IRQ13), respectively.
Table 48 shows the events that trigger interrupts A, B, C,
and D in each of the four operating modes. Note that some
interrupt sources are not used in some operating modes.
Table 48 Timer Interrupts Overview
Dual Input Capture +
Counter
Dual Counter
TAPND
TCNT1 reload from TCRA Input capture on TA transition TCNT1 reload from TCRA
TBPND
TCNT1 reload from TCRB Input Capture on TB
transition
TCPND
Timer
Int. 2
(TB Int.)
Mode 3
te
Timer
Int. 1
(TA Int.)
PWM + Counter
Mode 2
TDPND
ol
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Sys. Int.
Mode 1
Interrupt
Pending
Bit
N/A
N/A
TCNT1 underflow
N/A
TCNT2 underflow
TCNT2 underflow
TCNT2 reload from TCRB
Table 49 Timer I/O Functions
Mode 1
PWM + Counter
Mode 2
Mode 3
Dual Input Capture +
counter
Dual Counter
TAEN = 0
TBEN = X
No Output
Capture TCNT1 into TCRA
No Output Toggle
TAEN = 1
TBEN = X
Toggle Output on
Underflow of TCNT1
Capture TCNT1 into TCRA
and Preset TCNT1
Toggle Output on Underflow
of TCNT1
O
TA
bs
I/O
TAEN
TBEN
141
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CP3UB17
22.3
CP3UB17
22.5
TIMER REGISTERS
22.5.2
The TCKC register is a byte-wide, read/write register that
selects the clock source for each timer/counter. Selecting
the clock source also starts the counter. This register is
cleared on reset, which disables the timer/counters. The
register format is shown below.
Table 50 lists the CPU-accessible registers used to control
the Multi-Function Timers.
Table 50 Multi-Function Timer Registers
Name
Address
Description
TPRSC
FF FF48h
Clock Prescaler
Register
TCKC
FF FF4Ah
Clock Unit Control
Register
TCNT1
FF FF40h
Timer/Counter 1
Register
TCNT2
FF FF46h
Timer/Counter 2
Register
TCRA
FF FF42h
Reload/Capture A
Register
TCRB
FF FF44h
Reload/Capture B
Register
TCTRL
FF FF4Ch
Timer Mode
Control Register
TICTL
FF FF4Eh
Timer Interrupt
Control Register
TICLR
FF FF50h
Timer Interrupt
Clear Register
7
bs
4
Reserved
0
CLKPS
The Clock Prescaler field specifies the divisor
used to generate the Timer Clock from the
System Clock. When the timer is configured to
use the prescaled clock, the System Clock is
divided by (CLKPS + 1) to produce the timer
clock. Therefore, the System Clock divisor
can range from 1 to 32.
O
CLKPS
3
C2CSEL
0
C1CSEL
The Counter 1 Clock Select field specifies the
clock mode for Timer/Counter 1 as follows:
000 – No clock (Timer/Counter 1 stopped,
modes 1, 2, and 3 only).
001 – Prescaled System Clock.
010 – Reserved.
011 – Reserved.
100 – Slow Clock.*
101 – Reserved.
110 – Reserved.
111 – Reserved.
The Counter 2 Clock Select field specifies the
clock mode for Timer/Counter 2 as follows:
000 – No clock (Timer/Counter 2 stopped,
modes 1, 2, and 3 only).
001 – Prescaled System Clock.
010 – Reserved.
011 – Reserved.
100 – Slow Clock*
101 – Reserved.
110 – Reserved.
111 – Reserved.
* Operation of the Slow Clock is determined by the CRCTRL.SCLK control bit, as described in Section 11.8.1.
22.5.3
Timer/Counter 1 Register (TCNT1)
The TCNT1 register is a word-wide, read/write register that
holds the current count value for Timer/Counter 1. The register contents are not affected by a reset and are unknown
after power-up.
15
0
TCNT1
22.5.4
Timer/Counter 2 Register (TCNT2)
The TCNT2 register is a word-wide, read/write register that
holds the current count value for Timer/Counter 2. The register contents are not affected by a reset and are unknown
after power-up.
15
0
TCNT2
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2
te
Clock Prescaler Register (TPRSC)
5
5
ol
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C2CSEL
The TPRSC register is a byte-wide, read/write register that
holds the current value of the 5-bit clock prescaler (CLKPS).
This register is cleared on reset. The register format is
shown below.
7
6
Reserved
C1CSEL
22.5.1
Clock Unit Control Register (TCKC)
142
Reload/Capture A Register (TCRA)
TAEN
The TA Enable bit controls whether the TA pin
is enabled to operate as a preset input or as a
PWM output, depending on the timer operating mode. In Mode 2 (Dual Input Capture), a
transition on the TA pin presets the TCNT1
counter to FFFFh. In the other modes, TA
functions as a PWM output. When this bit is
clear, operation of the pin for the timer/counter
is disabled.
0 – TA input disabled.
1 – TA input enabled.
The TA Output Data bit indicates the current
state of the TA pin when the pin is used as a
PWM output. The hardware sets and clears
this bit, but software can also read or write this
bit at any time and therefore control the state
of the output pin. In case of conflict, a software
write has precedence over a hardware update. This bit setting has no effect when the
TA pin is used as an input.
0 – TA pin is low.
1 – TA pin is high.
The Timer Enable bit controls whether the
Multi-Function Timer is enabled. When the
module is disabled all clocks to the counter
unit are stopped to minimize power consumption. For that reason, the timer/counter registers (TCNT1 and TCNT2), the capture/reload
registers (TCRA and TCRB), and the interrupt
pending bits (TXPND) cannot be written in
this mode. Also, the 5-bit clock prescaler and
the interrupt pending bits are cleared, and the
TA I/O pin becomes an input.
0 – Multi-Function Timer is disabled.
1 – Multi-Function Timer is enabled.
The TCRA register is a word-wide, read/write register that
holds the reload or capture value for Timer/Counter 1. The
register contents are not affected by a reset and are unknown after power-up.
15
0
TCRA
22.5.6
TAOUT
Reload B Register (TCRB)
15
0
TCRB
22.5.7
TEN
Timer Mode Control Register (TCTRL)
7
6
5
2
1
0
TAEDG MDSEL
The Mode Select field sets the operating
mode of the timer/counter as follows:
00 – Mode 1: PWM plus system timer.
01 – Mode 2: Input Capture plus system timer.
10 – Mode 3: Dual Timer/Counter.
11 – Reserved.
The TA Edge Polarity bit selects the polarity of
the edges that trigger the TA input.
0 – TA input is sensitive to falling edges (high
to low transitions).
1 – TA input is sensitive to rising edges (low
to high transitions).
O
TAEDG
3
Res.
bs
MDSEL
4
TAEN
ol
e
The TCTRL register is a byte-wide, read/write register that
sets the operating mode of the timer/counter and the TA pin.
This register is cleared at reset. The register format is
shown below.
TEN TAOUT Res.
te
The TCRB register is a word-wide, read/write register that
holds the reload value for Timer/Counter 2. The register
contents are not affected by a reset and are unknown after
power-up.
22.5.8
Timer Interrupt Control Register (TICTL)
The TICTL register is a byte-wide, read/write register that
contains the interrupt enable bits and interrupt pending bits
for the four timer interrupt sources, designated A, B, C, and
D. The condition that causes each type of interrupt depends
on the operating mode, as shown in Table 48.
This register is cleared upon reset. The register format is
shown below.
7
6
5
4
3
2
1
0
TDIEN TCIEN TBIEN TAIEN TDPND TCPND TBPND TAPND
TAPND
143
The Timer Interrupt Source A Pending bit indicates that timer interrupt condition A has occurred. For an explanation of interrupt
conditions A, B, C, and D, see Table 48. This
bit can be set by hardware or by software. To
clear this bit, software must use the Timer Interrupt Clear Register (TICLR). Any attempt
by software to directly write a 0 to this bit is ignored.
0 – Interrupt source A has not triggered.
1 – Interrupt source A has triggered.
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CP3UB17
22.5.5
TAIEN
The TICLR register is a byte-wide, write-only register that allows software to clear the TAPND, TBPND, TCPND, and
TDPND bits in the Timer Interrupt Control (TICTRL) register. Do not modify this register with instructions that access
the register as a read-modify-write operand, such as the bit
manipulation instructions. The register reads as FFh. The
register format is shown below.
7
TCIEN
TDIEN
4
Reserved
TACLR
TBCLR
TCCLR
TDCLR
O
TBIEN
Timer Interrupt Clear Register (TICLR)
3
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2
144
1
0
TDCLR TCCLR TBCLR TACLR
The Timer Pending A Clear bit is used to clear
the Timer Interrupt Source A Pending bit
(TAPND) in the Timer Interrupt Control register (TICTL).
0 – Writing a 0 has no effect.
1 – Writing a 1 clears the TAPND bit.
The Timer Pending A Clear bit is used to clear
the Timer Interrupt Source B Pending bit (TBPND) in the Timer Interrupt Control register
(TICTL).
0 – Writing a 0 has no effect.
1 – Writing a 1 clears the TBPND bit.
The Timer Pending C Clear bit is used to clear
the Timer Interrupt Source C Pending bit
(TCPND) in the Timer Interrupt Control register (TICTL).
0 – Writing a 0 has no effect.
1 – Writing a 1 clears the TCPND bit.
The Timer Pending D Clear bit is used to clear
the Timer Interrupt Source D Pending bit (TDPND) in the Timer Interrupt Control register
(TICTL).
0 – Writing a 0 has no effect.
1 – Writing a 1 clears the TDPND bit.
te
TDPND
22.5.9
ol
e
TCPND
The Timer Interrupt Source B Pending bit indicates that timer interrupt condition B has occurred. For an explanation of interrupt
conditions A, B, C, and D, see Table 48. This
bit can be set by hardware or by software. To
clear this bit, software must use the Timer Interrupt Clear Register (TICLR). Any attempt
by software to directly write a 0 to this bit is ignored.
0 – Interrupt source B has not triggered.
1 – Interrupt source B has triggered.
The Timer Interrupt Source C Pending bit indicates that timer interrupt condition C has occurred. For an explanation of interrupt
conditions A, B, C, and D, see Table 48. This
bit can be set by hardware or by software. To
clear this bit, software must use the Timer Interrupt Clear Register (TICLR). Any attempt
by software to directly write a 0 to this bit is ignored.
0 – Interrupt source C has not triggered.
1 – Interrupt source C has triggered.
The Timer Interrupt Source D Pending bit indicates that timer interrupt condition D has occurred. For an explanation of interrupt
conditions A, B, C, and D, see Table 48. This
bit can be set by hardware or by software. To
clear this bit, software must use the Timer Interrupt Clear Register (TICLR). Any attempt
by software to directly write a 0 to this bit is ignored.
0 – Interrupt source D has not triggered.
1 – Interrupt source D has triggered.
The Timer Interrupt A Enable bit controls
whether an interrupt is generated on each occurrence of interrupt condition A. For an explanation of interrupt conditions A, B, C, and
D, see Table 48.
0 – Condition A interrupts disabled.
1 – Condition A interrupts enabled.
The Timer Interrupt B Enable bit controls
whether an interrupt is generated on each occurrence of interrupt condition B. For an explanation of interrupt conditions A, B, C, and
D, see Table 48.
0 – Condition B interrupts disabled.
1 – Condition B interrupts enabled.
The Timer Interrupt C Enable bit controls
whether an interrupt is generated on each occurrence of interrupt condition C. For an explanation of interrupt conditions A, B, C, and
D, see Table 48.
0 – Condition C interrupts disabled.
1 – Condition C interrupts enabled.
The Timer Interrupt D Enable bit controls
whether an interrupt is generated on each occurrence of interrupt condition D. For an explanation of interrupt conditions A, B, C, and
D, see Table 48.
0 – Condition D interrupts disabled.
1 – Condition D interrupts enabled.
bs
CP3UB17
TBPND
ol
e
te
The VTU contains four fully independent 16-bit timer sub- The VTU controls a total of eight I/O pins, each of which
systems. Each timer subsystem can operate either as dual
can function as either:
8-bit PWM timers, as a single 16-bit PWM timer, or as a 16— PWM output with programmable output polarity
bit counter with 2 input capture channels. These timer sub— Capture input with programmable event detection and
systems offers an 8-bit clock prescaler to accommodate a
timer reset
wide range of system frequencies.
A flexible interrupt scheme with
— Four separate system level interrupt requests
The VTU offers the following features:
— A total of 16 interrupt sources each with a separate in The VTU can be configured to provide:
terrupt pending bit and interrupt enable bit
— Eight fully independent 8-bit PWM channels
23.1
VTU FUNCTIONAL DESCRIPTION
— Four fully independent 16-bit PWM channels
— Eight 16-bit input capture channels
The VTU is comprised of four timer subsystems. Each timer
The VTU consists of four timer subsystems, each of subsystem contains an 8-bit clock prescaler, a 16-bit upwhich contains:
counter, and two 16-bit registers. Each timer subsystem
— A 16-bit counter
controls two I/O pins which either function as PWM outputs
— Two 16-bit capture / compare registers
or capture inputs depending on the mode of operation.
— An 8-bit fully programmable clock prescaler
There are four system-level interrupt requests, one for each
Each of the four timer subsystems can operate in the fol- timer subsystem. Each system-level interrupt request is
lowing modes:
controlled by four interrupt pending bits with associated en— Low power mode, i.e. all clocks are stopped
able/disable bits. All four timer subsystems are fully inde— Dual 8-bit PWM mode
pendent, and each may operate as a dual 8-bit PWM timer,
— 16-bit PWM mode
a 16-bit PWM timer, or as a dual 16-bit capture timer.
— Dual 16-bit input capture mode
Figure 53 shows the main elements of the VTU.
15
0
15
0
MODE
15
INTCTL
15
0
15
INTPND
7
0
Timer Subsystem 4
7
C2 PRSC
C3 PRSC
C4RSC
==
Prescaler
Counter
==
Prescaler
Counter
==
Prescaler
Counter
bs
==
Prescaler
Counter
15
0
15
0
15
0
Count1
Count2
Count3
Count4
Compare - Capture
Compare - Capture
Compare - Capture
Compare - Capture
PERCAP1
PERCAP2
PERCAP3
PERCAP4
Compare - Capture
Compare - Capture
Compare - Capture
Compare - Capture
DTYCAP1
DTYCAP2
DTYCAP3
DTYCAP4
O
15
Timer Subsystem 3
7
C1 PRSC
0
IO2CTL
Timer Subsystem 2
Timer Subsystem 1
7
0
IO1CTL
I/O Control
TIO1
I/O Control
TIO2
I/O Control
TIO3
I/O Control
I/O Control
TIO4
TIO5
I/O Control
TIO6
I/O Control
TIO7
I/O Control
TIO8
DS088
Figure 53. Versatile Timer Unit Block Diagram
145
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CP3UB17
23.0 Versatile Timer Unit (VTU)
CP3UB17
23.1.1
Dual 8-bit PWM Mode
The period of the PWM output waveform is determined by
the value of the PERCAPx register. The TIOx output starts
at the default value as programmed in the IOxCTL.PxPOL
bit. Once the counter value reaches the value of the period
register PERCAPx, the counter is cleared on the next
counter increment. On the following increment from 00h to
01h, the TIOx output will change to the opposite of the default value.
Each timer subsystem may be configured to generate two
fully independent PWM waveforms on the respective TIOx
pins. In this mode, the counter COUNTx is split and operates as two independent 8-bit counters. Each counter increments at the rate determined by the clock prescaler.
Each of the two 8-bit counters may be started and stopped
separately using the corresponding TxRUN bits. Once either of the two 8-bit timers is running, the clock prescaler
starts counting. Once the clock prescaler counter value
matches the value of the associated CxPRSC register field,
COUNTx is incremented.
The duty cycle of the PWM output waveform is controlled by
the DTYCAPx register value. Once the counter value reaches the value of the duty cycle register DTYCAPx, the PWM
output TIOx changes back to its default value on the next
counter increment. Figure 54 illustrates this concept.
COUNTx
0A
PERCAPx
0A
09
09
08
08
06
06
05
05
04
04
DTYCAPx
07
te
07
03
03
02
02
01
ol
e
01
00
00
TxRUN = 1
TIOx (PxPOL = 0)
bs
TIOx (PxPOL = 1)
Figure 54.
VTU PWM Generation
The period time is determined by the following formula:
PWM Period = (PERCAPx + 1) × (CxPRSC + 1) × TCLK
The duty cycle in percent is calculated as follows:
Duty Cycle = (DTYCAPx / (PERCAPx + 1)) × 100
O
DS089
If the duty cycle register (DTYCAPx) holds a value which is
greater than the value held in the period register (PERCAPx) the TIOx output will remain at the opposite of its default value which corresponds to a duty cycle of 100%. If the
duty cycle register (DTYCAPx) register holds a value of 00h,
the TIOx output will remain at the default value which corresponds to a duty cycle of 0%, in which case the value in the
PERCAPx register is irrelevant. This scheme allows the
duty cycle to be programmed in a range from 0% to 100%.
Reading the PERCAPx or DTYCAPx register will always return the most recent value written to it.
The counter registers can be written if both 8-bit counters
are stopped. This allows software to preset the counters before starting, which can be used to generate PWM output
waveforms with a phase shift relative to each other. If the
counter is written with a value other than 00h, it will start incrementing from that value. The TIOx output will remain at
its default value until the first 00h to 01h transition of the
counter value occurs. If the counter is preset to values which
are less than or equal to the value held in the period register
(PERCAPx) the counter will count up until a match between
the counter value and the PERCAPx register value occurs.
The counter will then be cleared and continue counting up.
Alternatively, the counter may be written with a value which
is greater than the value held in the period register. In that
case the counter will count up to FFh, then roll over to 00h.
In any case, the TIOx pin always changes its state at the
00h to 01h transition of the counter.
In order to allow fully synchronized updates of the period
and duty cycle compare values, the PERCAPx and DTYCAPx registers are double buffered when operating in PWM
mode. Therefore, if software writes to either the period or
duty cycle register while either of the two PWM channels is
enabled, the new value will not take effect until the counter Software may only write to the COUNTx register if both
value matches the previous period value or the timer is TxRUN bits of a timer subsystem are clear. Any writes to the
counter register while either timer is running will be ignored.
stopped.
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146
Figure 56 illustrates the configuration of a timer subsystem
while operating in 16-bit PWM mode. The numbering in
Figure 56 refers to timer subsystem 1 but equally applies to
the other three timer subsystems.
The associated TIOx pin will return to its default value as
defined by the IOxCTL.PxPOL bit.
The counter will stop and will retain its last value.
Any pending updates of the PERCAPx and DTYCAPx
register will be completed.
The prescaler counter will be stopped and reset if both
MODE.TxRUN bits are cleared.
7
0
C1PRSC
TMOD1 = 10
==
Prescaler
Counter
T1RUN
Figure 55 illustrates the configuration of a timer subsystem
while operating in dual 8-bit PWM mode. The numbering in
Figure 55 refers to timer subsystem 1 but equally applies to
the other three timer subsystems.
15
0
[15:0]
Restart
Count1[15:0]
Compare
0
PERCAP1[15:0]
C1PRSC
TMOD1 = 01
te
7
==
Prescaler
Counter
Compare
DTYCAP1[15:0]
T2RUN
T1RUN
R
Q
R
0
7
[15:8]
Res
ol
e
S
15
COUNT1[15:8]
S
0
[7:0]
Res
Compare
Q
P2POL
COUNT1[7:0]
P1POL
TIO2
TIO1
Compare
PERCAP1[15:8]
DS091
PERCAP1[7:0]
Figure 56. VTU 16-bit PWM Mode
Compare
Compare
R
S
23.1.3
DTYCAP1[7:0]
bs
DTYCAP1[15:8]
Q
R
Q
S
P2POL
P1POL
TIO2
TIO1
DS090
O
Figure 55. VTU Dual 8-Bit PWM Mode
23.1.2
16-Bit PWM Mode
Dual 16-Bit Capture Mode
In addition to the two PWM modes, each timer subsystem
may be configured to operate in an input capture mode
which provides two 16-bit capture channels. The input capture mode can be used to precisely measure the period and
duty cycle of external signals.
In capture mode the counter COUNTx operates as a 16-bit
up-counter while the two TIOx pins associated with a timer
subsystem operate as capture inputs. A capture event on
the TIOx pins causes the contents of the counter register
(COUNTx) to be copied to the PERCAPx or DTYCAPx registers respectively.
Each of the four timer subsystems may be independently
configured to provide a single 16-bit PWM channel. In this
case the lower and upper bytes of the counter are concatenated to form a single 16-bit counter.
Starting the counter is identical to the 16-bit PWM mode, i.e.
setting the lower of the two MODE.TxRUN bits will start the
counter and the clock prescaler. In addition, the capture
event inputs are enabled once the MODE.TxRUN bit is set.
Operation in 16-bit PWM mode is conceptually identical to
the dual 8-bit PWM operation as outlined under Dual 8-bit
PWM Mode on page 146. The 16-bit timer may be started
or stopped with the lower MODE.TxRUN bit, i.e. T1RUN for
timer subsystem 1.
The TIOx capture inputs can be independently configured to
detect a capture event on either a positive transition, a negative transition or both a positive and a negative transition.
In addition, any capture event may be used to reset the
counter COUNTx and the clock prescaler counter. This
avoids the need for software to keep track of timer overflow
conditions and greatly simplifies the direct frequency and
duty cycle measurement of an external signal.
The two TIOx outputs associated with a timer subsystem
can be used to produce either two identical PWM waveforms or two PWM waveforms of opposite polarities. This
can be accomplished by setting the two PxPOL bits of the
respective timer subsystem to either identical or opposite
values.
147
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CP3UB17
The two I/O pins associated with a timer subsystem function
as independent PWM outputs in the dual 8-bit PWM mode.
If a PWM timer is stopped using its associated
MODE.TxRUN bit the following actions result:
CP3UB17
Figure 57 illustrates the configuration of a timer subsystem
while operating in capture mode. The numbering in
Figure 57 refers to timer subsystem 1 but equally applies to
the other three timer subsystems.
7
23.1.5
The VTU has a total of 16 interrupt sources, four for each of
the four timer subsystems. All interrupt sources have a
pending bit and an enable bit associated with them. All interrupt pending bits are denoted IxAPD through IxDPD
where “x” relates to the specific timer subsystem. There is
one system level interrupt request for each of the four timer
subsystems.
0
C1PRSC
Interrupts
TMOD1=11
==
Prescaler
Counter
Figure 58 illustrates the interrupt structure of the versatile
timer module.
T1RUN
I1AEN
15
0
I1BEN
15:0
Count1[15:0]
Restart
I1CEN
I1DEN
Compare
PERCAP1[15:0]
te
I1APD
Compare
I1BPD
DTYCAP1[15:0]
System
Interrupt
Request 1
I1CPD
I1DPD
cap
rst
rst
2
ol
e
cap
0
2
C1EDG
I4AEN
0
C2EDG
TIO1
I4BEN
TIO2
I4CEN
DS092
Figure 57.
23.1.4
I4DEN
VTU Dual 16-bit Capture Mode
Low Power Mode
I4APD
I4BPD
O
bs
In case a timer subsystem is not used, software can place it
in a low-power mode. All clocks to a timer subsystem are
stopped and the counter and prescaler contents are frozen
once low-power mode is entered. Software may continue to
write to the MODE, INTCTL, IOxCTL, and CLKxPS registers. Write operations to the INTPND register are allowed;
but if a timer subsystem is in low-power mode, its associated interrupt pending bits cannot be cleared. Software cannot write to the COUNTx, PERCAPx, and DTYCAPx
registers of a timer subsystem while it is in low-power mode.
All registers can be read at any time.
Pending Flag
System
Interrupt
Request 4
Table 51
I4CPD
I4DPD
DS093
Figure 58. VTU Interrupt Request Structure
Each of the timer pending bits - IxAPD through IxDPD - is
set by a specific hardware event depending on the mode of
operation, i.e., PWM or Capture mode. Table 51 outlines the
specific hardware events relative to the operation mode
which cause an interrupt pending bit to be set.
VTU Interrupt Sources
Dual 8-bit PWM Mode
16-bit PWM Mode
Capture Mode
IxAPD
Low Byte Duty Cycle match
Duty Cycle match
Capture to PERCAPx
IxBPD
Low Byte Period match
Period match
Capture to DTYCAPx
IxCPD
High Byte Duty Cycle match
N/A
Counter Overflow
IxDPD
High Byte Period match
N/A
N/A
23.1.6
ISE Mode operation
The VTU supports breakpoint operation of the In-SystemEmulator (ISE). If FREEZE is asserted, all timer counter
clocks will be inhibited and the current value of the timer regwww.national.com
isters will be frozen; in capture mode, all further capture
events are disabled. Once FREEZE becomes inactive,
counting will resume from the previous value and the capture input events are re-enabled.
148
VTU REGISTERS
23.2.1
Mode Control Register (MODE)
The VTU contains a total of 19 user accessible registers, as The MODE register is a word-wide read/write register which
listed in Table 52. All registers are word-wide and are initial- controls the mode selection of all four timer subsystems.
ized to a known value upon reset. All software accesses to The register is clear after reset.
the VTU registers must be word accesses.
7
Table 52 VTU Registers
6
5
4
3
2
1
0
TMOD2 T4RUN T3RUN TMOD1 T2RUN T1RUN
Name
Address
Description
MODE
FF FF80h
Mode Control Register
IO1CTL
FF FF82h
I/O Control Register 1
IO2CTL
FF FF84h
I/O Control Register 2
INTCTL
FF FF86h
Interrupt Control
Register
INTPND
FF FF88h
Interrupt Pending
Register
CLK1PS
FF FF8Ah
Clock Prescaler
Register 1
CLK2PS
FF FF98h
Clock Prescaler
Register 2
COUNT1
FF FF8Ch
Counter 1 Register
PERCAP1
FF FF8Eh
Period/Capture 1
Register
DTYCAP1
FF FF90h
Duty Cycle/Capture 1
Register
COUNT2
FF FF92h
PERCAP2
FF FF94h
15
14
13
12
11
10
9
8
TMOD4 T8RUN T7RUN TMOD3 T6RUN T5RUN
The Timer Run bit controls whether the corresponding timer is stopped or running. If set,
the associated counter and clock prescaler is
started depending on the mode of operation.
Once set, the clock to the clock prescaler and
the counter are enabled and the counter will
increment each time the clock prescaler
counter value matches the value defined in
the associated clock prescaler field (CxPRSC).
0 – Timer stopped.
1 – Timer running.
The Timer System Operating Mode field enables or disables the Timer Subsystem and
defines its operating mode.
00 – Low-Power Mode. All clocks to the
counter subsystem are stopped. The
counter is stopped regardless of the value of the TxRUN bits. Read operations
to the Timer Subsystem will return the
last value; software must not perform
any write operations to the Timer Subsystem while it is disabled since those
will be ignored.
01 – Dual 8-bit PWM mode. Each 8-bit
counter may individually be started or
stopped via its associated TxRUN bit.
The TIOx pins will function as PWM outputs.
10 – 16-bit PWM mode. The two 8-bit
counters are concatenated to form a single 16-bit counter. The counter may be
started or stopped with the lower of the
two TxRUN bits, i.e. T1RUN, T3RUN,
T5RUN, and T7RUN. The TIOx pins will
function as PWM outputs.
11 – Capture Mode. Both 8-bit counters are
concatenated and operate as a single
16-bit counter. The counter may be started or stopped with the lower of the two
TxRUN bits, i.e., T1RUN, T3RUN,
T5RUN, and T7RUN. The TIOx pins will
function as capture inputs.
ol
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te
TxRUN
TMODx
Counter 2 Register
bs
Period/Capture 2
Register
DTYCAP2
FF FF96h
Duty Cycle/Capture 2
Register
COUNT3
FF FF9Ah
Counter 3 Register
PERCAP3
FF FF9Ch
Period/Capture 3
Register
FF FF9Eh
Duty Cycle/Capture 3
Register
COUNT4
FF FFA0h
Counter 4 Register
PERCAP4
FF FFA2h
Period/Capture 4
Register
DTYCAP4
FF FFA4h
Duty Cycle/Capture 4
Register
O
DTYCAP3
149
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CP3UB17
23.2
I/O Control Register 1 (IO1CTL)
23.2.3
The I/O Control Register 1 (IO1CTL) is a word-wide read/
write register. The register controls the function of the I/O
pins TIO1 through TIO4 depending on the selected mode of
operation. The register is clear after reset.
6
P2POL
15
P4POL
CxEDG
4
3
C2EDG
14
P1POL
12
C4EDG
2
11
P3POL
The IO2CTL register is a word-wide read/write register. The
register controls the functionality of the I/O pins TIO5
through TIO8 depending on the selected mode of operation.
The register is cleared at reset.
0
7
C1EDG
10
6
P6POL
8
15
C3EDG
4
C6EDG
14
P8POL
3
2
P5POL
12
C8EDG
11
0
C5EDG
10
P7POL
8
C7EDG
The Capture Edge Control field specifies the The functionality of the bit fields of the IO2CTL register is
polarity of a capture event and the reset of the identical to the ones described in the IO1CTL register seccounter. The value of this three bit field has no tion.
effect while operating in PWM mode.
23.2.4 Interrupt Control Register (INTCTL)
CxEDG
Capture
Counter Reset
The INTCTL register is a word-wide read/write register. It
000
Rising edge
No
001
Falling edge
No
010
Rising edge
Yes
011
Falling edge
Yes
100
Both edges
No
101
Both edges
Rising edge
110
Both edges
Falling edge
111
Both edges
Both edges
te
7
I/O Control Register 2 (IO2CTL)
contains the interrupt enable bits for all 16 interrupt sources
of the VTU. Each interrupt enable bit corresponds to an interrupt pending bit located in the Interrupt Pending Register
(INTPND). All INTCTL register bits are solely under software control. The register is clear after reset.
ol
e
CP3UB17
23.2.2
7
6
5
4
3
2
1
0
I2DEN I2CEN I2BEN I2AEN I1DEN I1CEN I1BEN I1AEN
bs
The PWM Polarity bit selects the output polarity. While operating in PWM mode the bit
specifies the polarity of the corresponding IxAEN
PWM output (TIOx). Once a counter is
stopped, the output will assume the value of
PxPOL, i.e., its initial value. The PxPOL bit
has no effect while operating in capture mode.
0 – The PWM output goes high at the 00h to
01h transition of the counter and will go
low once the counter value matches the
duty cycle value.
1 – The PWM output goes low at the 00h to IxBEN
01h transition of the counter and will go
high once the counter value matches the
duty cycle value.
O
PxPOL
15
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14
13
12
11
10
9
8
I4DEN I4CEN I4BEN I4AEN I3DEN I3CEN I3BEN I3AEN
150
The Timer x Interrupt A Enable bit controls interrupt requests triggered on the corresponding IxAPD bit being set. The associated
IxAPD bit will be updated regardless of the
value of the IxAEN bit.
0 – Disable system interrupt request for the
IxAPD pending bit.
1 – Enable system interrupt request for the IxAPD pending bit.
The Timer x Interrupt B Enable bit controls interrupt requests triggered on the corresponding IxBPD bit being set. The associated
IxBPD bit will be updated regardless of the
value of the IxBEN bit.
0 – Disable system interrupt request for the
IxBPD pending bit.
1 – Enable system interrupt request for the IxBPD pending bit.
The Timer x Interrupt C Enable bit controls interrupt requests triggered on the corresponding IxCPD bit being set. The associated
IxCPD bit will be updated regardless of the
value of the IxCEN bit.
0 – Disable system interrupt request for the
IxCPD pending bit.
1 – Enable system interrupt request for the IxCPD pending bit.
Timer x Interrupt D Enable bit controls interrupt requests triggered on the corresponding
IxDPD bit being set. The associated IxDPD bit
will be updated regardless of the value of the
IxDEN bit.
0 – Disable system interrupt request for the
IxDPD pending bit.
1 – Enable system interrupt request for the
IxDPD pending bit.
IxDEN
Interrupt Pending Register (INTPND)
23.2.6
15
5
4
3
2
1
0
I2DPD I2CPD I2BPD I2APD I1DPD I1CPD I1BPD I1APD
15
14
13
12
11
10
9
8
bs
I4DPD I4CPD I4BPD I4APD I3DPD I3CPD I3BPD I3APD
The Timer x Interrupt A Pending bit indicates
that an interrupt condition for the related timer
subsystem has occurred. Table 51 on page
148 lists the hardware condition which causes
this bit to be set.
0 – No interrupt pending.
1 – Timer interrupt condition occurred.
The Timer x Interrupt B Pending bit indicates
that an interrupt condition for the related timer
subsystem has occurred. Table 51 on page
148 lists the hardware condition which causes
this bit to be set.
0 – No interrupt pending.
1 – Timer interrupt condition occurred.
The Timer x Interrupt C Pending bit indicates
that an interrupt condition for the related timer
subsystem has occurred. Table 51 on page
148 lists the hardware condition which causes
this bit to be set.
0 – No interrupt pending.
1 – Timer interrupt condition occurred.
O
IxAPD
IxBPD
IxCPD
8
7
C2PRSC
0
C1PRSC
The Clock Prescaler 1 Compare Value field
holds the 8-bit prescaler value for timer subsystem 1. The counter of timer subsystem is
incremented each time when the clock prescaler compare value matches the value of the
clock prescaler counter. The division ratio is
equal to (C1PRSC + 1). For example, 00h is a
ratio of 1, and FFh is a ratio of 256.
The Clock Prescaler 2 Compare Value field
holds the 8-bit prescaler value for timer subsystem 2. The counter of timer subsystem is
incremented each time when the clock prescaler compare value matches the value of the
clock prescaler counter. The division ratio is
equal to (C2PRSC + 1).
ol
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6
Clock Prescaler Register 1 (CLK1PS)
The CLK1PS register is a word-wide read/write register.
The register is split into two 8-bit fields called C1PRSC and
C2PRSC. Each field holds the 8-bit clock prescaler compare value for timer subsystems 1 and 2 respectively. The
register is cleared at reset.
The INTPND register is a word-wide read/write register C1PRSC
which contains all 16 interrupt pending bits. There are four
interrupt pending bits called IxAPD through IxDPD for each
timer subsystem. Each interrupt pending bit is set by a hardware event and can be cleared if software writes a 1 to the
bit position. The value will remain unchanged if a 0 is written
to the bit position. All interrupt pending bits are cleared (0)
upon reset.
C2PRSC
7
The Timer x Interrupt D Pending bit indicates
that an interrupt condition for the related timer
subsystem has occurred. Table 51 on page
148 lists the hardware condition which causes
this bit to be set.
0 – No interrupt pending.
1 – Timer interrupt condition occurred.
te
23.2.5
IxDPD
23.2.7
Clock Prescaler Register 2 (CLK2PS)
The Clock Prescaler Register 2 (CLK2PS) is a word-wide
read/write register. The register is split into two 8-bit fields
called C3PRSC and C4PRSC. Each field holds the 8-bit
clock prescaler compare value for timer subsystems 3 and
4 respectively. The register is cleared at reset.
15
8
C4PRSC
C3PRSC
C4PRSC
151
7
0
C3PRSC
The Clock Prescaler 3 Compare Value field
holds the 8-bit prescaler value for timer subsystem 3. The counter of timer subsystem is
incremented each time when the clock prescaler compare value matches the value of the
clock prescaler counter. The division ratio is
equal to (C3PRSC + 1).
The Clock Prescaler 4 Compare Value field
holds the 8-bit prescaler value for timer subsystem 4. The counter of timer subsystem is
incremented each time when the clock prescaler compare value matches the value of the
clock prescaler counter. The division ratio is
equal to (C4PRSC + 1).
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CP3UB17
IxCEN
CP3UB17
23.2.8
Counter Register n (COUNTx)
23.2.10 Duty Cycle/Capture Register n (DTYCAPx)
The Counter (COUNTx) registers are word-wide read/write
registers. There are a total of four registers called COUNT1
through COUNT4, one for each of the four timer subsystems. Software may read the registers at any time.
Reading the register will return the current value of the
counter. The register may only be written if the counter is
stopped (i.e. if both TxRUN bits associated with a timer subsystem are clear). The registers are cleared at reset.
15
The Duty Cycle/Capture (DTYCAPx) registers are wordwide read/write registers. There are a total of four registers
called DTYCAP1 through DTYCAP4, one for each timer
subsystem. The registers hold the period compare value in
PWM mode or the counter value at the time the last associated capture event occurred. In PWM mode, the register is
double buffered. If a new duty cycle compare value is written
while the counter is running, the write will not take effect until the counter value matches the previous period compare
value or until the counter is stopped. The update takes effect
on period boundaries only. Reading may take place at any
time and will return the most recent value which was written.
The DTYCAPx registers are cleared at reset.
0
CNTx
Period/Capture Register n (PERCAPx)
15
0
DCAPx
ol
e
The PERCAPx registers are word-wide read/write registers.
There are a total of four registers called PERCAP1 through
PERCAP4, one for each timer subsystem. The registers
hold the period compare value in PWM mode of the counter
value at the time the last associated capture event occurred.
In PWM mode the register is double buffered. If a new period compare value is written while the counter is running, the
write will not take effect until counter value matches the previous period compare value or until the counter is stopped.
Reading may take place at any time and will return the most
recent value which was written. The PERCAPx registers are
cleared at reset.
te
23.2.9
15
0
O
bs
PCAPx
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152
Table 53 is a detailed memory map showing the specific
memory address of the memory, I/O ports, and registers.
The table shows the starting address, the size, and a brief
description of each memory block and register. For detailed
information on using these memory locations, see the applicable sections in the data sheet.
the byte-wide and word-wide registers reside at word
boundaries (even addresses). Therefore, each byte-wide
register uses only the lowest eight bits of the internal data
bus.
Most device registers are read/write registers. However,
some registers are read-only or write-only, as indicated in
the table. An attempt to read a write-only register or to write
a read-only register will have unpredictable results.
All addresses not listed in the table are reserved and must
not be read or written. An attempt to access an unlisted address will have unpredictable results.
When software writes to a register in which one or more bits
Each byte-wide register occupies a single address and can are reserved, it must write a zero to each reserved bit unless
be accessed only in a byte-wide transaction. Each word- indicated otherwise in the description of the register. Readwide register occupies two consecutive memory addresses ing a reserved bit returns an undefined value.
and can be accessed only in a word-wide transaction. Both
Table 53 Detailed Device Mapping
Size
Access
Type
Value After
Reset
Read/Write
00h
Address
Comments
te
Register Name
USB Node Registers
FAR
NFSR
MAEV
MAMSK
ALTEV
TXEV
FF FD80h
Byte
FF FD88h
Read/Write
00h
Byte
FF FD8Ah
Read/Write
00h
Byte
FF FD8Ch
Read/Write
00h
Byte
FF FD8Eh
Read/Write
00h
Byte
FF FD90h
Read/Write
00h
Byte
FF FD92h
Read/Write
00h
bs
ALTMSK
Byte
ol
e
MCNTRL
Byte
FF FD94h
Read/Write
00h
Byte
FF FD96h
Read/Write
00h
Byte
FF FD98h
Read/Write
00h
RXMSK
Byte
FF FD9Ah
Read/Write
00h
NAKEV
Byte
FF FD9Ch
Read/Write
00h
NAKMSK
Byte
FF FD9Eh
Read/Write
00h
FWEV
Byte
FF FDA0h
Read/Write
00h
FWMSK
Byte
FF FDA2h
Read/Write
00h
FNH
Byte
FF FDA4h
Read/Write
C0h
FNL
Byte
FF FDA6h
Read/Write
00h
DMACNTRL
Byte
FF FDA8h
Read/Write
00h
DMAEV
Byte
FF FDAAh
Read/Write
00h
DMAMSK
Byte
FF FDACh
Read/Write
00h
MIR
Byte
FF FDAEh
Read/Write
1Fh
DMACNT
Byte
FF FDB0h
Read/Write
00h
DMAERR
Byte
FF FDB2h
Read/Write
00h
TXMSK
O
RXEV
153
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CP3UB17
24.0 Register Map
Access
Type
Value After
Reset
EPC0
Byte
FF FDC0h
Read/Write
00h
TXD0
Byte
FF FDC2h
Read/Write
TXS0
Byte
FF FDC4h
Read/Write
08h
TXC0
Byte
FF FDC6h
Read/Write
00h
RXD0
Byte
FF FDCAh
Read/Write
XXh
RXS0
Byte
FF FDCCh
Read/Write
00h
RXC0
Byte
FF FDCEh
Read/Write
00h
EPC1
Byte
FF FDD0h
Read/Write
00h
TXD1
Byte
FF FDD2h
Read/Write
XXh
TXS1
Byte
FF FDD4h
Read/Write
1Fh
TXC1
Byte
FF FDD6h
Read/Write
00h
EPC2
Byte
FF FDD8h
Read/Write
00h
RXD1
Byte
FF FDDAh
Read/Write
XXh
RXS1
Byte
FF FDDCh
Read/Write
00h
Byte
FF FDDEh
Read/Write
00h
Byte
FF FDE0h
Read/Write
00h
Byte
FF FDE2h
Read/Write
XXh
Byte
FF FDE4h
Read/Write
1Fh
Byte
FF FDE6h
Read/Write
00h
Byte
FF FDE8h
Read/Write
00h
RXC1
EPC3
TXD2
TXS2
TXC2
RXD2
bs
EPC4
Byte
FF FDEAh
Read/Write
XXh
Byte
FF FDECh
Read/Write
00h
Byte
FF FDEEh
Read/Write
00h
Byte
FF FDF0h
Read/Write
00h
Byte
FF FDF2h
Read/Write
XXh
TXS3
Byte
FF FDF4h
Read/Write
1Fh
TXC3
Byte
FF FDF6h
Read/Write
00h
EPC6
Byte
FF FDF8h
Read/Write
00h
RXD3
Byte
FF FDFAh
Read/Write
XXh
RXS3
Byte
FF FDFCh
Read/Write
00h
RXC3
Byte
FF FDFEh
Read/Write
00h
RXS2
RXC2
EPC5
O
TXD3
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Comments
te
Address
ol
e
CP3UB17
Size
Register Name
154
Size
Address
Access
Type
Value After
Reset
Comments
DMA Controller
Double
Word
FF F800h
Read/Write
0000 0000h
ADRA0
Double
Word
FF F804h
Read/Write
0000 0000h
ADCB0
Double
Word
FF F808h
Read/Write
0000 0000h
ADRB0
Double
Word
FF F80Ch
Read/Write
0000 0000h
BLTC0
Word
FF F810h
Read/Write
0000h
BLTR0
Word
FF F814h
Read/Write
0000h
DMACNTL0
Word
FF F81Ch
Read/Write
0000h
DMASTAT0
Byte
FF F81Eh
Read/Write
00h
Double
Word
FF F820h
Read/Write
0000 0000h
Double
Word
FF F824h
Read/Write
0000 0000h
Double
Word
FF F828h
Read/Write
0000 0000h
Double
Word
FF F82Ch
Read/Write
0000 0000h
Word
FF F830h
Read/Write
0000h
Word
FF F834h
Read/Write
0000h
DMACNTL1
Word
FF F83Ch
Read/Write
0000h
DMASTAT1
Byte
FF F83Eh
Read/Write
00h
Double
Word
FF F840h
Read/Write
0000 0000h
ADRA2
Double
Word
FF F844h
Read/Write
0000 0000h
ADCB2
Double
Word
FF F848h
Read/Write
0000 0000h
ADRB2
Double
Word
FF F84Ch
Read/Write
0000 0000h
BLTC2
Word
FF F850h
Read/Write
0000h
BLTR2
Word
FF F854h
Read/Write
0000h
DMACNTL2
Word
FF F85Ch
Read/Write
0000h
DMASTAT2
Byte
FF F85Eh
Read/Write
00h
Double
Word
FF F860h
Read/Write
0000 0000h
ol
e
ADCA1
ADRA1
ADCB1
BLTR1
O
ADCA2
bs
ADRB1
BLTC1
ADCA3
te
ADCA0
155
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CP3UB17
Register Name
Address
Access
Type
Value After
Reset
ADRA3
Double
Word
FF F864h
Read/Write
0000 0000h
ADCB3
Double
Word
FF F868h
Read/Write
0000 0000h
ADRB3
Double
Word
FF F86Ch
Read/Write
0000 0000h
BLTC3
Word
FF F870h
Read/Write
0000h
BLTR3
Word
FF F874h
Read/Write
0000h
DMACNTL3
Word
FF F87Ch
Read/Write
0000h
DMASTAT3
Byte
FF F87Eh
Read/Write
00h
Bus Interface Unit
Byte
FF F900h
Read/Write
07h
IOCFG
Word
FF F902h
Read/Write
069Fh
SZCFG0
Word
FF F904h
Read/Write
069Fh
Word
FF F906h
Read/Write
069Fh
Word
FF F908h
Read/Write
069Fh
SZCFG2
ol
e
BCFG
SZCFG1
System Configuration
MCFG
MSTAT
Byte
FF F910h
Read/Write
00h
Byte
FF F912h
Read/Write
00h
Byte
FF F914h
Read Only
ENV2:0 pins
bs
DBGCFG
Flash Program Memory Interface
Word
FF F940h
Read/Write
0000h
FMIBDR
Word
FF F942h
Read/Write
0000h
FM0WER
Word
FF F944h
Read/Write
0000h
FM1WER
Word
FF F946h
Read/Write
0000h
FMCTRL
Word
FF F94Ch
Read/Write
0000h
FMSTAT
Word
FF F94Eh
Read/Write
0000h
FMPSR
Byte
FF F950h
Read/Write
04h
FMSTART
Byte
FF F952h
Read/Write
18h
FMTRAN
Byte
FF F954h
Read/Write
30h
FMPROG
Byte
FF F956h
Read/Write
16h
FMPERASE
Byte
FF F958h
Read/Write
04h
FMMERASE0
Byte
FF F95Ah
Read/Write
EAh
O
FMIBAR
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Comments
te
CP3UB17
Size
Register Name
156
Address
Access
Type
Value After
Reset
FMEND
Byte
FF F95Eh
Read/Write
18h
FMMEND
Byte
FF F960h
Read/Write
3Ch
FMRCV
Byte
FF F962h
Read/Write
04h
FMAR0
Word
FF F964h
Read Only
FMAR1
Word
FF F966h
Read Only
FMAR2
Word
FF F968h
Read Only
Comments
Flash Data Memory Interface
Word
FF F740h
Read/Write
0000h
FSMIBDR
Word
FF F742h
Read/Write
0000h
FSM0WER
Word
FF F744h
Read/Write
0000h
FSMCTRL
Word
FF F74Ch
Read/Write
0000h
FSMSTAT
Word
FF F74Eh
Read/Write
0000h
FSMPSR
Byte
FF F750h
Read/Write
04h
Byte
FF F752h
Read/Write
18h
Byte
FF F754h
Read/Write
30h
Byte
FF F756h
Read/Write
16h
Byte
FF F758h
Read/Write
04h
Byte
FF F75Ah
Read/Write
EAh
Byte
FF F75Eh
Read/Write
18h
FSMMEND
Byte
FF F760h
Read/Write
3Ch
FSMRCV
Byte
FF F762h
Read/Write
04h
FSMAR0
Word
FF F764h
Read Only
FSMAR1
Word
FF F766h
Read Only
FSMAR2
Word
FF F768h
Read Only
FSMTRAN
FSMPROG
FSMPERASE
FSMMERASE0
O
bs
FSMEND
ol
e
FSMSTART
te
FSMIBAR
CVSD/PCM Converter
CVSDIN
Word
FF FC20h
Write Only
0000h
CVSDOUT
Word
FF FC22h
Read Only
0000h
PCMIN
Word
FF FC24h
Write Only
0000h
PCMOUT
Word
FF FC26h
Read Only
0000h
LOGIN
Byte
FF FC28h
Write Only
0000h
LOGOUT
Byte
FF FC2Ah
Read Only
0000h
LINEARIN
Word
FF FC2Ch
Write Only
0000h
LINEAROUT
Word
FF FC2Eh
Read Only
0000h
157
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CP3UB17
Size
Register Name
CP3UB17
Size
Address
Access
Type
Value After
Reset
CVCTRL
Word
FF FC30h
Read/Write
0000h
CVSTAT
Word
FF FC32h
Read Only
0000h
CVTEST
Word
FF FC34h
Read/Write
0000h
CVRADD
Word
FF FC36h
Read/Write
0000h
CVRDAT
Word
FF FC38h
Read/Write
0000h
CVDECOUT
Word
FF FC3Ah
Read Only
0000h
CVENCIN
Word
FF FC3Ch
Read Only
0000h
CVENCPR
Word
FF FC3Eh
Read Only
0000h
Register Name
Comments
te
Triple Clock + Reset
Byte
FF FC40h
Read/Write
00X0 0110b
PRSFC
Byte
FF FC42h
Read/Write
4Fh
PRSSC
Byte
FF FC44h
Read/Write
B6h
PRSAC
Byte
FF FC46h
Read/Write
FFh
ol
e
CRCTRL
Power Management
PMMCR
PMMSR
Byte
FF FC60h
Read/Write
00h
Byte
FF FC62h
Read/Write
0000 0XXXb
bs
Multi-Input Wake-Up
Word
FF FC80h
Read/Write
00h
WKENA
Word
FF FC82h
Read/Write
00h
WKICTL1
Word
FF FC84h
Read/Write
00h
WKICTL2
Word
FF FC86h
Read/Write
00h
WKPND
Word
FF FC88h
Read/Write
00h
WKPCL
Word
FF FC8Ah
Write Only
XXh
WKIENA
Word
FF FC8Ch
Read/Write
00h
O
WKEDG
General-Purpose I/O ports
PBALT
Byte
FF FB00h
Read/Write
00h
PBDIR
Byte
FF FB02h
Read/Write
00h
PBDIN
Byte
FF FB04h
Read Only
XXh
PBDOUT
Byte
FF FB06h
Read/Write
XXh
PBWPU
Byte
FF FB08h
Read/Write
00h
PBHDRV
Byte
FF FB0Ah
Read/Write
00h
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158
Bits may only be set;
writing 0 has no effect.
Address
Access
Type
Value After
Reset
PBALTS
Byte
FF FB0Ch
Read/Write
00h
PCALT
Byte
FF FB10h
Read/Write
00h
PCDIR
Byte
FF FB12h
Read Only
00h
PCDIN
Byte
FF FB14h
Read/Write
XXh
PCDOUT
Byte
FF FB16h
Read/Write
XXh
PCWPU
Byte
FF FB18h
Read/Write
00h
PCHDRV
Byte
FF FB1Ah
Read/Write
00h
PCALTS
Byte
FF FB1Ch
Read/Write
00h
Comments
te
I/O ports with Alternate Functions
Byte
FF FCA0h
Read/Write
00h
PGDIR
Byte
FF FCA2h
Read/Write
00h
PGDIN
Byte
FF FCA4h
Read Only
XXh
PGDOUT
Byte
FF FCA6h
Read/Write
XXh
Byte
FF FCA8h
Read/Write
00h
Byte
FF FCAAh
Read/Write
00h
Byte
FF FCACh
Read/Write
00h
Byte
FF FCC0h
Read/Write
00h
Byte
FF FCC2h
Read/Write
00h
Byte
FF FCC4h
Read Only
XXh
PHDOUT
Byte
FF FCC6h
Read/Write
XXh
PHWPU
Byte
FF FCC8h
Read/Write
00h
PHHDRV
Byte
FF FCCAh
Read/Write
00h
PHALTS
Byte
FF FCCCh
Read/Write
00h
PIALT
Byte
FF FEE0h
Read/Write
00h
PIDIR
Byte
FF FEE2h
Read/Write
00h
PIDIN
Byte
FF FEE4h
Read Only
XXh
PIDOUT
Byte
FF FEE6h
Read/Write
XXh
PIWPU
Byte
FF FEE8h
Read/Write
00h
PIHDRV
Byte
FF FEEAh
Read/Write
00h
PIALTS
Byte
FF FEECh
Read/Write
00h
PGWPU
PGHDRV
PGALTS
PHALT
O
PHDIN
bs
PHDIR
ol
e
PGALT
159
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CP3UB17
Size
Register Name
CP3UB17
Register Name
Size
Access
Type
Address
Value After
Reset
Comments
Advanced Audio Interface
Word
FF FD40h
Read Only
0000h
ARDR0
Word
FF FD42h
Read Only
0000h
ARDR1
Word
FF FD44h
Read Only
0000h
ARDR2
Word
FF FD46h
Read Only
0000h
ARDR3
Word
FF FD48h
Read Only
0000h
ATFR
Word
FF FD4Ah
Write Only
XXXXh
ATDR0
Word
FF FD4Ch
Write Only
0000h
ATDR1
Word
FF FD4Eh
Write Only
0000h
ATDR2
Word
FF FD50h
Write Only
0000h
ATDR3
Word
FF FD52h
Write Only
0000h
AGCR
Word
FF FD54h
Read/Write
0000h
AISCR
Word
FF FD56h
Read/Write
0000h
Word
FF FD58h
Read/Write
0004h
Word
FF FD5Ah
Read/Write
F003h
Word
FF FD5Ch
Read/Write
0000h
Word
FF FD5Eh
Read/Write
0000h
ATSCR
ACCR
ADMACR
ol
e
ARSCR
te
ARFR
IVCT
bs
Interrupt Control Unit
Byte
FF FE00h
Read Only
10h
NMISTAT
Byte
FF FE02h
Read Only
00h
EXNMI
Byte
FF FE04h
Read/Write
XXXX 00X0b
Word
FF FE0Ah
Read Only
0000h
Word
FF FE0Ch
Read Only
0000h
IENAM0
Word
FF FE0Eh
Read/Write
0000h
IENAM1
Word
FF FE10h
Read/Write
0000h
ISTAT0
O
ISTAT1
UART
UTBUF
Byte
FF FE40h
Read/Write
XXh
URBUF
Byte
FF FE42h
Read Only
XXh
UICTRL
Byte
FF FE44h
Read/Write
01h
USTAT
Byte
FF FE46h
Read only
00h
UFRS
Byte
FF FE48h
Read/Write
00h
UMDSL1
Byte
FF FE4Ah
Read/Write
00h
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Fixed Addr.
160
Bits 0:1 read only
Address
Access
Type
Value After
Reset
UBAUD
Byte
FF FE4Ch
Read/Write
00h
UPSR
Byte
FF FE4Eh
Read/Write
00h
UOVR
Byte
FF FE50h
Read/Write
00h
UMDSL2
Byte
FF FE52h
Read/Write
00h
USPOS
Byte
FF FE54h
Read/Write
06h
Comments
Microwire/SPI interface
MWDAT
Word
FF FE60h
Read/Write
XXXXh
MWCTL1
Word
FF FE62h
Read/Write
0000h
MWSTAT
Word
FF FE64h
All implemented bits
are 0
te
Read Only
ACBSDA
ACBST
ACBCST
ACBCTL1
ACBADDR
Byte
FF FEC0h
Read/Write
XXh
Byte
FF FEC2h
Read/Write
00h
Byte
FF FEC4h
Read/Write
00h
Byte
FF FEC6h
Read/Write
00h
Byte
FF FEC8h
Read/Write
XXh
Byte
FF FECAh
Read/Write
00h
bs
ACBCTL2
ol
e
ACCESS.bus
ACBADDR2
Byte
FF FECCh
Read/Write
XXh
ACBCTL3
Byte
FF FECEh
Read/Write
00h
Timing and Watchdog
Byte
FF FF20h
Read/Write
00h
TWCP
Byte
FF FF22h
Read/Write
00h
TWMT0
Word
FF FF24h
Read/Write
FFFFh
T0CSR
Byte
FF FF26h
Read/Write
00h
WDCNT
Byte
FF FF28h
Write Only
0Fh
WDSDM
Byte
FF FF2Ah
Write Only
5Fh
O
TWCFG
Multi-Function Timer
TCNT1
Word
FF FF40h
Read/Write
XXh
TCRA
Word
FF FF42h
Read/Write
XXh
TCRB
Word
FF FF44h
Read/Write
XXh
161
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CP3UB17
Size
Register Name
CP3UB17
Size
Address
Access
Type
Value After
Reset
TCNT2
Word
FF FF46h
Read/Write
XXh
TPRSC
Byte
FF FF48h
Read/Write
00h
TCKC
Byte
FF FF4Ah
Read/Write
00h
TCTRL
Byte
FF FF4Ch
Read/Write
00h
TICTL
Byte
FF FF4Eh
Read/Write
00h
TICLR
Byte
FF FF50h
Read/Write
00h
Register Name
Comments
Versatile Timer Unit
Word
FF FF80h
Read/Write
0000h
IO1CTL
Word
FF FF82h
Read/Write
0000h
IO2CTL
Word
FF FF84h
Read/Write
0000h
INTCTL
Word
FF FF86h
Read/Write
0000h
INTPND
Word
FF FF88h
Read/Write
0000h
CLK1PS
Word
FF FF8Ah
Read/Write
0000h
Word
FF FF8Ch
Read/Write
0000h
Word
FF FF8Eh
Read/Write
0000h
Word
FF FF90h
Read/Write
0000h
Word
FF FF92h
Read/Write
0000h
Word
FF FF94h
Read/Write
0000h
Word
FF FF96h
Read/Write
0000h
CLK2PS
Word
FF FF98h
Read/Write
0000h
COUNT3
Word
FF FF9Ah
Read/Write
0000h
PERCAP3
Word
FF FF9Ch
Read/Write
0000h
DTYCAP3
Word
FF FF9Eh
Read/Write
0000h
COUNT4
Word
FF FFA0h
Read/Write
0000h
PERCAP4
Word
FF FFA2h
Read/Write
0000h
DTYCAP4
Word
FF FFA4h
Read/Write
0000h
PERCAP1
DTYCAP1
COUNT2
PERCAP2
O
bs
DTYCAP2
ol
e
COUNT1
te
MODE
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162
The following tables show the functions of the bit fields of the device registers. For more information on using these registers, see the detailed description of the applicable function elsewhere in this data sheet.
USB
Registers
7
6
MCNTRL
FAR
5
Reserved
4
3
2
1
0
HOS
NAT
HALT
Reserved
USBEN
AD_EN
AD[6:0]
NFSR
Reserved
NSF[1:0]
INTR
RX_EV
ULD
NAK
FRAME
TX_EV
ALT
WARN
MAMSK
INTR
RX_EV
ULD
NAK
FRAME
TX_EV
ALT
WARN
ALTEV
RESUME
RESET
SD5
SD3
EOP
DMA
CLKSTB
Reserved
ALTMSK
RESUME
RESET
SD5
SD3
TXUDRRUN[3:0]
TXMSK
TXUDRRUN[3:0]
RXEV
RXOVRRUN[3:0]
RXMSK
NAKEV
NAKMSK
EOP
DMA
CLKSTB
Reserved
TXFIFO[3:0]
TXFIFO[3:0]
RXFIFO[3:0]
ol
e
TXEV
te
MAEV
RXOVRRUN[3:0]
RXFIFO[3:0]
OUT[3:0]
IN[3:0]
OUT[3:0]
IN[3:0]
FWEV
RXWARN[3:1]
Reserved
TXWARN[3:1]
Reserved
FWMSK
RXWARN[3:1]
Reserved
TXWARN[3:1]
Reserved
FNL
MF
DMACNTRL
DMAEV
UL
DEN
IGNRXTGL
Reserved
DMAMSK
Reserved
EPC0
DMOD
NTGL
ARDY
DSIZ
DCNT
DERR
DSHLT
DSIZ
DCNT
DERR
DSHLT
Reserved
Reserved
TXC0
DMAERRCNT[6:0]
DEF
Reserved
ACK_STAT TX_DONE
Red
TCOUNT[4:0]
IGN_IN
FLUSH
TOGGLE
Reserved
TX_EN
RXFD[7:0]
Res.
RXC0
EPC1
EP[3:0]
TXFD[7:0]
RXD0
RXS0
STAT[7:0]
AEH
STALL
DSRC[2:0]
DCOUNT[7:0]
TXD0
TXS0
FN[7:0]
ADMA
DMACNT
DMAERR
FN[10:8]
DTGL
O
MIR
RFC
bs
FNH
SETUP
TOGGLE
RX_LAST
Reserved
STALL
Reserved
ISO
RCOUNT[3:0]
FLUSH
EP_EN
TXD1
IGN_
SETUP
IGN_OUT
RX_EN
EP[3:0]
TXFD[7:0]
163
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CP3UB17
25.0 Register Bit Fields
CP3UB17
USB
Registers
TXS1
7
6
5
4
TX_URUN ACK_STAT TX_DONE
TXC1
IGN_
ISOMSK
EPC2
STALL
TFWL[1:0]
Reserved
ISO
RX_ERR
RXC1
Reserved
EPC3
STALL
RFF
SETUP
TOGGLE
RFWL[1:0]
Reserved
ISO
EPC4
STALL
TX_EN
RX_LAST
Res.
RCOUNT[4:0]
FLUSH
IGN_
SETUP
EP_EN
Reserved
RX_EN
EP[3:0]
TFWL[1:0]
Reserved
ISO
TCOUNT[4:0]
RFF
FLUSH
TOGGLE
EP_EN
LAST
TX_EN
EP[3:0]
RXFD[7:0]
RXS2
RX_ERR
RXC2
Reserved
EPC5
STALL
TXD3
SETUP
TOGGLE
RFWL[1:0]
Reserved
ISO
RX_LAST
Reserved
RCOUNT[4:0]
FLUSH
IGN_
SETUP
EP_EN
Reserved
RX_EN
EP[3:0]
TXFD[7:0]
TX_URUN ACK_STAT TX_DONE
TCOUNT[4:0]
bs
IGN_
ISOMSK
STALL
RX_ERR
Reserved
TFWL[1:0]
Reserved
SETUP
O
RXC3
LAST
EP[3:0]
ol
e
RXD2
RXS3
TOGGLE
te
TX_URUN ACK_STAT TX_DONE
IGN_
ISOMSK
RXD3
0
TXFD[7:0]
TXC2
EPC6
FLUSH
EP_EN
TXD2
TXC3
1
RXFD[7:0]
RXS1
TXS3
2
TCOUNT[4:0]
RXD1
TXS2
3
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ISO
TOGGLE
RFWL[1:0]
RFF
FLUSH
TOGGLE
EP_EN
TX_EN
EP[3:0]
RXFD[7:0]
RX_LAST
Reserved
164
LAST
RCOUNT[4:0]
FLUSH
IGN_
SETUP
Reserved
RX_EN
14
13
12
11
10
9
8
7
6
ADCA
Device A Address Counter
ADRA
Device A Address
ADCB
Device B Address Counter
ADRB
Device B Address
5
BLTC
N/A
Block Length Counter
BLTR
N/A
Block Length
DMACNTL
N/A
Res.
INCB
ADB
7
5
4
MEM_IO_ MISC_IO_
SPEED
SPEED
Reserved
DBGCFG
IND TCS
Reserved
VLD
3
2
USB_
ENABLE
DPGM
BUSY
bs
Reserved
15
12
11
10
9
2
1
0
EO
VR
ETC
CH
EN
CH
OVR
AC
TC
1
SCLKOE
8
7
PGMBUSY
6
0
MCLKOE PLLCLKOE
Reserved
MSTAT
IOCFG
6
DIR
ol
e
MCFG
BCFG
OT
N/A
System Configuration
Registers
BIU
Registers
SW
Res.
RQ
ADA
3
te
DMASTAT
INCA
4
OENV2
5
4
3
EXIOE
FREEZE
ON
OENV1
OENV0
2
1
Reserved
Reserved
EWR
IPST Res.
BW
Reserved
HOLD
WAIT
Reserved
FRE IPRE IPST Res.
BW
WBR RBE
HOLD
WAIT
SZCFG1
Reserved
FRE IPRE IPST Res.
BW
WBR RBE
HOLD
WAIT
SZCFG2
Reserved
FRE IPRE IPST Res.
BW
WBR RBE
HOLD
WAIT
O
SZCFG0
TBI Register
TMODE
7
6
Reserved
5
4
TSTEN
165
0
3
2
ENMEM
1
0
TMSEL
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CP3UB17
DMAC
20..16 15
Registers
15
14
13
FMIBAR
12
11
10
9
8
7
FM0WER
FM0WE[15:0]
FM1WER
FM1WE[15:0]
FM2WER
FM2WE[15:0]
FM3WER
FM3WE[15:0]
FMCTRL
Reserved
MER PER
FMSTAT
Reserved
FMPSR
Reserved
FMPROG
FMPERASE
FMMERASE0
FMEND
FTSTART[7:0]
Reserved
FTTRAN[7:0]
Reserved
FTPROG[7:0]
Reserved
FTPER[7:0]
Reserved
FTMER[7:0]
Reserved
FTEND[7:0]
Reserved
FTMEND[7:0]
Reserved
FTRCV[7:0]
Res.
RDPROT
WRPROT
15
14
13
12
11
10
ISPE
EMPTY
BOOTAREA
CADR15:0
9
8
7
Reserved
6
5
4
3
IBA
FSMIBDR
IBD
FSM0WER
FM0WE[15:0]
FSM1WER
FM1WE[15:0]
FSM2WER
FM2WE[15:0]
FSM3WER
FM3WE[15:0]
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0
IENP DIS
LOW
Res. CWD
ROG VRF
PRW
PE
Reserved
O
FSMIBAR
1
FTDIV[4:0]
bs
FMMEND
Flash
Data Memory
Interface
Registers
2
FM
DE FM
PERR EERR
RR FULL BUSY
Reserved
FMTRAN
FMAR2
3
ol
e
FMSTART
FMAR1
4
IBA
IBD
FMAR0
5
Reserved
FMIBDR
FMRCV
6
te
CP3UB17
Flash
Program
Memory
Interface
Registers
166
2
1
0
15
14
13
FSMCTRL
12
11
10
9
8
Reserved
FSMSTAT
7
6
5
MER PER
4
2
DE FM FM PE
RR FULL BUSY RR
Reserved
FTSTART[7:0]
FSMTRAN
Reserved
FTTRAN[7:0]
FSMPROG
Reserved
FTPROG[7:0]
FSMPERASE
Reserved
FTPER[7:0]
FSMMERASE0
Reserved
FSMEND
Reserved
FSMMEND
Reserved
FSMRCV
Reserved
FTEND[7:0]
FTMEND[7:0]
FTRCV[7:0]
ol
e
FSMAR2
RDPROT
ISPE
15
14
13
12
11
10
9
8
CVSDIN
O
LOGOUT
CVTEST
CVRADD
CVRDAT
6
5
4
3
Reserved
LOGIN
Reserved
LOGOUT
Reserved
2
1
0
PCMOUT
LINEARIN
LINEAROUT
CVSTAT
7
PCMIN
LINEARIN
CVCTRL
BOOTAREA
CVSDOUT
PCMOUT
LOGIN
EMPTY
CVSDIN
CVSDOUT
PCMIN
Res.
CADR15:0
bs
CVSD/PCM
Registers
FTMER[7:0]
Reserved
WRPROT
EE
RR
te
Reserved
FSMAR1
0
FTDIV[3:0]
FSMSTART
FSMAR0
1
IENP DIS
LOW
Res. CWD
ROG VRF
PRW
PE
Reserved
FSMPSR
3
LINEAROUT
PCM
CO
NV
Reserved
CVSD
CONV
CVS
DMA DMA DMA DMA
CVS PCM CLK
DER
PI
PO
CI
CO
DINT INT EN
RINT
CV
EN
PCM CVN
INT
F
CV
NE
CVOUTST
CVINST
CVF CVE
TEST ENC DEC
_VAL _IN _EN
Reserved
Reserved
RT
TB
CVRADD[6:0]
CVRDAT[15:0]
167
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CP3UB17
Flash
Data Memory
Interface
Registers
CP3UB17
CVSD/PCM
Registers
15
14
13
12
11
10
9
CVDECOUT
8
7
6
4
3
2
1
0
CVDECOUT[15:0]
CVENCIN
CVENCIN[15:0]
CVENCPR
CVENCPRT[15:0]
CLK3RES
Registers
7
CRCTRL
6
Reserved
PRSFC
Reserved
5
4
3
2
1
0
POR
ACE2
ACE1
PLLPWD
FCLK
SCLK
MODE
FCDIV
PRSSC
SCDIV
ACDIV2
PMMCR
7
6
5
HCCH
HCCM
DHC
PMMSR
4
3
2
1
0
DMC
WBPSM
HALT
IDLE
PSM
OHC
OMC
OLC
ol
e
PMM Register
ACDIV1
te
PRSAC
Reserved
MIWU16
Registers
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
WKED
bs
WKEDG
WKENA
5
WKINTR6
WKINTR5
WKEN
WKICTL1
WKINTR7
WKINTR4
WKINTR3
WKINTR2
WKINTR1
WKINTR0
WKICTL2
WKINTR15 WKINTR14 WKINTR13 WKINTR12 WKINTR11 WKINTR10
WKINTR9
WKINTR8
WKPD
WKPCL
WKCL
O
WKPND
WKIENA
GPIO Registers
WKIEN
7
6
5
4
3
2
PxALT
Px Pins Alternate Function Enable
PxDIR
Px Port Direction
PxDIN
Px Port Output Data
PxDOUT
Px Port Input Data
PxWPU
Px Port Weak Pull-Up Enable
PxHDRV
Px Port High Drive Strength Enable
PxALTS
Px Pins Alternate Function Source Selection
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168
1
0
15
14
13
12
11
10
9
8
7
6
5
4
3
ARSH
ARSL
ATSR
ATSH
ATSL
ARFR
ARFH
ARFL
ARDR0
ARDH
ARDL
ARDR1
ARDH
ARDL
ARDR2
ARDH
ARDL
ARDR3
ARDH
ARDL
ATFR
ATFH
ARFL
ATDR0
ATDH
ATDL
ATDR1
ATDH
ATDR2
ATDH
ATDR3
ATDH
AAI
IOM2 IFS
EN
ATDL
ATDL
FSL[1:0]
TX
EIC
TX
IC
CTF CRF IEBC FSS IEFS
SCS[1:0]
RX
EIC
RX
IP
AISCR
Reserved
ARSCR
RXFWM[3:0]
RXDSA[3:0]
ATSCR
TXFWM[3:0]
TXDSA[3:0]
ADMACR
ICU Registers
TX
EIP
TX
IP
Reserved
ACO[1:0]
RX
EIP
TX
EIE
LPB DWL ASS
TX
IE
RX
EIE
RX
IE
RXSA[3:0]
RXO RXE RXF
RX
AF
TXSA[3:0]
TXU TXF TXE TXAE
FCPRS[6:0]
ACD{2:0]
15 . . . 12 11 . . . 8
7
6
Reserved
0
0
O
IVCT
RX
IC
BCPRS[7:0]
bs
ACCR
0
ATDL
ol
e
CLK
EN
AGCR
1
te
ARSR
2
TMD[3:0]
5
4
RMD[3:0]
2
1
0
INTVECT[5:0]
ISTAT0
IST(15:0)
ISTAT1
IST(31:16)
IENAM0
IENA(15:0)
IENAM1
IENA(31:16)
169
3
CSS
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CP3UB17
AAI
Registers
CP3UB17
UART
Registers
7
6
5
4
UTBUF
UTBUF
URBUF
URBUF
3
2
1
0
UICTRL
UEEI
UERI
UETI
UEFCI
UCTS
UDCTS
URBF
UTBE
USTAT
Reserved
UXMIP
URB9
UBKD
UERR
UDOE
UFE
UPE
UFRS
Reserved
UPEN
UXB9
USTP
URTS
UFCE
UCKS
UBRK
UMDSL1
UPSEL
UERD
UETD
UBAUD
UATN
UMOD
UDIV[7:0]
UPSR
UPSC[4:0]
UDIV[10:8]
Reserved
UOVSR[3:0]
te
UOVR
UMDSL2
Reserved
Reserved
MWSPI16
Registers
15 . . . 9
MWDAT
8
USMD
USAMP[3:0]
ol
e
USPOS
7
6
5
4
3
2
1
0
EIO
ECHO
MOD
MNS
MWEN
OVR
RBF
BSY
MWDAT
MWCTL1
SCDV
SCIDL
SCM
EIW
ACB Registers
EIR
Reserved
bs
MWSTAT
7
6
5
4
ACBSDA
ACBST
UCHAR
ACBCST
SLVSTP
SDAST
ARPMATCH MATCHAF
STASTRE
ACBADDR
SAEN
O
ACBCTL1
NMINTE
ACBCTL3
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2
1
0
DATA
BER
NEGACK
STASTR
NMATCH
MASTER
XMIT
TGSCL
TSDA
GMATCH
MATCH
BB
BUSY
GCMEN
ACK
Reserved
INTEN
STOP
START
ADDR
ACBCTL2
ACBADDR2
3
SCLFRQ[6:0]
SAEN
ENABLE
ADDR
Reserved
ARPEN
170
SCLFRQ[8:7]
15 . . . 8
7
TWCFG
Reserved
TWCP
Reserved
6
5
Reserved
4
3
2
1
0
WDSDME WDCT0I LWDCNT LTWMT0 LTWCP LTWCFG
Reserved
TWMT0
MDIV
PRESET
T0CSR
Reserved
WDCNT
Reserved
PRESET
WDSDM
Reserved
RSTDATA
15 . . . 8
7
6
FRZT0E WDTLD
5
4
3
T0INTE
2
TC
RST
1
0
te
MFT16
Registers
Reserved
TCNT1
TCNT1
TCRA
TCRA
TCRB
TCRB
TCNT2
Reserved
TCKC
Reserved
TCTRL
Reserved
TICTL
Reserved
TICLR
Reserved
Reserved
Reserved
CLKPS
C2CSEL
C1CSEL
TEN
TAOUT
TBEN
TAEN
TBEDG
TAEDG
TDIEN
TCIEN
TBIEN
TAIEN
TDPND
TCPND
TBPND
TAPND
TDCLR
TCCLR
TBCLR
TACLR
Reserved
TMDSEL
O
bs
TPRSC
ol
e
TCNT2
171
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CP3UB17
TWM Registers
CP3UB17
VTU
Registers
MODE
15
14
TMOD4
13
12
T8
T7
RUN RUN
11
10
TMOD3
9
8
T6
T5
RUN RUN
7
6
TMOD2
5
4
T4
T3
RUN RUN
3
2
TMOD1
1
0
T2
T1
RUN RUN
IO1CTL
P4
POL
C4EDG
P3
POL
C3EDG
P2
POL
C2EDG
P1
POL
C1EDG
IO2CTL
P7
POL
C7EDG
P6
POL
C6EDG
P5
POL
C5EDG
P5
POL
C5EDG
INTCTL
I4DEN I4CEN I4BEN I4AEN I3DEN I3CEN I3BEN I3AEN I2DEN I2CEN I2BEN I2AEN I1DEN I1CEN I1BEN I1AEN
INTPND
I4DPD I4CPD I4BPD I4APD I3DPD I3CPD I3BPD I3APD I2DPD I2CPD I2BPD I2APD I1DPD I1CPD I1BPD I1APD
CLK1PS
C2PRSC
CNT1
te
COUNT1
PERCAP1
PCAP1
DTYCAP1
DCAP1
COUNT2
DTYCAP2
CLK2PS
COUNT3
PERCAP3
DTYCAP3
PCAP2
DCAP2
C4PRSC
CNT3
PCAP3
DCAP3
CNT4
bs
COUNT4
CNT2
ol
e
PERCAP2
C1PRSC
PCAP4
DTYCAP4
DCAP4
O
PERCAP4
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172
C3PRSC
26.1
ABSOLUTE MAXIMUM RATINGS
Total current into IOVCC pins
Total current into VCC pins (source)
Total current out of GND pins (sink)
Latch-up immunity
Storage temperature range
If Military/Aerospace specified devices are required, please
contact the National Semiconductor Sales Office/Distributors for availability and specifications.
Supply voltage (VCC)
All input and output voltages with respect to GND*
3.6V
-0.5V to
IOVCC + 0.5V
ESD protection level
2 kV
(Human Body
Model)
Allowable sink/source current per
signal pin
200 mA
200 mA
200 mA
±200 mA
-65°C to +150°C
Note: Absolute maximum ratings indicate limits beyond
which damage to the device may occur. DC and AC electrical specifications are not ensured when operating the device at absolute maximum ratings. *The latch-up tolerance
on ACCESS.bus pins exceeds 150 mA.
±10 mA
Symbol
Parameter
Digital Logic Supply Voltage
IOVcc
I/O Supply Voltage
AVcc
Analog PLL Supply Voltage
UVcc
USB Transceiver Power Supply
Conditions
Min
Max
Units
2.25
2.75
V
2.25
3.63
V
2.25
2.75
V
3.63
V
0.3 Vcc
V
ol
e
Vcc
te
DC ELECTRICAL CHARACTERISTICS (Temperature: -40°C ≤ TA ≤ +85°C)
26.2
2.97
a
Logical 0 Input Voltage
(except X2CKI)
-0.5
VIH
Logical 1 Input Voltage
(except X2CKI)
0.7 IOVcc
IOVcc + 0.5 a V
Vxl1
X1CKI Low Level Input Voltage
External X1 clock
-0.5 a
0.3 Vcc
V
Vxh1
X1CKI High Level Input Voltage OSC
External X1 clock
0.7 Vcc
Vcc + 0.5
V
0.6
V
Vcc + 0.5
V
Vxl2
Vxh2
Vhys
IOH
a
X2CKI Logical 0 Input Voltage
External X2 clock
-0.5
X2CKI Logical 1 Input Voltage
External X2 clock
0.7 Vcc
Hysteresis Loop Width
a
0.1 IOVcc
V
Logical 1 Output Current
VOH = 1.8V,
IOVcc = 2.25V
-1.6
mA
Logical 0 Output Current
VOL = 0.45V,
IOVcc = 2.25V
1.6
mA
O
IOL
bs
VIL
IOLACB
SDA, SCL Logical 0 Output Current
VOL = 0.4V,
IOVcc = 2.25V
3.0
mA
IOHW
Weak Pull-up Current
VOH = 1.8V,
IOVcc =2.25V
-10
µA
IIL
RESET pin Weak Pull-down Current
VIL = 0.45V,
IOVcc = 2.25V
IL
High Impedance Input Leakage Current
0V ≤ Vin ≤ IOVcc
IO(Off)
Output Leakage Current
(I/O pins in input mode)
0V ≤ Vout ≤ Vcc
Icca1
Digital Supply Current Active Mode b
Icca2
Digital Supply Current Active Mode c
0.4
µA
-2.0
2.0
µA
-2.0
2.0
µA
Vcc = 2.75V,
IOVcc = 3.63V
12
mA
Vcc = 2.75V,
IOVcc = 3.63V
8
mA
173
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CP3UB17
26.0 Electrical Characteristics
CP3UB17
Symbol
Parameter
Conditions
Min
Max
Units
Iccprog
Digital Supply Current Active Mode d
Vcc = 2.75V,
IOVcc = 3.63V
15
mA
Iccps
Digital Supply Current Power Save Mode e
Vcc = 2.75V,
IOVcc = 3.63V
4.0
mA
Iccid
Digital Supply Current Idle Mode f
Vcc = 2.75V,
IOVcc = 3.63V
950
µA
Iccq
Digital Supply Current Halt Mode f,g,h
Vcc = 2.75V,
IOVcc = 3.63V
700
µA
ol
e
te
a. Guaranteed by design
b. Test code executing from internal RAM. No peripheral blocks other than PLL and Auxiliary Clock enabled.
X1CLKI is 24 MHz. Not programming Flash memory. Typical applications will show 16 mA (Icca1 + 4 mA) at
24 MHz executing code from flash memory.
c. Waiting for interrupt on executing WAIT instruction, Iout = 0 mA, X1CKI = 12 MHz, PLL enabled (4×), internal
system clock is 24 MHz, not programming Flash memory
d. Same conditions as Icca1, but programming or erasing Flash memory page
e. Running from internal memory (RAM), Iout = 0 mA, XCKI1 = 12 MHz, PLL disabled, X2CKI = 32.768 kHz,
device put in power-save mode, Slow Clock derived from XCKI1
f. Iout = 0 mA, XCKI1 = off, X2CKI = 32.768 kHz
g. USB switched off (suspend)
h. Halt current approximately doubles for every 20°C.
USB TRANSCEIVER ELECTRICAL CHARACTERISTICS (Temperature: -40°C ≤ TA ≤ +85°C)
26.3
Symbol
Parameter
Differential Input Sensitivity
Differential Common Mode Range
VSE
VOL
VOH
VOZ
Single-Ended Receiver Threshold
Output Low Voltage
TRI-STATE Data Line Leakage
0V < VIN < 3.3V
Transceiver Capacitance
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Min
174
Max
Units
-0.2
0.2
V
0.8
2.5
V
0.8
2.0
V
RL = 1.5K ohm to 3.6V
Output High Voltage
O
CTRN
(D+) - (D-)
bs
VDI
VCM
Conditions
0.3
2.8
-10
V
V
10
µA
20
pF
FLASH MEMORY ON-CHIP PROGRAMMING
Symbol
Parameter
Conditions
tSTART
Program/Erase to NVSTR Setup Time
(NVSTR = Non-Volatile Storage
tTRAN
NVSTR to Program Setup Timeb
tMERASE
-
µs
10
-
µs
20
40
µs
20
-
ms
200
-
ms
5
-
µs
100
-
µs
1
-
µs
128K program blocks
-
8
ms
8K data block
-
4
ms
d
Page Erase Pulse Width
Module Erase Pulse Width
NVSTR Hold Time
e
f
NVSTR Hold Time (Module Erase)
g
Recovery Time
tHV
Cumulative Program High Voltage Period For
Each Row After Erasei
Write/Erase Endurance
Data Retention
te
h
tRCV
tHV
5
Programming Pulse Width
tPERASE
tMEND
Max
c
tPROG
tEND
Min
Units
a
25°C
20,000
-
cycles
100
-
years
O
bs
ol
e
a. Program/erase to NVSTR Setup Time is determined by the following equation:
tSTART = Tclk × (FTDIV + 1) × (FTSTART + 1), where Tclk is the System Clock period, FTDIV is the contents of
the FMPSR or FSMPSR register, and FTSTART is the contents of the FMSTART or FSMSTART register
b. NVSTR to Program Setup Time is determined by the following equation:
tTRAN = Tclk × (FTDIV + 1) × (FTTRAN + 1), where Tclk is the System Clock period, FTDIV is the contents of
the FMPSR or FSMPSR register, and FTTRAN is the contents of the FMTRAN or FSMTRAN register
c. Programming Pulse Width is determined by the following equation:
tPROG = Tclk × (FTDIV + 1) × 8 × (FTPROG + 1), where Tclk is the System Clock period, FTDIV is the contents of the FMPSR or FSMPSR register, and FTPROG is the contents of the FMPROG or FSMPROG register
d. Page Erase Pulse Width is determined by the following equation:
tPERASE = Tclk × (FTDIV + 1) × 4096 × (FTPER + 1), where Tclk is the System Clock period, FTDIV is the
contents of the FMPSR or FSMPSR register, and FTPER is the contents of the FMPERASE or FSMPERASE register
e. Module Erase Pulse Width is determined by the following equation:
tMERASE = Tclk × (FTDIV + 1) × 4096 × (FTMER + 1), where Tclk is the System Clock period, FTDIV is the
contents of the FMPSR or FSMPSR register, and FTMER is the contents of the FMMERASE0 or
FSMMERASE0 register
f. NVSTR Hold Time is determined by the following equation:
tEND = Tclk × (FTDIV + 1) × (FTEND + 1), where Tclk is the System Clock period, FTDIV is the contents of the
FMPSR or FSMPSR register, and FTEND is the contents of the FMEND or FSMEND register
g. NVSTR Hold Time (Module Erase) is determined by the following equation:
tMEND = Tclk × (FTDIV + 1) × 8 × (FTMEND + 1), where Tclk is the System Clock period, FTDIV is the contents of the FMPSR or FSMPSR register, and FTMEND is the contents of the FMMEND or FSMMEND register
h. Recovery Time is determined by the following equation:
tRCV = Tclk × (FTDIV + 1) × (FTRCV + 1), where Tclk is the System Clock period, FTDIV is the contents of the
FMPSR or FSMPSR register, and FTRCV is the contents of the FMRCV or FSMRCV register
i. Cumulative program high voltage period for each row after erase tHV is the accumulated duration a flash cell
is exposed to the programming voltage after the last erase cycle.
175
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CP3UB17
26.4
CP3UB17
26.5
OUTPUT SIGNAL LEVELS
The RESET and NMI input pins are active during the Power
Save mode. In order to guarantee that the Power Save curAll output signals are powered by the digital supply (VCC).
rent not exceed 1 mA, these inputs must be driven to a voltTable 54 summarizes the states of the output signals during age lower than 0.5V or higher than VCC - 0.5V. An input
the reset state (when VCC power exists in the reset state) voltage between 0.5V and (VCC - 0.5V) may result in power
and during the Power Save mode.
consumption exceeding 1 mA.
Table 54 Output Pins During Reset and Power-Save
Reset State
(with Vcc)
Signals on a Pin
Power Save Mode
TRI-STATE
Previous state
PC7:0
TRI-STATE
Previous state
PG5, PG3:0
TRI-STATE
Previous state
PH7:0
TRI-STATE
Previous state
PI7:0
TRI-STATE
Previous state
26.6
I/O ports will maintain their values when
entering power-save mode
te
PB7:0
Comments
CLOCK AND RESET TIMING
Table 55 Clock and Reset Signals
Symbol Figure
Reference
ol
e
Description
Min (ns)
Max (ns)
83.33
83.33
Clock Input Signals
Rising Edge (RE) on X1 to
next RE on X1
tX1p
59
X1 period
tX1h
59
X1 high time, external clock
At 2V level (Both Edges)
(0.5 Tclk) - 5
tX1l
59
X1 low time, external clock
At 0.8V level (Both Edges)
(0.5 Tclk) - 5
a
59
X2 period
tX2h
59
X2 high time, external clock
tX2l
tIH
RE on X2 to next RE on X2
At 2V level (both edges)
bs
tX2p
59
X2 low time, external clock
At 0.8V level (both edges)
60
Input hold time (NMI, RXD1, RXD2)
After RE on CLK
10,000
(0.5 Tclk) - 500
(0.5 Tclk) - 500
0
Reset and NMI Input Signals
tIW
NMI Pulse Width
NMI Falling Edge (FE) to
RE
20
61
RESET Pulse Width
RESET FE to RE
100
O
tRST
60
tR
61
Vcc Rise Time
0.1 Vcc to 0.9 Vcc
a. Only when operating with an external square wave on X2CKI; otherwise a 32 kHz crystal network must be
used between X2CKI and X2CKO. If Slow Clock is internally generated from Main Clock, it may not exceed
this given limit.
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176
CP3UB17
tX1p
X1CKI
tX1h
tX1l
tX2p
X2CKI
tX2h
tX2l
te
DS095
Figure 59.
Clock Timing
ol
e
CLK
tlS
NMI
tlH
tIW
NMI Signal Timing
bs
Figure 60.
DS096
CLK
tRST
O
RESET
DS097
Figure 61. Non-Power-On Reset
0.9 VCC
VCC
0.1 VCC
tR
Figure 62.
DS115
Power-On Reset
177
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CP3UB17
26.7
I/O PORT TIMING
Table 56 I/O Port Signals
Symbol Figure
Description
Reference
Min (ns)
Max (ns)
I/O Port Input Signals
tIS
63
Input Setup Time
Before Falling Edge (FE)
on System Clock
22.5
-
tIH
63
Input Hold Time
After FE on System Clock
0
-
-
3
I/O Port Output Signals
63
Output Valid Time
After FE on System Clock
CLK
tIS
Port Input
te
tCOv1
ol
e
tlH
Port Output
tCOv1
tCOv1
DS100
O
bs
Figure 63. I/O Port Timing
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178
CP3UB17
26.8
ADVANCED AUDIO INTERFACE (AAI) TIMING
Table 57 Advanced Audio Interface (AAI) Signals
Symbol Figure
Description
Reference
Min (ns)
Max (ns)
AAI Input Signals
tRDS
64,66 Receive Data Setup Time
Before Falling Edge (FE)
on SRCLK
20
-
tRDH
64,66 Receive Data Hold Time
After FE on SRCLK
20
-
tFSS
64
Frame Sync Setup Time
Before Rising Edge (RE)
on SRCLK
20
-
tFSH
64
Frame Sync Hold Time
After RE on SRCLK
20
-
-
AAI Output Signals
64
Receive/Transmit Clock Period
RE on SRCLK/SCK to RE
on SRCLK/SCK
976.6
tCL
64
Receive/Transmit Low Time
FE on SRCLK/SCK to RE
on SRCLK/SCK
488.3
-
tCH
64
Receive/Transmit High Time
RE on SRCLK/SCK to FE
on SRCLK/SCK
488.3
-
te
tCP
64,66 Frame Sync Valid High
RE on SRCLK/SCK to RE
on SRFS/SFS
-
20
tFSVL
64,66 Frame Sync Valid Low
RE on SRCLK/SCK to FE
on SRFS/SFS
-
20
tTDV
65,67 Transmit Data Valid
RE on SCK to STD Valid
-
20
ol
e
tFSVH
bs
tCP
SRCLK
0
1
tCH
2
tCL
SRFS
O
tFSVH
tFSVL
SRD
0
1
tRDH
tRDS
DS116
Figure 64. Receive Timing, Short Frame Sync
179
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CP3UB17
SCK
0
1
2
SFS
STD
0
1
tTDV
DS117
SRCLK
SRFS
tFSVH
SRD
1
2
N
ol
e
0
Transmit Timing, Short Frame Sync
te
Figure 65.
0
tFSVL
1
tRDH
bs
tRDS
DS118
Figure 66. Receive Timing, Long Frame Sync
0
O
SCK
1
2
N
SFS
STD
0
1
tTDV
DS119
Figure 67.
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Transmit Timing, Long Frame Sync
180
CP3UB17
26.9
MICROWIRE/SPI TIMING
Table 58 Microwire/SPI Signals
Symbol Figure
Description
Reference
Min (ns)
Max (ns)
Microwire/SPI Input Signals
tMSKh
68
Microwire Clock High
At 2.0V (both edges)
80
-
tMSKl
68
Microwire Clock Low
At 0.8V (both edges)
80
-
SCIDL bit = 0; Rising Edge
(RE) MSK to next RE MSK
68
tMSKp
Microwire Clock Period
SCIDL bit = 1; Falling Edge
(FE) MSK to next FE MSK
69
200
-
tMSKh
68
MSK Hold (slave only)
After MWCS goes inactive
40
-
tMSKs
68
MSK Setup (slave only)
Before MWCS goes active
80
-
SCIDL bit = 0: After FE
MSK
te
68
MWCS Hold (slave only)
tMCSh
69
SCIDL bit = 1: After RE
MSK
68
SCIDL bit = 0: Before RE
MSK
tMCSs
MWCS Setup (slave only)
68
SCIDL bit = 1: Before FE
MSK
ol
e
69
Microwire Data In Hold (master)
70
tMDIh
68
Microwire Data In Hold (slave)
Normal Mode: After RE
MSK
Alternate Mode: After FE
MSK
Normal Mode: Before RE
MSK
68
tMDIs
Alternate Mode: After FE
MSK
bs
70
Normal Mode: After RE
MSK
Microwire Data In Setup
Alternate Mode: Before FE
MSK
70
-
40
-
80
0
40
80
-
Microwire/SPI Output Signals
68
Microwire Clock High
At 2.0V (both edges)
40
-
68
Microwire Clock Low
At 0.8V (both edges)
40
-
O
tMSKh
tMSKl
68
tMSKp
Microwire Clock Period
69
SCIDL bit = 0: Rising Edge
(RE) MSK to next RE MSK
SCIDL bit = 1: Falling Edge
(FE) MSK to next FE MSK
tMSKd
68
MSK Leading Edge Delayed (master
only)
Data Out Bit #7 Valid
tMDOf
68
Microwire Data Float b
(slave only)
After RE on MCSn
68
tMDOh
Microwire Data Out Hold
69
tMDOnf
72
Microwire Data No Float (slave only)
Normal Mode: After FE
MSK
Alternate Mode: After RE
MSK
After FE on MWCS
181
100
0.5 tMSK
1.5 tMSK
-
25
-
0.0
0
25
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CP3UB17
Table 58 Microwire/SPI Signals
Symbol Figure
tMDOv
tMITOp
Description
68
Microwire Data Out Valid
72
MDODI to MDIDO
(slave only)
Reference
Normal Mode: After FE on
MSK
Alternate Mode: After RE
on MSK
Propagation Time
Value is the same in all
clocking modes of the
Microwire
Min (ns)
Max (ns)
-
25
-
25
MSK
tMSKh
tMSKs
tMSKhd
ol
e
Data In
tMSKl
te
tMSKp
msb
tMDls
MDIDO
(slave)
lsb
tMDlh
msb
tMDOf
lsb
tMDOv
tMDOff
bs
tMDOh
MDODI
(master)
msb
lsb
tMSKd
O
MCS
(slave)
tMCSs
Figure 68.
www.national.com
tMCSh
Microwire Transaction Timing, Normal Mode, SCIDL = 0
182
DS101
CP3UB17
tMSKp
MSK
tMSKh
tMSKh
tMSKhd
tMSKs
Data In
msb
tMDls
MDIDO
(slave)
lsb
tMDlh
msb
lsb
te
tMDOv
tMDOf
tMDOf
tMDOh
MDODO
(master)
MCS
(slave)
tMCSs
lsb
ol
e
msb
DS102
Microwire Transaction Timing, Normal Mode, SCIDL = 1
O
bs
Figure 69.
tMCSh
183
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CP3UB17
tMSKp
MSK
tMSKhd
tMSKs
tMSKh
Data In
tMSKl
msb
tMDls
MDIDO
(slave)
lsb
tMDlh
msb
lsb
te
tMDOv
tMDOf
tMDOf
tMDOh
MDODO
(master)
MCS
(slave)
tMCSs
lsb
ol
e
msb
tMCSh
O
bs
Figure 70. Microwire Transaction Timing, Alternate Mode, SCIDL = 0
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184
DS103
CP3UB17
tMSKp
MSK
tMSKhd
tMSKs
tMSKh
Data In
tMSKh
msb
lsb
tMDlh
tMDls
MDIDO
(slave)
msb
lsb
tMDOf
tMDOv
tMDOff
MDODI
(master)
te
tMDOh
msb
lsb
ol
e
tSKd
MCS
(slave only)
tMCSs
tMCSh
DS104
bs
Figure 71. Microwire Transaction Timing, Alternate Mode, SCIDL = 1
tMSKp
MSK
tMSKs
tMSKh
MDODI
(slave)
O
Dl msb
tMDls
Dl lsb
tMDlh
tMITOp
MDIDO
(slave)
tMSKhd
tMSKl
tMITOp
DO msb
DO lsb
tMDOnf
tMDOf
MCS
tMCSs
tMCSh
DS105
Figure 72. Microwire Transaction Timing, Data Echoed to Output,
Normal Mode, SCIDL = 0, ECHO = 1, Slave Mode
185
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CP3UB17
26.10
ACCESS.BUS TIMING
Table 59 ACCESS.bus Signals
Symbol Figure
Description
Reference
Min (ns)
Max (ns)
tSCLhigho
-
ACCESS.bus Input Signals
tBUFi
74
Bus free time between Stop and Start
Condition
tCSTOsi
74
SCL setup time
Before Stop Condition
tCSTRhi
74
SCL hold time
After Start Condition
(8 × tCLK) - tSCLri
(8 × tCLK) - tSCLri
tCSTRsi
74
SCL setup time
Before Start Condition
(8 × tCLK) - tSCLri
-
2 × tCLK
-
2 × tCLK
-
-
300
75
Data High setup time
tDLCsi
74
Data Low setup time
Before SCL RE
tSCLfi
73
SCL signal Rise time
tSCLri
73
SCL signal Fall time
tSCLlowi
76
SCL low time
After SCL Falling Edge
(FE)
tSCLhighi
76
SCL high time
After SCL RE
tSDAfl
73
SDA signal Fall time
tSDAri
ol
e
te
tDHCsi
Before SCL Rising Edge
(RE)
-
73
SDA signal Rise time
tSDAhi
76
SDA hold time
After SCL FE
tSDAsi
76
SDA setup time
Before SCL RE
-
1000
16 × tCLK
-
16 × tCLK
-
300
-
1000
0
-
2 × tCLK
-
ACCESS.bus Output Signals
tBUFo
74
Bus free time between Stop and Start
Condition
tCSTOso
74
SCL setup time
tCSTRho
74
SCL hold time
75
SCL setup time
75
Data High setup time
74
Data Low setup time
73
73
tDHCso
tDLCso
tSCLfo
tSCLro
tSCLhigho
-
After Start Condition
tSCLhigho
-
Before Start Condition
tSCLhigho
-
Before SCL R.E.
tSCLhigho -tSDAro
-
Before SCL R.E.
tSCLhigho -tSDAfo
-
SCL signal Fall time
-
300 c
SCL signal Rise time
-
76
SCL low time
O
tSCLlowo
-
Before Stop Condition
bs
tCSTRso
tSCLhigho
After SCL F.E.
-d
(K × tCLK)
-1e
(K × tCLK)
-1e
-
76
SCL high time
tSDAfo
73
SDA signal Fall time
-
300
tSDAro
73
SDA signal Rise time
-
-
tSDAho
76
SDA hold time
After SCL F.E.
(7 × tCLK) - tSCLfo
-
tSDAvo
76
SDA valid time
After SCL F.E.
-
(7 × tCLK) + tRD
tSCLhigh
After SCL R.E.
-
o
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186
0.7VCC
0.3VCC
0.3VCC
CP3UB17
0.7VCC
SDA
tSDAr
tSDAf
0.7VCC
0.7VCC
0.3VCC
0.3VCC
SCL
tSCLr
tSCLf
te
Note: In the timing tables the parameter name is added with an "o" for output signal timing and "i" for input signal timing.
DS106
Figure 73. ACB Signals (SDA and SCL) Timing
SDA
tDLCs
SCL
Start Condition
ol
e
Stop Condition
tBUF
tCSTRh
bs
tCSTOs
Note: In the timing tables the parameter name is added with an "o" for output signal timing and "i" for input signal timing.
Figure 74.
DS107
ACB Start and Stop Condition Timing
O
Start Condition
SDA
SCL
tCSTRs
tCSTRh
tDHCs
Note: In the timing tables the parameter name is added with an "o" for output signal timing
and "i" for input signal timing.
DS108
Figure 75.
ACB Start Condition Timing
187
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CP3UB17
SDA
tSDAsi
SCL
tSCAvo
tSDAh
tCSLlow
tSCLhigh
Note: In the timing tables the parameter name is added with an "o" for output signal timing
and "i" for input signal timing. unless the parameter already includes the suffix.
DS109
O
bs
ol
e
te
Figure 76. ACB Data Timing
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188
CP3UB17
26.11
USB PORT AC CHARACTERISTICS
Table 60 USB Port Signals
Symbol
Conditionsa
Description
Min
Typ
Max
Units
TR
Rise Time
CL = 50 pF
4
20
ns
TF
Fall Time
CL = 50 pF
4
20
ns
TRFM
Fall/Rise Time Matching (TR/TF)
CL = 50 pF
90
110
%
VCRS
Output Signal Crossover Voltage
CL = 50 pF
1.3
2.0
V
ZDRV
Driver Output Impedance
CL = 50 pF
28
43
ohms
a. Waveforms measured at 10% to 90%.
MULTI-FUNCTION TIMER (MFT) TIMING
te
26.12
Table 61 Multi-Function Timer Input Signals
Symbol
Figur
e
tTAH
77
TA High Time
tTAL
77
TA Low Time
Description
Rising Edge (RE) on CLK
ol
e
CLK
Reference
RE on CLK
TCLK + 5
TCLK + 5
bs
DS169
Multi-Function Timer Input Timing
O
Figure 77.
Max (ns)
tTAL /tTBH
tTAL /tTBL
TA/TB
Min (ns)
189
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CP3UB17
26.13
VERSATILE TIMING UNIT (VTU) TIMING
Table 62 Versatile Timing Unit Input Signals
Symbol
Figur
e
tTIOH
77
TIOx Input High Time
Rising Edge (RE) on CLK
tTIOL
77
TIOx Input Low Time
RE on CLK
Description
Reference
Min (ns)
1.5 × TCLK + 5ns
1.5 × TCLK + 5ns
CLK
tTIOL tTIOH
te
TIOx
DS110
O
bs
ol
e
Figure 78. Versatile Timing Unit Input Timing
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190
Max (ns)
CP3UB17
26.14
EXTERNAL BUS TIMING
Table 63
Symbol Figure
External Bus Signals
Description
Reference
Min (ns)
Max (ns)
External Bus Input Signals
t1
79,
Input Setup Time
81,
D[15:0]
82, 83
Before Rising Edge (RE)
on CLK
8
-
t2
79,
Output Hold Time
81,
D[15:0]
82, 83
After RE on CLK
0
-
-
8
External Bus Output Signals
Output Valid Time
D[15:0]
t3
79, 80
t4
79,
Output Valid Time
80,
A[21:0] (CP3BT10)
81,
A[22:0] (CP3BT13)
82, 83
After RE on CLK
-
8
t5
79,
80,
81,
82, 83
Output Active/Inactive Time
RD
SEL[1:0]
SELIO
After RE on CLK
-
8
t6
79, 80
Output Active/Inactive Time
WR[1:0]
After RE on CLK
-
0.5 Tclk + 8
t7
81
Minimum Inactive Time
RD
At 2.0V
Tclk - 4
-
t8
79
Output Float Time
D[15:0]
After RE on CLK
-
8
t9
79
Minimum Delay Time
From RD Trailing Edge
(TE) to D[15:0] driven
Tclk - 4
-
From RD TE to SELn
Leading Edge (LE)
0
-
From SELx TE to SELy LE
0
-
After RE on CLK
0
-
After RE on CLK
0.5 Tclk - 3
-
t11
t13
te
ol
e
79, 80 Minimum Delay Time
80
Minimum Delay Time
Output Hold Time
A22 (CP3BT13 only)
79,
A[21:0]
80,
D[15:0]
81,
RD
82, 83
SEL[2:0]
SELIO
O
t12
bs
t10
After RE on CLK
79, 80
Output Hold Time
WR[1:0]
191
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CP3UB17
Normal Read
Bus State
T1
Early Write
T2
T1
T2
Normal Read
T3
T1
T2
CLK
t4
t4, t12
t5, t12
t5, t12
A[21:0]
A22 ('13 only)
SELx
t5, t12
t5, t12
SELy
(y ≠ x)
t2
t3
In
Out
t5, t12
t5, t12
RD
t8, t12
te
D[15:0]
t9
t1
In
t6, t13
WR[1:0]
ol
e
t6, t13
O
bs
Figure 79. Early Write Between Normal Read Cycles (No Wait States)
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192
DS124
Bus State
T1
Late Write
T2
T1
CP3UB17
Normal Read
Normal Read
T2
T1
T2
CLK
t4, t12
t4, t12
A[21:0]
A22 ('13 only)
t5, t12
t5, t12
SELx
(y ≠ x)
t11
SELy
(y ≠ x)
t5, t12
t5, t12
D[15:0]
t8, t12
te
t3
In
Out
t10
RD
t9
In
t5, t12
t5, t12
WR[1:0]
ol
e
t6, t13
t6, t13
DS125
O
bs
Figure 80. Late Write Between Normal Read Cycles (No Wait States)
193
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CP3UB17
Normal Read
T1
Bus State
Normal Read
T2
T2B
T1
T2
T2B
CLK
t4, t12
t4, t12
t4
A[21:0]
A22 ('13 only)
t5, t12
t5, t12
SELx
(y ≠ x)
t5, t12
SELy
(y ≠ x)
D[15:0]
t2
t1
In
In
t5, t12
In
ol
e
t5, t12
RD
te
t2
t1
WR[1:0]
In
t7
Consecutive Normal Read Cycles (Burst, No Wait States)
O
bs
Figure 81.
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t5, t12
194
DS126
TW
T2
CP3UB17
T1
Bus State
TH
CLK
t4, t12
t4
A21:0
A22 ('13 only)
t5, t12
t5, t12
SELn,
SELIO
t2
t1
D[15:0]
t5, t12
t5, t12
te
RD
WR[1:0]
ol
e
DS127
O
bs
Figure 82. Normal Read Cycle (Wait Cycle Followed by Hold Cycle)
195
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CP3UB17
Fast Read
Bus State
Tidle
Early Write
T1-2
T1
T2
Fast Read
T3
T1-2
T1
CLK
t4, t12
t4
A[21:0]
A22 ('13 only)
SELx
(y ≠ x)
t5, t12
t5, t12
SELy
(y ≠ x)
t1
D[15:0]
In
Out
RD
t5, t12
ol
e
t5, t12
WR[1:0]
te
t2
Early Write Between Fast Read Cycles
O
bs
Figure 83.
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196
In
DS128
CP3UB17
PG2/RTS/WUI12
PG3/CTS/WUI13
PC1
PC2
PC3
PC4
PC5
PC6
PC7
PG5/SRFS/NMI
TMS
TCK
TDI
GND
IOVCC
ENV2
SEL0
SCL
SDA
TDO
D-
D+
UVCC
UGND
RDY
27.0 Pin Assignments
SEL1
PC0
SEL2
PG1/TXD/WUI11
SELIO
PG0/RXD/WUI10
A21
PI7/TA
A20
PI6/WUI9
PH0/MSK/TIO1
PI5
PH1/MDIDO/TIO2
PI4
PH2/MDODO/TIO3
PI3
IOVCC
PH3/MWCS/TIO4
GND
te
ENV0
PB7
IOVCC
PB6
GND
VCC
PB4
GND
PB3
RESET
PB2
RD
PB1
A19
A18
A17
A16
A15
PH4/SCK/TIO5
PH5/SFS/TIO6
ol
e
WR0
WR1
PB5
CP3UB17
PB0
PI2/SRCLK
PI1
PI0
A0
A1
A2
A3
NC
GND
X1CKI
X1CKO
IOVCC
AGND
AVCC
GND
X2CKO
X2CKI
VCC
A4
A5
A6
A7
A8
A9
ENV1
PH7/SRD/TIO8
PH6/STD/TIO7
A10
A11
bs
A12
A13
A14
1
DS134
O
Figure 84. CP3UB17 in the 100-pin LQFP Package (Top View)
197
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PG2/RTS/WUI12
PG3/CTS/WUI13
PG5/SRFS/NMI
TMS
TCK
TDI
GND
IOVCC
TDO
D-
D+
UVCC
UGND
RDY
CP3UB17
PH0/MSK/TIO1
PG1/TXD/WUI11
PH1/MDIDO/TIO2
PG0/RXD/WUI10
PH2/MDODI/TIO3
PI7/TA
PH3/MWCS/TIO4
PI6/WUI9
ENV0
PI5
CP3UB17
VCC
PI4
PI3
GND
PI2/SRCLK
RESET
PI1
PH4/SCK/TIO5
PI0
te
NC
GND
X1CKI
X1CKO
IOVCC
AGND
AVCC
GND
X2CKO
X2CKI
VCC
ENV1
PH6/STD/TIO7
1
PH7/SRD/TIO8
PH5/SFS/TIO6
DS136
O
bs
ol
e
Figure 85. CP3UB17 in the 48-pin CSP Package (Top View)
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198
Table 64 Revision History (Continued)
Table 64 Revision History
Date
Major Changes From Previous Version
Date
Major Changes From Previous Version
7/16/04
Changed product selection guide table.
10/14/02
Original release of full CP3UB17 datasheet.
8/24/04
Added AC timing specifications for GPIO.
Deleted AC timing section for UART.
10/16/02
Corrections to flash memory programming
sequence and MFT block diagrams.
11/11/02
Numerous minor corrections. Added more
description to AAI section. Added external
reset circuit. Fixed problems with figures.
9/7/04
11/21/02
Converted to new data sheet format.
Removed TB functionality from MFT
section.
In Section 17.2, added sentence that an
external frame sync must be used in
asynchronous mode. In Section 12, in
several places noted that Idle and Halt
modes may only be entered from Active
mode, and the DHC and DMC bits must be
set when entering Idle and Halt modes.
Added usage hints Section 16.8. Removed
Section 20.4.1.
1/13/03
Removed erroneous warning to always
write the IOCFG register with bit 1 set.
Alternate clock source for Advanced Audio
Interface changed to Aux1 clock. Changed
warning about clock glitches to say
Microwire interface must be disabled when
modifying bits in MWCTL1 register.
Changed bit settings which occur in step 2
of the sequence of ACCESS.bus slave
mode address match or global match.
Timer Mode Control Register bit 3 is
reserved and bit 2 is TAEDG. Bit 7 is the
TEN bit (a bit description has been added).
Polarity of all of the bits in the INTCTL
register has been inverted.
5/20/03
Updated DC specifications. Fixed errors in
Microwire bit and pin names. Changed
UART pin names to TXD and RXD. Added
Section 11.6 “Auxiliary Clocks”. Changed
diagram of I/O Port Pin Logic (Section 14).
11/14/03
Defined valid range of SCDV field in
Microwire/SPI module. Noted default
PRSSC register value generates a Slow
Clock frequency slightly higher than 32768
Hz. Clarified usage of CVSTAT register bits
and fields in CVSD/PCM module. Added
usage hint for avoiding ACCESS.bus
module bus error.
te
Added new reset circuits. Added note about
fluctuations in response due to SDI activity.
New back page.
O
bs
ol
e
4/4/05
2/28/04
Changed CVSD Conversion section.
Changed definition of the RESOLUTION
field of the CVSD Control register
(CVCTRL). Changed DC specification for
Vxl2.
3/16/04
Updated DC specifications Iccid and Iccq.
6/23/04
Moved revision history in front of physical
dimensions. Changed back page
disclaimers. Changed absolute maximum
supply voltage to 3.6V. Changed processor
selection guide table.
7/3/04
Changed footnote b in DC specs. Changed
product selection guide table.
199
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CP3UB17
28.0 Revision History
ol
e
te
CP3UB17
29.0 Physical Dimensions (millimeters) unless otherwise noted
100-Pin LQFP Package
O
bs
Figure 86.
Figure 87. 48-Pin CSP Package
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200
CP3UB17
O
bs
ol
e
te
Notes
201
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bs
CP3UB17 Reprogrammable Connectivity Processor with USB Interface
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves
the right at any time without notice to change said circuitry and specifications.
For the most current product information visit us at www.national.com.
O
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