CSD15571Q2

CSD15571Q2 www.ti.com SLPS435 – AUGUST 2013 20-V N-Channel NexFET™ Power MOSFETs Check for Samples: CSD15571Q2 FEATURES 1 • • • • • • • 2 PRODUCT SUMMARY Ultralow Qg and Qgd Low Thermal Resistance Avalanche Rated Pb Free Terminal Plating RoHS Compliant Halogen Free SON 2-mm × 2-mm Plastic Package VDS Drain to Source Voltage 20 V Qg Gate Charge Total (4.5V) 2.5 nC Qgd Gate Charge Gate to Drain RDS(on) Drain to Source On Resistance VGS(th) Threshold Voltage nC 16 mΩ VGS = 10V 12 mΩ 1.45 V ORDERING INFORMATION Device Package Media CSD15571Q2 SON 2-mm × 2-mm Plastic Package 7-Inch Reel APPLICATIONS • • • • 0.66 VGS = 4.5V Optimized for Load Switch Applications Storage, Tablets, and Handheld Devices Optimized for Control FET Applications Point of Load Synchronous Buck Converters Qty Ship 3000 Tape and Reel ABSOLUTE MAXIMUM RATINGS TA = 25°C unless otherwise stated VALUE UNIT VDS Drain to Source Voltage 20 V DESCRIPTION VGS Gate to Source Voltage ±20 V The NexFET™ power MOSFET has been designed to minimize losses in power conversion and load management applications. The SON 2x2 offers excellent thermal performance for the size of the package. ID Continuous Drain Current (Package Limit) 22 A Continuous Drain Current(1) 10 A IDM Pulsed Drain Current, TA = 25°C(2) 52 A PD Power Dissipation(1) 2.5 W TJ, TSTG Operating Junction and Storage Temperature Range –55 to 150 °C EAS Avalanche Energy, single pulse ID = 19A, L = 0.1mH, RG = 25Ω 18 mJ Top View D 1 6 D 5 D 4 S (1) RθJA = 50 on 1in² Cu (2 oz.) on .060" thick FR4 PCB. (2) Pulse duration 10μs, duty cycle ≤2% D D 2 G 3 S P0108-01 RDS(on) vs VGS GATE CHARGE 10 TC = 25°C, I D = 5A TC = 125°C, I D = 5A 28 26 VGS - Gate-to-Source Voltage (V) RDS(on) - On-State Resistance (mΩ) 30 24 22 20 18 16 14 12 10 8 0 2 4 6 8 10 12 14 16 VGS - Gate-to- Source Voltage (V) 18 20 G001 ID = 5A VDS =10V 9 8 7 6 5 4 3 2 1 0 0 0.5 1 1.5 2 2.5 3 3.5 4 Qg - Gate Charge (nC) 4.5 5 5.5 G001 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. NexFET is a trademark of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2013, Texas Instruments Incorporated CSD15571Q2 SLPS435 – AUGUST 2013 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ELECTRICAL CHARACTERISTICS TA = 25°C, unless otherwise specified PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Static Characteristics BVDSS Drain to Source Voltage VGS = 0V, ID = 250μA IDSS Drain to Source Leakage Current VGS = 0V, VDS = 20V IGSS Gate to Source Leakage Current VDS = 0V, VGS = 20V VGS(th) Gate to Source Threshold Voltage VDS = VGS, IDS = 250μA RDS(on) Drain to Source On Resistance gfs Transconductance 20 1.10 V 1 μA 100 nA 1.45 1.90 V VGS = 4.5V, IDS = 5A 16.0 19.2 mΩ VGS = 10V, IDS = 5A 12.0 15.0 mΩ VDS = 16V, IDS = 5A 25 S Dynamic Characteristics CISS Input Capacitance 320 419 pF COSS Output Capacitance CRSS Reverse Transfer Capacitance 184 239 pF 32 42 Rg pF Series Gate Resistance 3.8 7.6 Ω Qg Gate Charge Total (4.5V) 2.5 3.3 nC Qg Gate Charge Total (10V) 5.1 6.7 nC Qgd Gate Charge – Gate to Drain Qgs Qg(th) QOSS Output Charge td(on) Turn On Delay Time tr Rise Time td(off) Turn Off Delay Time tf Fall Time VGS = 0V, VDS = 10V, f = 1MHz VDS = 10V, IDS = 5A 0.66 nC Gate Charge Gate to Source 0.93 nC Gate Charge at Vth 0.52 nC 4.1 nC 4.7 ns 17.2 ns 9.9 ns 4.1 ns VDS = 10V, VGS = 0V VDS = 10V, VGS = 4.5V, IDS = 5A RG = 2Ω Diode Characteristics VSD Diode Forward Voltage Qrr Reverse Recovery Charge trr Reverse Recovery Time IDS = 5A, VGS = 0V 0.82 VDD = 10V, IF = 5A, di/dt = 300A/μs 1 V 10.7 nC 19 ns THERMAL CHARACTERISTICS (TA = 25°C unless otherwise stated) MAX UNIT RθJC Thermal Resistance Junction to Case (1) PARAMETER 4.5 °C/W RθJA Thermal Resistance Junction to Ambient (1) (2) 65 °C/W (1) (2) 2 MIN TYP RθJC is determined with the device mounted on a 1-inch2 (6.45-cm2), 2-oz. (0.071-mm thick) Cu pad on a 1.5-inch × 1.5-inch (3.81-cm × 3.81-cm), 0.06-inch (1.52-mm) thick FR4 PCB. RθJC is specified by design, whereas RθJA is determined by the user’s board design. Device mounted on FR4 material with 1-inch2 (6.45-cm2), 2-oz. (0.071-mm thick) Cu. Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: CSD15571Q2 CSD15571Q2 www.ti.com SLPS435 – AUGUST 2013 GATE GATE Source Source N-Chan N-Chan Max RθJA = 65 when mounted on 1 inch2 (6.45 cm2) of 2-oz. (0.071-mm thick) Cu. Max RθJA = 235 when mounted on minimum pad area of 2-oz. (0.071-mm thick) Cu. DRAIN DRAIN M0164-02 M0164-01 TYPICAL MOSFET CHARACTERISTICS (TA = 25°C unless otherwise stated) Figure 1. Transient Thermal Impedance TEXT ADDED FOR SPACING 30 45 27 IDS - Drain-to-Source Current (A) IDS - Drain-to-Source Current (A) TEXT ADDED FOR SPACING 50 40 35 30 25 20 15 VGS =10V VGS =6V VGS =4.5V 10 5 0 0 0.3 0.6 0.9 1.2 VDS - Drain-to-Source Voltage (V) 1.5 VDS = 5V 24 21 18 15 12 9 TC = 125°C TC = 25°C TC = −55°C 6 3 0 0 G001 Figure 2. Saturation Characteristics 0.5 1 1.5 2 2.5 VGS - Gate-to-Source Voltage (V) 3 Product Folder Links: CSD15571Q2 G001 Figure 3. Transfer Characteristics Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated 3.5 3 CSD15571Q2 SLPS435 – AUGUST 2013 www.ti.com TYPICAL MOSFET CHARACTERISTICS (continued) (TA = 25°C unless otherwise stated) TEXT ADDED FOR SPACING TEXT ADDED FOR SPACING 1000 ID = 5A VDS =10V 9 8 C − Capacitance (pF) VGS - Gate-to-Source Voltage (V) 10 7 6 5 4 3 100 Ciss = Cgd + Cgs Coss = Cds + Cgd Crss = Cgd 2 1 0 0 0.5 1 1.5 2 2.5 3 3.5 4 Qg - Gate Charge (nC) 4.5 5 10 5.5 0 3 6 9 12 15 VDS - Drain-to-Source Voltage (V) G001 Figure 4. Gate Charge TEXT ADDED FOR SPACING TEXT ADDED FOR SPACING ID = 250uA 1.8 RDS(on) - On-State Resistance (mΩ) VGS(th) - Threshold Voltage (V) G001 30 1.7 1.6 1.5 1.4 1.3 1.2 1.1 1 0.9 0.8 −75 −25 25 75 125 TC - Case Temperature (ºC) TC = 25°C, I D = 5A TC = 125°C, I D = 5A 28 26 24 22 20 18 16 14 12 10 8 175 0 2 G001 Figure 6. Threshold Voltage vs. Temperature TEXT ADDED FOR SPACING 18 20 G001 TEXT ADDED FOR SPACING VGS = 4.5V VGS = 10V ID = 5A 1.4 1.2 1 0.8 0.6 −75 6 8 10 12 14 16 VGS - Gate-to- Source Voltage (V) 10 ISD − Source-to-Drain Current (A) 1.6 4 Figure 7. On-State Resistance vs. Gate-to-Source Voltage 1.8 Normalized On-State Resistance 20 Figure 5. Capacitance 1.9 −25 25 75 125 TC - Case Temperature (ºC) 175 TC = 25°C TC = 125°C 1 0.1 0.01 0.001 0.0001 0 0.2 0.4 0.6 0.8 VSD − Source-to-Drain Voltage (V) G001 Figure 8. Normalized On-State Resistance vs. Temperature 4 18 1 G001 Figure 9. Typical Diode Forward Voltage Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: CSD15571Q2 CSD15571Q2 www.ti.com SLPS435 – AUGUST 2013 TYPICAL MOSFET CHARACTERISTICS (continued) (TA = 25°C unless otherwise stated) TEXT ADDED FOR SPACING TEXT ADDED FOR SPACING 100 1ms 10ms 100ms 1s DC IAV - Peak Avalanche Current (A) IDS - Drain-to-Source Current (A) 1000 100 10 1 0.1 Single Pulse Typical RthetaJA =190ºC/W(min Cu) 0.01 0.01 0.1 1 10 VDS - Drain-to-Source Voltage (V) 50 TC = 25ºC TC = 125ºC 10 1 0.1 0.001 0.01 0.1 TAV - Time in Avalanche (mS) G001 Figure 10. Maximum Safe Operating Area 1 G001 Figure 11. Single Pulse Unclamped Inductive Switching TEXT ADDED FOR SPACING IDS - Drain- to- Source Current (A) 27.0 24.0 21.0 18.0 15.0 12.0 9.0 6.0 3.0 0.0 −50 −25 0 25 50 75 100 125 TA - AmbientTemperature (ºC) 150 175 G001 Figure 12. Maximum Drain Current vs. Temperature Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: CSD15571Q2 5 CSD15571Q2 SLPS435 – AUGUST 2013 www.ti.com MECHANICAL DATA Q2 Package Dimensions D2 D K3 K1 K K2 4 1 2 3 4 5 6 3 2 1 K4 E E1 E2 5 E3 6 L Pin 1 Dot Top View Pin 1 ID e b D1 A A1 C Bottom View Front View M0165-01 DIM MILLIMETERS MIN NOM MAX MIN NOM MAX A 0.700 0.750 0.800 0.028 0.030 0.032 A1 0.000 0.050 0.000 b 0.250 0.350 0.010 0.300 C 0.203 TYP D 2.000 TYP D1 0.900 0.950 D2 0.300 TYP E 2.000 TYP E1 0.900 1.000 0.002 0.012 0.080 TYP 1.000 0.036 0.038 0.080 TYP 1.100 0.036 0.040 0.280 TYP 0.0112 TYP 0.470 TYP 0.0188 TYP e 0.650 BSC 0.026 TYP K 0.280 TYP 0.0112 TYP K1 0.350 TYP 0.014 TYP K2 0.200 TYP 0.008 TYP K3 0.200 TYP 0.008 TYP 0.470 TYP 0.200 0.25 0.040 0.012 TYP E3 L 0.014 0.008 TYP E2 K4 6 INCHES 0.044 0.0188 TYP 0.300 0.008 Submit Documentation Feedback 0.010 0.012 Copyright © 2013, Texas Instruments Incorporated Product Folder Links: CSD15571Q2 CSD15571Q2 www.ti.com SLPS435 – AUGUST 2013 Recommended PCB Pattern For recommended circuit layout for PCB designs, see application note SLPA005 – Reducing Ringing Through PCB Layout Techniques. Recommended Stencil Pattern Note: All dimensions are in mm, unless otherwise specified. Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: CSD15571Q2 7 CSD15571Q2 SLPS435 – AUGUST 2013 www.ti.com Q2 Tape and Reel Information 4.00 ±0.10 Ø 1.50 ±0.10 4.00 ±0.10 Ø 1.00 ±0.25 1.00 ±0.05 2.30 ±0.05 10° Max 3.50 ±0.05 8.00 +0.30 –0.10 1.75 ±0.10 2.00 ±0.05 0.254 ±0.02 2.30 ±0.05 10° Max M0168-01 Notes: 1. Measured from centerline of sprocket hole to centerline of pocket 2. Cumulative tolerance of 10 sprocket holes is ±0.20 3. Other material available 4. Typical SR of form tape Max 109 OHM/SQ 5. All dimensions are in mm, unless otherwise specified. 8 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated Product Folder Links: CSD15571Q2 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) CSD15571Q2 ACTIVE WSON DQK 6 3000 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -55 to 150 1551 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of