CSD16323Q3

Sample & Buy Product Folder Support & Community Tools & Software Technical Documents CSD16323Q3 SLPS224C – AUGUST 2009 – REVISED NOVEMBER 2016 CSD16323Q3 N-Channel NexFET™ Power MOSFET 1 Features • • • • • • • • 1 Product Summary Optimized for 5-V Gate Drive Ultra-Low Qg and Qgd Low Thermal Resistance Avalanche Rated Lead-Free Terminal Plating RoHS Compliant Halogen Free SON 3.3-mm × 3.3-mm Plastic Package TA = 25°C • 25 V Qg Gate Charge Total (4.5 V) 6.2 nC Qgd Gate Charge Gate-to-Drain RDS(on) 5.4 VGS = 4.5 V 4.4 VGS = 8 V 3.8 Threshold Voltage 1.1 mΩ V DEVICE MEDIA QTY PACKAGE SHIP CSD16323Q3 13-Inch Reel 2500 CSD16323Q3T 7-Inch Reel 250 SON 3.30-mm × 3.30-mm Plastic Package Tape and Reel (1) For all available packages, see the orderable addendum at the end of the data sheet. Absolute Maximum Ratings TA = 25°C (unless otherwise stated) This 25-V, 3.8-mΩ, 3.3 × 3.3-mm SON NexFET™ power MOSFET has been designed to minimize losses in power conversion and optimized for 5-V gate drive applications. VALUE UNIT VDS Drain-to-Source Voltage 25 V VGS Gate-to-Source Voltage +10 / –8 V ID Top View 8 1 IDM D PD S 2 7 D S 3 6 D D 5 4 D Continuous Drain Current (Package Limit) 60 Continuous Drain Current (Silicon Limited), TC = 25°C 105 Continuous Drain Current(1) 20 Pulsed Drain Current(2) 240 Power Dissipation(1) 2.8 Power Dissipation, TC = 25°C 74 TJ, Tstg Operating Junction, Storage Temperature EAS Avalanche Energy, Single Pulse ID = 50 A, L = 0.1 mH, RG = 25 Ω A A W –55 to 150 °C 125 mJ (1) RθJA = 45°C/W on 1-in2, 2-oz Cu pad on 0.06-in thick FR4 PCB. (2) Max RθJC = 1.7°C/W, pulse duration ≤ 100 μs, duty cycle ≤ 1%. P0095-01 RDS(on) vs VGS Gate Charge 8 30 TC = 25qC, ID = 24 A TC = 125qC, ID = 24 A 25 VGS - Gate-to-Source Voltage (V) RDS(on) - On-State Resistance (m:) nC VGS = 3 V Device Information(1) 3 Description G 1.1 Drain-to-Source On Resistance Vth Point-of-Load Synchronous Buck Converter for Applications in Networking, Telecom and Computing Systems Optimized for Control or Synchronous FET Applications S UNIT Drain-to-Source Voltage 2 Applications • TYPICAL VALUE VDS 20 15 10 5 0 ID = 24 A 7 VDS = 12.5 V 6 5 4 3 2 1 0 0 1 2 3 4 5 6 7 8 VGS - Gate-to-Source Voltage (V) 9 10 D007 0 2 4 6 8 Qg - Gate Charge (nC) 10 12 D004 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. CSD16323Q3 SLPS224C – AUGUST 2009 – REVISED NOVEMBER 2016 www.ti.com Table of Contents 1 2 3 4 5 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Specifications......................................................... 1 1 1 2 3 5.1 Electrical Characteristics........................................... 3 5.2 Thermal Information .................................................. 3 5.3 Typical MOSFET Characteristics.............................. 4 6 Device and Documentation Support.................... 7 6.1 Receiving Notification of Documentation Updates.... 7 6.2 6.3 6.4 6.5 7 Community Resources.............................................. Trademarks ............................................................... Electrostatic Discharge Caution ................................ Glossary .................................................................... 7 7 7 7 Mechanical, Packaging, and Orderable Information ............................................................. 8 7.1 7.2 7.3 7.4 Q3 Package Dimensions .......................................... 8 Recommended PCB Pattern..................................... 9 Recommended Stencil Opening ............................... 9 Q3 Tape and Reel Information................................ 10 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision B (June 2011) to Revision C Page • Changed Description text ....................................................................................................................................................... 1 • Added silicon limited continuous drain current to Absolute Maximum Ratings table ............................................................. 1 • Changed Note 2 in Absolute Maximum Ratings table............................................................................................................ 1 • Changed values in the Thermal Information table to align with standards ............................................................................ 3 • Changed Figure 1 to reflect a transient RθJC curve ................................................................................................................ 4 • Changed Figure 10 to reflect measured data......................................................................................................................... 5 • Added Device and Documentation Support section............................................................................................................... 7 • Changed MECHANICAL DATA section to Mechanical, Packaging, and Orderable Information section .............................. 8 Changes from Revision A (April 2010) to Revision B Page • Replaced the THERMAL CHARACTERISTICS table with the new Thermal Information Table............................................ 4 • Replaced Figure 10 - Maximum Safe Operating Area ........................................................................................................... 5 Changes from Original (August 2009) to Revision A • 2 Page Changed RDS(on) - VGS = 3 V, ID = 24 A MAX value From: 6.5 To: 7.2 ................................................................................... 3 Submit Documentation Feedback Copyright © 2009–2016, Texas Instruments Incorporated Product Folder Links: CSD16323Q3 CSD16323Q3 www.ti.com SLPS224C – AUGUST 2009 – REVISED NOVEMBER 2016 5 Specifications 5.1 Electrical Characteristics TA = 25°C (unless otherwise stated) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT STATIC CHARACTERISTICS BVDSS Drain-to-source voltage VGS = 0 V, ID = 250 μA IDSS Drain-to-source leakage current VGS = 0 V, VDS = 20 V IGSS Gate-to-source leakage current VDS = 0 V, VGS = +10/-8 V VGS(th) Gate-to-source threshold voltage VDS = VGS, ID = 250 μA RDS(on) Drain-to-source on-resistance gfs Transconductance 25 0.9 V 1 μA 100 nA V 1.1 1.4 VGS = 3 V, ID = 24 A 5.4 7.2 VGS = 4.5 V, ID = 24 A 4.4 5.5 VGS = 8 V, ID = 24 A 3.8 4.5 VDS = 12.5 V, ID = 24 A 108 mΩ S DYNAMIC CHARACTERISTICS CISS Input capacitance 1020 1300 pF COSS Output capacitance CRSS Reverse transfer capacitance 740 960 pF 50 65 Rg pF Series gate resistance 1.4 2.8 Ω Qg Gate charge total (4.5 V) 6.2 8.4 nC Qgd Gate charge gate-to-drain 1.1 nC Qgs Gate charge gate-to-source 1.8 nC Qg(th) Gate charge at Vth QOSS Output charge td(on) VGS = 0 V, VDS = 12.5 V, ƒ = 1 MHz VDS = 12.5 V, ID = 24 A 1 nC 14 nC Turnon delay time 5.3 ns tr Rise time 15 ns td(off) Turnoff delay time 13 ns tf Fall time 6.3 ns VDS = 12.5 V, VGS = 0 V VDS = 12.5 V, VGS = 4.5 V, ID = 24 A RG = 2 Ω DIODE CHARACTERISTICS VSD Diode forward voltage IS = 24 A, VGS = 0 V Qrr Reverse recovery charge VDD = 12.5 V, IF = 24 A, di/dt = 300 A/μs 0.85 21 1 nC V trr Reverse recovery time VDD = 12.5 V, IF = 24 A, di/dt = 300 A/μs 16 ns 5.2 Thermal Information TA = 25°C (unless otherwise stated) MAX UNIT RθJC Junction-to-case thermal resistance (1) THERMAL METRIC 1.7 °C/W RθJA Junction-to-ambient thermal resistance (1) (2) 55 °C/W (1) (2) MIN TYP RθJC is determined with the device mounted on a 1-in2 (6.45-cm2), 2-oz (0.071-mm) thick Cu pad on a 1.5-in × 1.5-in (3.81-cm × 3.81cm), 0.06-in (1.52-mm) thick FR4 PCB. RθJC is specified by design, whereas RθJA is determined by the user’s board design. Device mounted on FR4 material with 1-in2 (6.45-cm2), 2-oz (0.071-mm) thick Cu. Submit Documentation Feedback Copyright © 2009–2016, Texas Instruments Incorporated Product Folder Links: CSD16323Q3 3 CSD16323Q3 SLPS224C – AUGUST 2009 – REVISED NOVEMBER 2016 GATE www.ti.com GATE Source Source Max RθJA = 160°C/W when mounted on minimum pad area of 2-oz Cu. Max RθJA = 55°C/W when mounted on 1 in2 of 2-oz Cu. DRAIN DRAIN M0161-02 M0161-01 5.3 Typical MOSFET Characteristics TA = 25°C (unless otherwise stated) Figure 1. Transient Thermal Impedance 4 Submit Documentation Feedback Copyright © 2009–2016, Texas Instruments Incorporated Product Folder Links: CSD16323Q3 CSD16323Q3 www.ti.com SLPS224C – AUGUST 2009 – REVISED NOVEMBER 2016 Typical MOSFET Characteristics (continued) TA = 25°C (unless otherwise stated) 100 90 IDS - Drain-to-Source Current (A) IDS - Drain-to-Source Current (A) 100 80 70 60 50 40 30 20 VGS = 3 V VGS = 4.5 V VGS = 8 V 10 TC = 125° C TC = 25° C TC = -55° C 80 60 40 20 0 0 0 0.1 0.2 0.3 0.4 0.5 VDS - Drain-to-Source Voltage (V) 0.6 1 1.25 1.5 1.75 2 2.25 VGS - Gate-to-Source Voltage (V) D002 2.5 D003 VDS = 5 V Figure 2. Saturation Characteristics Figure 3. Transfer Characteristics 10000 Ciss = Cgd + Cgs Coss = Cds + Cgd Crss = Cgd 7 6 C - Capacitance (pF) VGS - Gate-to-Source Voltage (V) 8 5 4 3 2 1000 100 1 10 0 0 2 4 6 8 Qg - Gate Charge (nC) ID = 24 A 10 0 12 5 D004 VDS = 12.5 V f = 1 MHz Figure 4. Gate Charge 25 D005 VGS = 0 V Figure 5. Capacitance 1.5 30 RDS(on) - On-State Resistance (m:) VGS(th) - Threshold Voltage (V) 10 15 20 VDS - Drain-to-Source Voltage (V) 1.3 1.1 0.9 0.7 0.5 -75 TC = 25qC, ID = 24 A TC = 125qC, ID = 24 A 25 20 15 10 5 0 -50 -25 0 25 50 75 100 TC - Case Temperature (qC) 125 150 175 0 1 2 D006 ID = 250 µA 3 4 5 6 7 8 VGS - Gate-to-Source Voltage (V) 9 10 D007 ID = 24 A Figure 6. Threshold Voltage vs Temperature Figure 7. On Resistance vs Gate Voltage Submit Documentation Feedback Copyright © 2009–2016, Texas Instruments Incorporated Product Folder Links: CSD16323Q3 5 CSD16323Q3 SLPS224C – AUGUST 2009 – REVISED NOVEMBER 2016 www.ti.com Typical MOSFET Characteristics (continued) TA = 25°C (unless otherwise stated) 100 1.5 ISD - Source-to-Drain Current (A) Normalized On-State Resistance 1.6 1.4 1.3 1.2 1.1 1 0.9 0.8 TC = 25° C TC = 125° C 10 1 0.1 0.01 0.001 0.7 0.6 -75 0.0001 -50 -25 0 25 50 75 100 TC - Case Temperature (° C) ID = 24 A 125 150 175 0 0.4 0.6 0.8 VSD - Source-to-Drain Voltage (V) 1 D009 VGS = 4.5 V Figure 8. Normalized On Resistance vs Temperature Figure 9. Typical Diode Forward Voltage 1000 100 IAV - Peak Avalanche Current (A) IDS - Drain-to-Source Current (A) 0.2 D008 100 10 1 100 ms 10 ms 1 ms 0.1 0.1 100 µs 10 µs 1 10 VDS - Drain-to-Source Voltage (V) 100 TC = 25q C TC = 125q C 10 1 0.01 D010 0.1 1 10 TAV - Time in Avalanche (ms) 100 D011 Single pulse, max RθJC = 1.7°C/W Figure 10. Maximum Safe Operating Area Figure 11. Single Pulse Unclamped Inductive Switching IDS - Drain-to-Source Current (A) 70 60 50 40 30 20 10 0 -50 -25 0 25 50 75 100 125 TC - Case Temperature (qC) 150 175 D012 Figure 12. Maximum Drain Current vs Temperature 6 Submit Documentation Feedback Copyright © 2009–2016, Texas Instruments Incorporated Product Folder Links: CSD16323Q3 CSD16323Q3 www.ti.com SLPS224C – AUGUST 2009 – REVISED NOVEMBER 2016 6 Device and Documentation Support 6.1 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. 6.2 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support. 6.3 Trademarks NexFET, E2E are trademarks of Texas Instruments. All other trademarks are the property of their respective owners. 6.4 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 6.5 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. Submit Documentation Feedback Copyright © 2009–2016, Texas Instruments Incorporated Product Folder Links: CSD16323Q3 7 CSD16323Q3 SLPS224C – AUGUST 2009 – REVISED NOVEMBER 2016 www.ti.com 7 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 7.1 Q3 Package Dimensions DIM MILLIMETERS NOM MAX MIN NOM MAX A 0.950 1.000 1.100 0.037 0.039 0.043 A1 0.000 0.000 0.050 0.000 0.000 0.002 b 0.280 0.340 0.400 0.011 0.013 0.016 b1 0.310 NOM 0.012 NOM c 0.150 0.200 0.250 0.006 0.008 0.010 D 3.200 3.300 3.400 0.126 0.130 0.134 D2 1.650 1.750 1.800 0.065 0.069 0.071 d 0.150 0.200 0.250 0.006 0.008 0.010 d1 0.300 0.350 0.400 0.012 0.014 0.016 E 3.200 3.300 3.400 0.126 0.130 0.134 E2 2.350 2.450 2.550 0.093 0.096 0.100 0.550 0.014 e H 0.650 TYP 0.35 K 8 INCHES MIN 0.450 0.026 TYP 0.650 TYP 0.018 0.022 0.026 TYP L 0.35 0.450 0.550 0.014 0.018 0.022 L1 0 — 0 0 — 0 θ 0 — 0 0 — 0 Submit Documentation Feedback Copyright © 2009–2016, Texas Instruments Incorporated Product Folder Links: CSD16323Q3 CSD16323Q3 www.ti.com SLPS224C – AUGUST 2009 – REVISED NOVEMBER 2016 7.2 Recommended PCB Pattern For recommended circuit layout for PCB designs, see Reducing Ringing Through PCB Layout Techniques (SLPA005). 7.3 Recommended Stencil Opening All dimensions are in mm, unless otherwise specified. Submit Documentation Feedback Copyright © 2009–2016, Texas Instruments Incorporated Product Folder Links: CSD16323Q3 9 CSD16323Q3 SLPS224C – AUGUST 2009 – REVISED NOVEMBER 2016 www.ti.com 1.75 ±0.10 7.4 Q3 Tape and Reel Information 2.00 ±0.05 4.00 ±0.10 (See Note 1) 8.00 ±0.10 +0.10 –0.00 3.60 1.30 3.60 5.50 ±0.05 12.00 +0.30 –0.10 Ø 1.50 M0144-01 Notes: 1. 10 sprocket hole pitch cumulative tolerance ±0.2. 2. Camber not to exceed 1 mm in 100 mm, noncumulative over 250 mm. 3. Material: black static dissipative polystyrene. 4. All dimensions are in mm (unless otherwise specified). 5. Thickness: 0.30 ±0.05 mm. 6. MSL1 260°C (IR and Convection) PbF-Reflow Compatible. 10 Submit Documentation Feedback Copyright © 2009–2016, Texas Instruments Incorporated Product Folder Links: CSD16323Q3 PACKAGE OPTION ADDENDUM www.ti.com 29-Mar-2016 PACKAGING INFORMATION Orderable Device Status (1) CSD16323Q3 ACTIVE Package Type Package Pins Package Drawing Qty VSON-CLIP DQG 8 2500 Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Pb-Free (RoHS Exempt) CU SN Level-1-260C-UNLIM Op Temp (°C) Device Marking (4/5) -55 to 150 CSD16323 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. 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