CSD16340Q3T

Sample & Buy Product Folder Support & Community Tools & Software Technical Documents CSD16340Q3 SLPS247E – DECEMBER 2009 – REVISED AUGUST 2014 CSD16340Q3 25-V N-Channel NexFET™ Power MOSFET 1 Features • • • • • • • • • 1 Product Summary Optimized for 5 V Gate Drive Resistance Rated at VGS =2.5 V Ultra-Low Qg and Qgd Low Thermal Resistance Avalanche Rated Pb Free Terminal Plating RoHS Compliant Halogen Free SON 3.3-mm × 3.3-mm Plastic Package TA = 25°C • 25 V Qg Gate Charge Total (4.5 V) 6.5 nC Qgd Gate Charge Gate-to-Drain RDS(on) 8 D S 2 7 D 4 VGS = 4.5 V 4.3 mΩ VGS = 8 V 3.8 mΩ Threshold Voltage 0.85 Device Media Qty Package Ship CSD16340Q3 13-Inch Reel 2500 CSD16340Q3T 7-Inch Reel 250 SON 3.3 x 3.3 mm Plastic Package Tape and Reel VALUE UNIT VDS Drain-to-Source Voltage 25 V VGS Gate-to-Source Voltage +10 / –8 V Continuous Drain Current, TC = 25°C 60 A Continuous Drain Current(1) 21 A IDM Pulsed Drain Current, TA = 25°C(2) 115 A PD Power Dissipation(1) 3 W TJ, Tstg Operating Junction and Storage Temperature Range –55 to 150 °C EAS Avalanche Energy, single pulse ID = 40 A, L = 0.1 mH, RG = 25 Ω 80 mJ ID (1) Typical RθJA = 39°C/W on 1in2 Cu (2 oz.) on 0.060" thick FR4 PCB. (2) Pulse width ≤300 μs, duty cycle ≤2% D 6 V Absolute Maximum Ratings Top View G mΩ (1) For all available packages, see the orderable addendum at the end of the data sheet. This 25 V, 3.8 mΩ, 3.3 × 3.3 mm SON NexFET™ power MOSFET is designed to minimize losses in power conversion and optimized for 5 V gate drive applications. 3 6.1 TA = 25°C 1 nC VGS = 2.5 V . Ordering Information(1) 3 Description S 1.2 Drain-to-Source On-Resistance Vth Point of Load Synchronous Buck Converter for Applications in Networking, Telecom, and Computing Systems Optimized for Control or Synchronous FET Applications S UNIT Drain-to-Source Voltage 2 Applications • VALUE VDS D 5 D P0095-01 RDS(on) vs VGS Gate Charge 8 ID = 20A VDS = 12.5V 7 14 ID = 20A VG − Gate Voltage − V RDS(on) − On-State Resistance − mW 16 12 10 8 TC = 125°C 6 4 TC = 25°C 2 6 5 4 3 2 1 0 0 0 1 2 3 4 5 6 7 8 VGS − Gate to Source Voltage − V 9 10 G006 0 2 4 6 8 Qg − Gate Charge − nC 10 12 G003 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. CSD16340Q3 SLPS247E – DECEMBER 2009 – REVISED AUGUST 2014 www.ti.com Table of Contents 1 2 3 4 5 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Specifications......................................................... 1 1 1 2 3 5.1 Electrical Characteristics........................................... 3 5.2 Thermal Information .................................................. 4 5.3 Typical MOSFET Characteristics.............................. 5 6 Device and Documentation Support.................... 8 6.1 Trademarks ............................................................... 8 6.2 Electrostatic Discharge Caution ................................ 8 6.3 Glossary .................................................................... 8 7 Mechanical, Packaging, and Orderable Information ............................................................. 9 7.1 7.2 7.3 7.4 Q3 Package Dimensions .......................................... 9 Recommended PCB Pattern................................... 10 Recommended Stencil Opening ............................. 10 Q3 Tape and Reel Information................................ 11 4 Revision History Changes from Revision D (November 2011) to Revision E Page • Added 7" reel to Ordering Information ................................................................................................................................... 1 • Updated Mechanical Information ........................................................................................................................................... 9 Changes from Revision C (June 2011) to Revision D Page • Replaced the THERMAL CHARACTERISTICS table with the new Thermal Information Table............................................ 4 • Replaced Figure 10 - Maximum Safe Operating Area ........................................................................................................... 6 Changes from Revision B (September 2010) to Revision C • Deleted the Package Marking Information section ................................................................................................................ 9 Changes from Revision A (January 2010) to Revision B • 2 Page Changed Figure 2, reversed the order of the VGS labels........................................................................................................ 5 Changes from Original (December 2009) to Revision A • Page Page Changed Qg in the PRODUCT SUMMARY table from: 6.8 To 6.5 nC .................................................................................. 1 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated Product Folder Links: CSD16340Q3 CSD16340Q3 www.ti.com SLPS247E – DECEMBER 2009 – REVISED AUGUST 2014 5 Specifications 5.1 Electrical Characteristics (TA = 25°C unless otherwise stated) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT STATIC CHARACTERISTICS BVDSS Drain-to-Source Voltage VGS = 0 V, IDS = 250 μA IDSS Drain-to-Source Leakage Current VGS = 0 V, VDS = 20 V IGSS Gate-to-Source Leakage Current VDS = 0 V, VGS = +10/–8 V VGS(th) Gate-to-Source Threshold Voltage VDS = VGS, IDS = 250 μA RDS(on) Drain-to-Source On-Resistance gƒs Transconductance 25 0.6 V 1 μA 100 nA 0.85 1.1 V VGS = 2.5 V, IDS = 20 A 6.1 7.8 mΩ VGS = 4.5 V, IDS = 20 A 4.3 5.5 mΩ VGS = 8 V, IDS = 20 A 3.8 4.5 mΩ VDS = 15 V, IDS = 20 A 121 S DYNAMIC CHARACTERISTICS CISS Input Capacitance 1050 1350 pF COSS Output Capacitance CRSS Reverse Transfer Capacitance 730 950 pF 53 69 Rg pF Series Gate Resistance 1.5 3 Ω Qg Gate Charge Total (4.5 V) 6.5 9.2 nC Qgd Gate Charge Gate-to-Drain 1.2 nC Qgs Gate Charge Gate-to-Source 2.1 nC Qg(th) Gate Charge at Vth QOSS Output Charge td(on) Turn On Delay Time tr Rise Time td(off) Turn Off Delay Time tƒ Fall Time VGS = 0 V, VDS = 12.5 V, ƒ = 1 MHz VDS = 12.5 V, ID = 20 A VDS = 13 V, VGS = 0 V VDS = 12.5 V, VGS = 4.5 V, ID = 20 A RG = 2 Ω 1 nC 15 nC 4.8 ns 16.1 ns 13.8 ns 5.2 ns DIODE CHARACTERISTICS VSD Diode Forward Voltage Qrr Reverse Recovery Charge trr Reverse Recovery Time IS = 20 A, VGS = 0 V VDD = 13 V, IF = 20 A, di/dt = 300 A/μs 0.8 1 nC 20 ns Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated Product Folder Links: CSD16340Q3 V 14.5 3 CSD16340Q3 SLPS247E – DECEMBER 2009 – REVISED AUGUST 2014 www.ti.com 5.2 Thermal Information CSD16340Q3 THERMAL METRIC (1) (2) Q3 (8 PINS) θJA Junction-to-Ambient Thermal Resistance 42.0 θJCtop Junction-to-Case (top) Thermal Resistance 20.6 θJB Junction-to-Board Thermal Resistance 8.8 ψJT Junction-to-Top Characterization Parameter 0.3 ψJB Junction-to-Board Characterization Parameter 8.7 θJCbot Junction-to-Case (bottom) Thermal Resistance 0.1 (1) (2) °C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. For thermal estimates of this device based on PCB copper area, see the TI PCB Thermal Calculator. GATE GATE Source Source Max RθJA = 162°C/W when mounted on minimum pad area of 2 oz. Cu. Max RθJA = 58°C/W when mounted on 1 inch2 of 2 oz. Cu. DRAIN DRAIN M0161-02 M0161-01 4 UNITS Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated Product Folder Links: CSD16340Q3 CSD16340Q3 www.ti.com SLPS247E – DECEMBER 2009 – REVISED AUGUST 2014 5.3 Typical MOSFET Characteristics (TA = 25°C unless otherwise stated) ZqJA – NormalizedThermal Impedance 10 1 0.5 0.3 0.1 0.1 Duty Cycle = t1/t2 0.05 0.01 P 0.02 0.01 t1 t2 o Typical R qJA = 138 C/W (min Cu) TJ = P x ZqJA x R qJA Single Pulse 0.001 0.001 0.01 0.1 1 10 100 1k tP – Pulse Duration–s G012 50 50 45 45 40 VGS = 2.5V 35 ID − Drain Current − A ID − Drain Current − A Figure 1. Transient Thermal Impedance VGS = 3V 30 VGS = 3.5V 25 VGS = 4.5V 20 VGS = 8V 15 40 35 30 25 TC = 25°C 20 TC = 125°C 15 10 10 5 5 0 0.0 VDS = 5V TC = −55°C 0 0.1 0.2 0.3 0.4 0.5 VDS − Drain to Source Voltage − V 0.6 0.7 G001 Figure 2. Saturation Characteristics 0.9 1.1 1.3 1.5 1.7 1.9 2.1 VGS − Gate to Source Voltage − V Figure 3. Transfer Characteristics Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated Product Folder Links: CSD16340Q3 G002 5 CSD16340Q3 SLPS247E – DECEMBER 2009 – REVISED AUGUST 2014 www.ti.com Typical MOSFET Characteristics (continued) (TA = 25°C unless otherwise stated) 8 2.5 6 C − Capacitance − nF VG − Gate Voltage − V f = 1MHz VGS = 0V ID = 20A VDS = 12.5V 7 5 4 3 2 2.0 CISS = CGD + CGS 1.5 COSS = CGD + CGS 1.0 CRSS = CGD 0.5 1 0 0.0 0 2 4 6 8 10 12 Qg − Gate Charge − nC 0 5 10 G003 Figure 4. Gate Charge RDS(on) − On-State Resistance − mW VGS(th) − Threshold Voltage − V ID = 250mA 0.8 0.6 0.4 0.2 14 ID = 20A 12 10 8 TC = 125°C 6 4 TC = 25°C 2 25 75 125 175 0 G005 2 3 4 5 6 7 8 9 10 G006 Figure 7. On-Resistance vs Gate Voltage 1.6 100 ID = 20A VGS = 4.5V ISD − Source to Drain Current − A Normalized On-State Resistance 1 VGS − Gate to Source Voltage − V Figure 6. Threshold Voltage vs Temperature 1.2 1.0 0.8 0.6 0.4 0.2 10 1 TC = 125°C 0.1 TC = 25°C 0.01 0.001 0.0001 −25 25 75 TC − Case Temperature − °C 125 175 0.0 0.2 0.4 0.6 0.8 VSD − Source to Drain Voltage − V G007 Figure 8. Normalized On Resistance vs Temperature 6 G004 0 −25 TC − Case Temperature − °C 0.0 −75 25 Figure 5. Capacitance 1.0 1.4 20 16 1.2 0.0 −75 15 VDS − Drain to Source Voltage − V 1.0 G008 Figure 9. Typical Diode Forward Voltage Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated Product Folder Links: CSD16340Q3 CSD16340Q3 www.ti.com SLPS247E – DECEMBER 2009 – REVISED AUGUST 2014 Typical MOSFET Characteristics (continued) (TA = 25°C unless otherwise stated) 1k 1ms 10ms 100ms 1s DC I(AV) − Peak Avalanche Current − A IDS - Drain-to-Source Current - A 1000 100 10 Area Limited by Rds(on) 1 0.1 Single Pulse Typical RthetaJA = 138ºC/W(min Cu) 0.01 0.01 0.1 1 10 TC = 25°C TC = 125°C 10 1 0.01 100 VDS - Drain-to-Source Voltage - V 100 0.1 1 10 100 G001 t(AV) − Time in Avalanche − ms G010 Figure 11. Single Pulse Unclamped Inductive Switching Figure 10. Maximum Safe Operating Area 80 ID − Drain Current − A 70 60 50 40 30 20 10 0 −50 −25 0 25 50 75 100 125 TC − Case Temperature − °C 150 175 G011 Figure 12. Maximum Drain Current vs Temperature Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated Product Folder Links: CSD16340Q3 7 CSD16340Q3 SLPS247E – DECEMBER 2009 – REVISED AUGUST 2014 www.ti.com 6 Device and Documentation Support 6.1 Trademarks NexFET is a trademark of Texas Instruments. 6.2 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 6.3 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 8 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated Product Folder Links: CSD16340Q3 CSD16340Q3 www.ti.com SLPS247E – DECEMBER 2009 – REVISED AUGUST 2014 7 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 7.1 Q3 Package Dimensions DIM MILLIMETERS INCHES MIN NOM MAX MIN NOM MAX A 0.950 1.000 1.100 0.037 0.039 0.043 A1 0.000 0.000 0.050 0.000 0.000 0.002 b 0.280 0.340 0.400 0.011 0.013 0.016 b1 0.310 NOM 0.012 NOM c 0.150 0.200 0.250 0.006 0.008 0.010 D 3.200 3.300 3.400 0.126 0.130 0.134 D2 1.650 1.750 1.800 0.065 0.069 0.071 d 0.150 0.200 0.250 0.006 0.008 0.010 d1 0.300 0.350 0.400 0.012 0.014 0.016 E 3.200 3.300 3.400 0.126 0.130 0.134 E2 2.350 2.450 2.550 0.093 0.096 0.100 0.550 0.014 e H 0.650 TYP 0.35 K 0.450 0.026 0.650 TYP 0.018 0.022 0.026 TYP L 0.35 0.450 0.550 0.014 0.018 0.022 L1 0 — 0 0 — 0 θ 0 — 0 0 — 0 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated Product Folder Links: CSD16340Q3 9 CSD16340Q3 SLPS247E – DECEMBER 2009 – REVISED AUGUST 2014 www.ti.com 7.2 Recommended PCB Pattern For recommended circuit layout for PCB designs, see application note SLPA005 – Reducing Ringing Through PCB Layout Techniques. 7.3 Recommended Stencil Opening All dimensions are in mm, unless otherwise specified. 10 Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated Product Folder Links: CSD16340Q3 CSD16340Q3 www.ti.com SLPS247E – DECEMBER 2009 – REVISED AUGUST 2014 1.75 ±0.10 7.4 Q3 Tape and Reel Information 4.00 ±0.10 (See Note 1) Ø 1.50 +0.10 –0.00 3.60 1.30 3.60 5.50 ±0.05 12.00 +0.30 –0.10 8.00 ±0.10 2.00 ±0.05 M0144-01 Notes: 1. 10 sprocket hole pitch cumulative tolerance ±0.2 2. Camber not to exceed 1 mm in 100 mm, noncumulative over 250 mm 3. Material: black static dissipative polystyrene 4. All dimensions are in mm (unless otherwise specified). 5. Thickness: 0.30 ±0.05 mm 6. MSL1 260°C (IR and Convection) PbF-Reflow Compatible Submit Documentation Feedback Copyright © 2009–2014, Texas Instruments Incorporated Product Folder Links: CSD16340Q3 11 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) CSD16340Q3 ACTIVE VSON-CLIP DQG 8 2500 RoHS-Exempt & Green SN Level-1-260C-UNLIM -55 to 150 CSD16340 CSD16340Q3T ACTIVE VSON-CLIP DQG 8 250 RoHS-Exempt & Green SN Level-1-260C-UNLIM -55 to 150 CSD16340 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of