CSD16406Q3

Sample & Buy Product Folder Support & Community Tools & Software Technical Documents CSD16406Q3 SLPS202B – AUGUST 2009 – REVISED DECEMBER 2015 CSD16406Q3 N-Channel NexFET™ Power MOSFET 1 Features • • • • • • • 1 Product Summary Ultra-Low Qg and Qgd Low Thermal Resistance Avalanche Rated Pb Free Terminal Plating RoHS Compliant Halogen Free SON 3.3 mm × 3.3 mm Plastic Package TA = 25°C TYPICAL VALUE Drain-to-Source Voltage 25 V Qg Gate Charge Total (4.5 V) 5.8 nC Qgd Gate Charge Gate to Drain RDS(on) Drain-to-Source OnResistance Vth Threshold Voltage • Point-of-Load Synchronous Buck Converter for Applications in Networking, Telecom, and Computing Systems Optimized for Control or Synchronous FET Applications nC 5.9 mΩ VGS = 10 V 4.2 mΩ 1.8 V DEVICE MEDIA QTY PACKAGE SHIP CSD16406Q3 13-Inch Reel 2500 CSD16406Q3T 13-Inch Reel 250 SON 3.3 x 3.3 mm Plastic Package Tape and Reel (1) For all available packages, see the orderable addendum at the end of the data sheet. Absolute Maximum Ratings 3 Description This 25 V, 4.2 mΩ, 3.3 mm × 3.3 mm SON NexFET™ power MOSFET has been designed to minimize losses in power conversion applications. TA = 25°C VALUE UNIT VDS Drain-to-Source Voltage 25 V VGS Gate-to-Source Voltage +16 / –12 V Top View ID 8 S D 7 S IDM D 6 D 5 D Continuous Drain Current (Package limited) 60 Continuous Drain Current (Silicon limited), TC = 25°C 79 (1) PD S D G 1.5 VGS = 4.5 V . Ordering Information(1) 2 Applications • UNIT VDS P0095-01 Continuous Drain Current 19 Pulsed Drain Current(2) 240 Power Dissipation(1) 2.8 Power Dissipation, TC = 25°C 46 A A W TJ, Tstg Operating Junction Temperature, Storage Temperature –55 to 150 °C EAS Avalanche Energy, single pulse ID = 45 A, L = 0.1 mH, RG = 25 Ω 101 mJ (1) Typical RθJA = 45°C/W on a 1 inch2, 2 oz. Cu pad on a 0.06 inch thick FR4 PCB. (2) Max RθJC = 2.7°C/W, pulse duration ≤100 μs, duty cycle ≤1% RDS(on) vs VGS Gate Charge 12 TC = 25° C, I D = 20 A TC = 125° C, I D = 20 A 12 VGS - Gate-to-Source Voltage (V) RDS(on) - On-State Resistance (m:) 14 10 8 6 4 2 0 ID = 10 A VDS = 12.5 V 10 8 6 4 2 0 0 2 4 6 8 10 12 VGS - Gate-To-Source Voltage (V) 14 16 D007 0 2 4 6 8 10 Qg - Gate Charge (nC) 12 14 D004 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. CSD16406Q3 SLPS202B – AUGUST 2009 – REVISED DECEMBER 2015 www.ti.com Table of Contents 1 2 3 4 5 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Specifications......................................................... 1 1 1 2 3 5.1 Electrical Characteristics........................................... 3 5.2 Thermal Information .................................................. 3 5.3 Typical MOSFET Characteristics.............................. 4 6 Device and Documentation Support.................... 7 6.1 6.2 6.3 6.4 7 Community Resources.............................................. Trademarks ............................................................... Electrostatic Discharge Caution ................................ Glossary .................................................................... 7 7 7 7 Mechanical, Packaging, and Orderable Information ............................................................. 8 7.1 7.2 7.3 7.4 Q3 Package Dimensions .......................................... 8 Recommended PCB Pattern..................................... 9 Recommended Stencil Opening ............................... 9 Q3 Tape and Reel Information................................ 10 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision A (September 2010) to Revision B Page • Added part number to title ..................................................................................................................................................... 1 • Added Silicon Limited ID, TC = 25°C ...................................................................................................................................... 1 • Added Power Dissipation, TC = 25°C .................................................................................................................................... 1 • Updated Typical RθJA ............................................................................................................................................................. 1 • Updated pulsed current conditions ........................................................................................................................................ 1 • Added Device and Documentation Support section .............................................................................................................. 7 • Updated Mechanical, Packaging, and Orderable Information ............................................................................................... 8 Changes from Original (August 2009) to Revision A • 2 Page Deleted the Package Marking Information section................................................................................................................. 8 Submit Documentation Feedback Copyright © 2009–2015, Texas Instruments Incorporated Product Folder Links: CSD16406Q3 CSD16406Q3 www.ti.com SLPS202B – AUGUST 2009 – REVISED DECEMBER 2015 5 Specifications 5.1 Electrical Characteristics (TA = 25°C unless otherwise stated) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT STATIC CHARACTERISTICS BVDSS Drain-to-source voltage VGS = 0 V, ID = 250 μA IDSS Drain-to-source leakage current VGS = 0 V, VDS = 20 V IGSS Gate-to-source leakage current VDS = 0 V, VGS = +16/–12 V VGS(th) Gate-to-source threshold voltage VDS = VGS, ID = 250 μA RDS(on) Drain-to-source on-resistance gfs Transconductance 25 1.4 V 1 μA 100 nA 1.8 2.2 V VGS = 4.5 V, ID = 20 A 5.9 7.4 mΩ VGS = 10 V, ID = 20 A 4.2 5.3 mΩ VDS = 15 V, ID = 20 A 53 S DYNAMIC CHARACTERISTICS CISS Input capacitance COSS Output capacitance CRSS Reverse transfer capacitance Rg Series gate resistance Qg Gate charge total (4.5 V) 5.8 Qgd Gate charge gate to drain Qgs Gate charge gate to source Qg(th) Gate charge at Vth QOSS Output charge td(on) Turn on delay time tr Rise time td(off) Turn off delay time tf Fall time VGS = 0 V, VDS = 12.5 V, ƒ = 1 MHz VDS = 12.5 V, ID = 20 A VDS = 13.6 V, VGS = 0 V VDS = 12.5 V, VGS = 4.5 V ID = 20 A RG = 2 Ω 840 1100 pF 680 950 pF 57 80 pF 1.2 2.4 Ω 8.1 nC 1.5 nC 2.5 nC 1.5 nC 13.9 nC 7.3 ns 12.9 ns 8.5 ns 4.8 ns DIODE CHARACTERISTICS VSD Diode forward voltage IS = 20 A, VGS = 0 V 0.85 1.0 V Qrr Reverse recovery charge VDD = 13.6 V, IF = 20 A, di/dt = 300 A/μs 18 nC trr Reverse recovery time VDD = 13.6 V, IF = 20 A, di/dt = 300 A/μs 22 ns 5.2 Thermal Information (TA = 25°C unless otherwise stated) THERMAL METRIC (1) RθJC Junction-to-case thermal resistance RθJA Junction-to-ambient thermal resistance (1) (2) (1) (2) MIN TYP MAX UNIT 2.7 °C/W 55 °C/W RθJC is determined with the device mounted on a 1 inch2 (6.45 cm2), 2 oz. (0.071 mm thick) Cu pad on a 1.5 inch × 1.5 inch (3.81 cm × 3.81 cm), 0.06 inch (1.52 mm) thick FR4 PCB. RθJC is specified by design, whereas RθJA is determined by the user’s board design. Device mounted on FR4 material with 1 inch2 (6.45 cm2), 2 oz. (0.071 mm thick) Cu. Submit Documentation Feedback Copyright © 2009–2015, Texas Instruments Incorporated Product Folder Links: CSD16406Q3 3 CSD16406Q3 SLPS202B – AUGUST 2009 – REVISED DECEMBER 2015 GATE www.ti.com GATE Source Source Max RθJA = 160°C/W when mounted on minimum pad area of 2 oz. Cu. Max RθJA = 55°C/W when mounted on 1 inch2 of 2 oz. Cu. DRAIN DRAIN M0161-02 M0161-01 5.3 Typical MOSFET Characteristics (TA = 25°C unless otherwise stated) Figure 1. Transient Thermal Impedance 4 Submit Documentation Feedback Copyright © 2009–2015, Texas Instruments Incorporated Product Folder Links: CSD16406Q3 CSD16406Q3 www.ti.com SLPS202B – AUGUST 2009 – REVISED DECEMBER 2015 Typical MOSFET Characteristics (continued) (TA = 25°C unless otherwise stated) 50 VGS = 4.5 V VGS = 5 V VGS = 10 V 80 IDS - Drain-To-Source Current (A) IDS - Drain-to-Source Current (A) 100 60 40 20 0 0 0.2 0.4 0.6 0.8 1 VDS - Drain-to-Source Voltage (V) 1.2 TC = 125° C TC = 25° C TC = -55° C 40 30 20 10 0 1.5 1.4 2 D002 2.5 3 3.5 VGS - Gate-To-Source Voltage (V) 4 D003 VDS = 5 V Figure 2. Saturation Characteristics Figure 3. Transfer Characteristics 10000 10 C - Capacitance (pF) VGS - Gate-to-Source Voltage (V) 12 8 6 4 1000 100 10 Ciss = Cgd + Cgs Coss = Cds + Cgd Crss = Cgd 2 1 0 0 2 4 6 8 10 Qg - Gate Charge (nC) ID = 20 A 12 0 14 5 D004 D005 Figure 5. Capacitance 14 RDS(on) - On-State Resistance (m:) 2.2 VGS(th) - Threshold Voltage (V) 25 VDS = 12.5 V Figure 4. Gate Charge 2 1.8 1.6 1.4 1.2 1 -75 10 15 20 VDS - Drain-to-Source Voltage (V) TC = 25° C, I D = 20 A TC = 125° C, I D = 20 A 12 10 8 6 4 2 0 -50 -25 0 25 50 75 100 TC - Case Temperature (° C) 125 150 175 0 2 D006 4 6 8 10 12 VGS - Gate-To-Source Voltage (V) 14 16 D007 ID = 250 µA Figure 6. Threshold Voltage vs Temperature Figure 7. On Resistance vs Gate Voltage Submit Documentation Feedback Copyright © 2009–2015, Texas Instruments Incorporated Product Folder Links: CSD16406Q3 5 CSD16406Q3 SLPS202B – AUGUST 2009 – REVISED DECEMBER 2015 www.ti.com Typical MOSFET Characteristics (continued) (TA = 25°C unless otherwise stated) 100 1.4 ISD - Source-to-Drain Current (A) Normalized On-State Resistance 1.5 1.3 1.2 1.1 1 0.9 0.8 0.7 -75 TC = 25° C TC = 125° C 10 1 0.1 0.01 0.001 0.0001 -50 -25 0 25 50 75 100 TC - Case Temperature (° C) ID = 20 A 125 150 175 0 1 D009 Figure 9. Typical Diode Forward Voltage 1000 100 100 10 1 DC 10 ms 1 ms TC = 125° C TC = 25° C IDS - Drain-to-Source Current (A) IDS - Drain-to-Source Current (A) 0.4 0.6 0.8 VSD - Source-to-Drain Voltage (V) VGS = 10 V Figure 8. Normalized On-Resistance vs Temperature 0.1 0.1 0.2 D008 100 µs 10 µs 1 10 VDS - Drain-to-Source Voltage (V) 100 10 0.01 D010 0.1 VGS - Gate-to-Source Voltage (V) 1 D011 Single Pulse, Max RθJC = 2.7°C/W Figure 10. Maximum Safe Operating Area Figure 11. Single Pulse Unclamped Inductive Switching IDS - Drain-to-Source Current (A) 70 60 50 40 30 20 10 0 -50 -25 0 25 50 75 100 125 TC - Case Temperature (° C) 150 175 D012 Figure 12. Maximum Drain Current vs Temperature 6 Submit Documentation Feedback Copyright © 2009–2015, Texas Instruments Incorporated Product Folder Links: CSD16406Q3 CSD16406Q3 www.ti.com SLPS202B – AUGUST 2009 – REVISED DECEMBER 2015 6 Device and Documentation Support 6.1 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support. 6.2 Trademarks NexFET, E2E are trademarks of Texas Instruments. All other trademarks are the property of their respective owners. 6.3 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 6.4 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. Submit Documentation Feedback Copyright © 2009–2015, Texas Instruments Incorporated Product Folder Links: CSD16406Q3 7 CSD16406Q3 SLPS202B – AUGUST 2009 – REVISED DECEMBER 2015 www.ti.com 7 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 7.1 Q3 Package Dimensions DIM MILLIMETERS NOM MAX MIN NOM MAX A 0.950 1.000 1.100 0.037 0.039 0.043 A1 0.000 0.000 0.050 0.000 0.000 0.002 b 0.280 0.340 0.400 0.011 0.013 0.016 b1 0.310 NOM 0.012 NOM c 0.150 0.200 0.250 0.006 0.008 0.010 D 3.200 3.300 3.400 0.126 0.130 0.134 D2 1.650 1.750 1.800 0.065 0.069 0.071 d 0.150 0.200 0.250 0.006 0.008 0.010 d1 0.300 0.350 0.400 0.012 0.014 0.016 E 3.200 3.300 3.400 0.126 0.130 0.134 E2 2.350 2.450 2.550 0.093 0.096 0.100 0.550 0.014 e H 0.650 TYP 0.35 K 8 INCHES MIN 0.450 0.026 TYP 0.650 TYP 0.018 0.022 0.026 TYP L 0.35 0.450 0.550 0.014 0.018 0.022 L1 0 — 0 0 — 0 θ 0 — 0 0 — 0 Submit Documentation Feedback Copyright © 2009–2015, Texas Instruments Incorporated Product Folder Links: CSD16406Q3 CSD16406Q3 www.ti.com SLPS202B – AUGUST 2009 – REVISED DECEMBER 2015 7.2 Recommended PCB Pattern For recommended circuit layout for PCB designs, see application note SLPA005 – Reducing Ringing Through PCB Layout Techniques. 7.3 Recommended Stencil Opening All dimensions are in mm, unless otherwise specified. Submit Documentation Feedback Copyright © 2009–2015, Texas Instruments Incorporated Product Folder Links: CSD16406Q3 9 CSD16406Q3 SLPS202B – AUGUST 2009 – REVISED DECEMBER 2015 www.ti.com 1.75 ±0.10 7.4 Q3 Tape and Reel Information 2.00 ±0.05 4.00 ±0.10 (See Note 1) 8.00 ±0.10 +0.10 –0.00 3.60 1.30 3.60 5.50 ±0.05 12.00 +0.30 –0.10 Ø 1.50 M0144-01 Notes: 1. 10 sprocket hole pitch cumulative tolerance ±0.2 2. Camber not to exceed 1 mm in 100 mm, noncumulative over 250 mm 3. Material: black static dissipative polystyrene 4. All dimensions are in mm (unless otherwise specified). 5. Thickness: 0.30 ±0.05 mm 6. MSL1 260°C (IR and Convection) PbF-Reflow Compatible 10 Submit Documentation Feedback Copyright © 2009–2015, Texas Instruments Incorporated Product Folder Links: CSD16406Q3 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) CSD16406Q3 ACTIVE VSON-CLIP DQG 8 2500 RoHS-Exempt & Green SN Level-1-260C-UNLIM -55 to 150 CSD16406 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of