CSD16412Q5A

CSD16412Q5A SLPS207A – AUGUST 2009 – REVISED SEPTEMBER 2010 www.ti.com N-Channel NexFET™ Power MOSFETs Check for Samples: CSD16412Q5A FEATURES 1 • • • • • • • 2 PRODUCT SUMMARY Ultra Low Qg and Qgd Low Thermal Resistance Avalanche Rated Pb Free Terminal Plating RoHS Compliant Halogen Free SON 5mm x 6mm Plastic Package VDS Drain to Source Voltage 25 V Qg Gate Charge Total (4.5V) 2.9 nC Qgd Gate Charge Gate to Drain RDS(on) Drain to Source On Resistance VGS(th) Threshold Voltage • DESCRIPTION The NexFET™ power MOSFET has been designed to minimize losses in power conversion applications. Top View S 1 8 D S 2 7 D 3 G 4 mΩ VGS = 10V 9 mΩ 2 V ORDERING INFORMATION Point-of-Load Synchronous Buck Converter for Applications in Networking, Telecom and Computing Systems Optimized for Control FET Applications S nC 13 Device Package Media CSD16412Q5A SON 5 × 6 Plastic Package 13-inch reel APPLICATIONS • 0.7 VGS = 4.5V 6 D 5 D Qty Ship 2500 Tape and Reel ABSOLUTE MAXIMUM RATINGS TA = 25°C unless otherwise stated VALUE UNIT VDS Drain to Source Voltage 25 V VGS Gate to Source Voltage +16 / –12 V Continuous Drain Current, TC = 25°C 52 A Continuous Drain Current(1) 14 A IDM Pulsed Drain Current, TA = 25°C(2) 91 A PD Power Dissipation(1) 3 W TJ, TSTG Operating Junction and Storage Temperature Range –55 to 150 °C EAS Avalanche Energy, single pulse ID = 17A, L = 0.1mH, RG = 25Ω 14 mJ ID (1) RθJA = 42°C/W on 1in2 Cu (2 oz) on 0.060" thick FR4 PCB. (2) Pulse width ≤300μs, duty cycle ≤2% D P0093-01 RDS(ON) vs VGS Gate Charge 12 ID = 10A VDS = 12.5V ID = 10A 45 10 40 VG − Gate Voltage − V RDS(on) − On-State Resistance − mΩ 50 35 30 TC = 125°C 25 20 15 10 8 6 4 2 5 TC = 25°C 0 0 0 2 4 6 8 VGS − Gate to Source Voltage − V 10 12 G006 0 1 2 3 4 5 6 7 Qg − Gate Charge − nC G003 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. NexFET is a trademark of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2009–2010, Texas Instruments Incorporated CSD16412Q5A SLPS207A – AUGUST 2009 – REVISED SEPTEMBER 2010 www.ti.com ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise stated) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Static Characteristics BVDSS Drain to Source Voltage VGS = 0V, ID = 250μA IDSS Drain to Source Leakage Current VGS = 0V, VDS = 20V IGSS Gate to Source Leakage Current VDS = 0V, VGS = +16/-12V VGS(th) Gate to Source Threshold Voltage VDS = VGS, ID = 250μA RDS(on) Drain to Source On Resistance gfs Transconductance 25 1.7 V 1 μA 100 nA 2.0 2.3 V VGS = 4.5V, ID = 10A 13 16 mΩ VGS = 10V, ID = 10A 9 11 mΩ VDS = 15V, ID = 10A 33 S Dynamic Characteristics CISS Input Capacitance 410 530 pF COSS Output Capacitance CRSS Reverse Transfer Capacitance 350 450 pF 32 42 Rg pF Series Gate Resistance 0.7 1.4 Ω Qg Gate Charge Total (4.5V) 2.9 3.8 nC Qgd Gate Charge Gate to Drain Qgs Gate Charge Gate to Source Qg(th) Gate Charge at Vth QOSS Output Charge td(on) Turn On Delay Time tr Rise Time 7.1 ns td(off) Turn Off Delay Time 5.7 ns tf Fall Time 3.3 ns VGS = 0V, VDS = 12.5V, f = 1MHz VDS = 12.5V, ID = 10A VDS = 13V, VGS = 0V VDS = 12.5V, VGS = 4.5V, ID = 10A RG = 2Ω 0.7 nC 1.4 nC 0.9 nC 7 nC 5.5 ns Diode Characteristics VSD Diode Forward Voltage IS = 10A, VGS = 0V 0.85 1.0 V Qrr Reverse Recovery Charge Vdd= 13V, IF = 10A, di/dt = 300A/μs 12 nC trr Reverse Recovery Time Vdd= 13V, IF = 10A, di/dt = 300A/μs 16 ns THERMAL CHARACTERISTICS (TA = 25°C unless otherwise stated) PARAMETER R θJC Thermal Resistance Junction to Case (1) R θJA Thermal Resistance Junction to Ambient (1) (1) (2) 2 (2) MIN TYP MAX UNIT 3.7 °C/W 53 °C/W R θJC is determined with the device mounted on a 1 inch square 2 oz. Cu pad on a 1.5 × 1.5 in 0.060 inch thick FR4 board. R θJC is specified by design while R θJA is determined by the user’s board design. Device mounted on FR4 Material with 1 inch2 of 2 oz. Cu. Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated Product Folder Link(s): CSD16412Q5A CSD16412Q5A SLPS207A – AUGUST 2009 – REVISED SEPTEMBER 2010 www.ti.com GATE GATE Source Source N-Chan 5x6 QFN TTA MIN Rev3 N-Chan 5x6 QFN TTA MAX Rev3 Max RθJA = 53°C/W when mounted on 1inch2 of 2 oz. Cu. Max RθJA = 119°C/W when mounted on minimum pad area of 2 oz. Cu. DRAIN DRAIN M0137-02 M0137-01 TYPICAL MOSFET CHARACTERISTICS (TA = 25°C unless otherwise stated) ZqJA – Normalized Thermal Impedance 10 1 0.5 0.3 Duty Cycle = t1/t2 0.1 0.1 0.05 P t1 0.02 0.01 t2 0.01 RqJA = 95°C/W (min Cu) TJ = P ´ ZqJA ´ RqJA Single Pulse 0.001 0.0001 0.001 0.01 0.1 1 10 100 1k tp – Pulse Duration – s G012 Figure 1. Transient Thermal Impedance Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated Product Folder Link(s): CSD16412Q5A 3 CSD16412Q5A SLPS207A – AUGUST 2009 – REVISED SEPTEMBER 2010 www.ti.com TYPICAL MOSFET CHARACTERISTICS (continued) (TA = 25°C unless otherwise stated) TEXT ADDED FOR SPACING TEXT ADDED FOR SPACING TEXT ADDED FOR SPACING TEXT ADDED FOR SPACING 30 30 25 25 VGS = 10V VGS = 3.5V VGS = 4.5V 20 ID − Drain Current − A ID − Drain Current − A VDS = 5V VGS = 4V 15 10 VGS = 3V 5 0.5 1.0 1.5 2.0 2.5 TC = 25°C 10 TC = −55°C 2.5 3.0 3.5 4.0 VGS − Gate to Source Voltage − V G001 4.5 G002 Figure 2. Saturation Characteristics Figure 3. Transfer Characteristics TEXT ADDED FOR SPACING TEXT ADDED FOR SPACING TEXT ADDED FOR SPACING TEXT ADDED FOR SPACING 12 1200 ID = 10A VDS = 12.5V f = 1MHz VGS = 0V 1000 C − Capacitance − pF 10 VG − Gate Voltage − V 15 0 2.0 3.0 VDS − Drain to Source Voltage − V 8 6 4 2 800 COSS = CDS + CGD CISS = CGD + CGS 600 400 CRSS = CGD 200 0 0 0 1 2 3 4 5 6 7 Qg − Gate Charge − nC 0 10 15 20 G003 25 G004 Figure 4. Gate Charge Figure 5. Capacitance TEXT ADDED FOR SPACING TEXT ADDED FOR SPACING TEXT ADDED FOR SPACING TEXT ADDED FOR SPACING RDS(on) − On-State Resistance − mΩ 50 ID = 250µA 2.50 2.25 2.00 1.75 1.50 1.25 1.00 0.75 −75 5 VDS − Drain to Source Voltage − V 2.75 VGS(th) − Threshold Voltage − V TC = 125°C 5 0 0.0 ID = 10A 45 40 35 30 TC = 125°C 25 20 15 10 5 TC = 25°C 0 −25 25 75 125 175 TC − Case Temperature − °C 0 2 4 6 8 10 VGS − Gate to Source Voltage − V G005 Figure 6. Threshold Voltage vs. Temperature 4 20 12 G006 Figure 7. On Resistance vs. Gate Voltage Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated Product Folder Link(s): CSD16412Q5A CSD16412Q5A SLPS207A – AUGUST 2009 – REVISED SEPTEMBER 2010 www.ti.com TYPICAL MOSFET CHARACTERISTICS (continued) (TA = 25°C unless otherwise stated) TEXT ADDED FOR SPACING TEXT ADDED FOR SPACING TEXT ADDED FOR SPACING TEXT ADDED FOR SPACING 100 1.6 ID = 17A VGS = 10V ISD − Source to Drain Current − A Normalized On-State Resistance 1.8 1.4 1.2 1.0 0.8 0.6 0.4 −75 −25 25 75 125 TC = 25°C 0.01 0.001 0.2 0.4 0.6 0.8 1.0 Figure 8. On Resistance vs. Temperature Figure 9. Typical Diode Forward Voltage TEXT ADDED FOR SPACING TEXT ADDED FOR SPACING TEXT ADDED FOR SPACING TEXT ADDED FOR SPACING 1.2 G008 100 I(AV) − Peak Avalanche Current − A ID − Drain Current − A 0.1 VSD − Source to Drain Voltage − V 100 10 1ms 10ms 100ms Area Limited by RDS(on) 1s 0.1 0.01 0.01 TC = 125°C G007 1k 1 1 0.0001 0.0 175 TC − Case Temperature − °C 10 Single Pulse RqJA = 95°C/W (min Cu) 0.1 DC 1 10 TC = 25°C 10 TC = 125°C 1 0.01 100 VDS − Drain To Source Voltage − V 0.1 1 10 100 t(AV) − Time in Avalanche − ms G009 Figure 10. Maximum Safe Operating Area G010 Figure 11. Single Pulse Unclamped Inductive Switching TEXT ADDED FOR SPACING TEXT ADDED FOR SPACING 70 ID − Drain Current − A 60 50 40 30 20 10 0 −50 −25 0 25 50 75 100 TC − Case Temperature − °C 125 150 G011 Figure 12. Maximum Drain Current vs. Temperature Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated Product Folder Link(s): CSD16412Q5A 5 CSD16412Q5A SLPS207A – AUGUST 2009 – REVISED SEPTEMBER 2010 www.ti.com MECHANICAL DATA Q5A Package Dimensions L E2 H K 7 D2 3 4 b 4 5 5 6 3 6 e D1 7 2 2 8 8 1 1 q L1 Top View Bottom View Side View c A q E1 E Front View M0135-01 DIM MILLIMETERS MIN NOM MAX A 0.90 1.00 1.10 b 0.33 0.41 0.51 c 0.20 0.25 0.30 D1 4.80 4.90 5.00 D2 3.61 3.81 3.96 E 5.90 6.00 6.10 E1 5.70 5.75 5.80 E2 3.38 3.58 3.78 e 6 1.27 BSC H 0.41 0.51 0.61 K 1.10 L L1 0.51 0.61 0.71 0.06 0.13 θ 0° 0.20 Submit Documentation Feedback 12° Copyright © 2009–2010, Texas Instruments Incorporated Product Folder Link(s): CSD16412Q5A CSD16412Q5A SLPS207A – AUGUST 2009 – REVISED SEPTEMBER 2010 www.ti.com Figure 13. Recommended PCB Pattern DIM F1 F7 F3 8 1 F2 F11 F5 F9 5 4 F6 MILLIMETERS INCHES MIN MAX MIN MAX F1 6.205 6.305 0.244 0.248 F2 4.46 4.56 0.176 0.18 F3 4.46 4.56 0.176 0.18 F4 0.65 0.7 0.026 0.028 F5 0.62 0.67 0.024 0.026 F6 0.63 0.68 0.025 0.027 F7 0.7 0.8 0.028 0.031 F8 0.65 0.7 0.026 0.028 F9 0.62 0.67 0.024 0.026 F10 4.9 5 0.193 0.197 F11 4.46 4.56 0.176 0.18 F8 F4 F10 M0139-01 For recommended circuit layout for PCB designs, see application note SLPA005 – Reducing Ringing Through PCB Layout Techniques. K0 4.00 ±0.10 (See Note 1) 0.30 ±0.05 2.00 ±0.05 +0.10 –0.00 12.00 ±0.30 Ø 1.50 1.75 ±0.10 Q5A Tape and Reel Information 5.50 ±0.05 B0 R 0.30 MAX A0 8.00 ±0.10 Ø 1.50 MIN A0 = 6.50 ±0.10 B0 = 5.30 ±0.10 K0 = 1.40 ±0.10 R 0.30 TYP M0138-01 Notes: 1. 10 sprocket hole pitch cumulative tolerance ±0.2 2. Camber not to exceed 1mm IN 100mm, noncumulative over 250mm 3. Material:black static dissipative polystyrene 4. All dimensions are in mm (unless otherwise specified) 5. A0 and B0 measured on a plane 0.3mm above the bottom of the pocket 6. MSL1 260°C (IR and Convection) PbF Reflow Compatible Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated Product Folder Link(s): CSD16412Q5A 7 CSD16412Q5A SLPS207A – AUGUST 2009 – REVISED SEPTEMBER 2010 www.ti.com REVISION HISTORY Changes from Original (August 2009) to Revision A • 8 Page Deleted the Package Marking Information section ............................................................................................................... 7 Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated Product Folder Link(s): CSD16412Q5A PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) CSD16412Q5A ACTIVE VSONP DQJ 8 2500 RoHS-Exempt & Green SN Level-1-260C-UNLIM -55 to 150 CSD16412 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of