CSD16415Q5

Sample & Buy Product Folder Support & Community Tools & Software Technical Documents Reference Design CSD16415Q5 SLPS259A – DECEMBER 2011 – REVISED SEPTEMBER 2015 CSD16415Q5 25-V N-Channel NexFET™ Power MOSFET 1 Features • • • • • • • 1 Added text for spacing Ultralow Qg and Qgd Very Low On-Resistance Low Thermal Resistance Avalanche Rated Pb-Free Terminal Plating RoHS Compliant Halogen-Free Product Summary TA = 25°C VALUE Drain-to-Source Voltage 25 V Qg Gate Charge, Total (4.5 V) 21 nC Qgd Gate Charge, Gate-to-Drain RDS(on) Drain-to-Source On Resistance VGS(th) Threshold Voltage 2 Applications • • This 25 V, 1.3 mΩ, 5 x 6 mm SON NexFET™ power MOSFET has been designed to minimize losses in power conversion applications. Top View 8 1 D 0.99 mΩ 1.5 V MEDIA QTY SHIP CSD16415Q5 SON 5-mm × 6-mm Plastic Package 13-inch Reel 2500 Tape and Reel 7 2 Absolute Maximum Ratings TA = 25°C VALUE UNIT VDS Drain-to-Source Voltage 25 V VGS Gate-to-Source Voltage –12 to 16 V D PD D 6 3 5 4 D Continuous Drain Current (Package Limited) 100 Continuous Drain Current (Silicon Limited), TC = 25°C (1) 261 Continuous Drain Current (1) 38 Pulsed Drain Current, TA = 25°C (2) 200 Power dissipation (1) 3.2 Power Dissipation, , TC = 25°C 156 TJ, Tstg Operating Junction and Storage Temperature EAS Avalanche Energy, Single-Pulse ID = 100 A, L = 0.1 mH, RG = 25 Ω P0094-01 Added text for spacing (1) Added text for spacing (2) A A W –55 to 150 °C 500 mJ RθJA = 40°C/W on 1 in2 (6.45 cm2) Cu [2 oz. (0.071 mm thick)] on 0.060 inch (1.52 mm) thick FR4 PCB. Max RθJC = 0.8°C/W, pulse duration ≤100 μs, duty cycle ≤1% RDS(ON) vs VGS Gate Charge 12 5 TC = 25° C, I D = 40 A TC = 125° C, I D = 40 A 4.5 VGS - Gate-to-Source Voltage (V) RDS(on) - On-State Resistance (m:) VGS = 10 V PACKAGE ID D G mΩ DEVICE IDM S nC 1.5 (1) For all available packages, see the orderable addendum at the end of the data sheet. 3 Description S 5.2 VGS = 4.5 V Device Information(1) Point-of-Load Synchronous Buck Converter for Applications in Networking, Telecom, and Computing Systems Optimized for Synchronous FET Applications S UNIT VDS 4 3.5 3 2.5 2 1.5 1 0.5 0 0 1 2 3 4 5 6 7 8 VGS - Gate-to-Source Voltage (V) 9 10 D007 ID = 40 A VDS = 12.5 V 10 8 6 4 2 0 0 10 20 30 40 Qg - Gate Charge (nC) 50 60 D004 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. CSD16415Q5 SLPS259A – DECEMBER 2011 – REVISED SEPTEMBER 2015 www.ti.com Table of Contents 1 2 3 4 5 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Specifications......................................................... 1 1 1 2 3 5.1 Electrical Characteristics........................................... 3 5.2 Thermal Information .................................................. 3 5.3 Typical MOSFET Characteristics.............................. 4 6 Device and Documentation Support.................... 7 6.1 6.2 6.3 6.4 7 Community Resources.............................................. Trademarks ............................................................... Electrostatic Discharge Caution ................................ Glossary .................................................................... 7 7 7 7 Mechanical, Packaging, and Orderable Information ............................................................. 8 7.1 Q5 Package Dimensions .......................................... 8 7.2 Recommended PCB Pattern..................................... 9 7.3 Q5 Tape and Reel Information................................ 10 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Original (August 2014) to Revision A Page • Added part number to title ..................................................................................................................................................... 1 • Enhanced Description............................................................................................................................................................. 1 • Added Device and Documentation Support section and Mechanical, Packaging, and Orderable Information section ......... 1 • Updated pulsed current ......................................................................................................................................................... 1 • Updated Figure 1 to a normalized RθJC curve ........................................................................................................................ 4 • Updated the SOA in Figure 10 ............................................................................................................................................... 5 • Deleted Package Marking Information section at the end of the data sheet........................................................................ 10 2 Submit Documentation Feedback Copyright © 2011–2015, Texas Instruments Incorporated Product Folder Links: CSD16415Q5 CSD16415Q5 www.ti.com SLPS259A – DECEMBER 2011 – REVISED SEPTEMBER 2015 5 Specifications 5.1 Electrical Characteristics TA = 25°C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT STATIC CHARACTERISTICS BVDSS Drain-to-Source Voltage VGS = 0 V, ID = 250 μA IDSS Drain-to-Source Leakage Current VGS = 0 V, VDS = 20 V IGSS Gate-to-Source Leakage Current VDS = 0 V, VGS = –12 V to 16 V VGS(th) Gate-to-Source Threshold Voltage VDS = VGS, ID = 250 μA RDS(on) Drain-to-Source On Resistance gfs Transconductance 25 1.2 V 1 μA 100 nA 1.5 1.9 V VGS = 4.5 V, ID = 40 A 1.5 1.8 mΩ VGS = 10 V, ID = 40 A 0.99 1.15 mΩ VDS = 15 V, ID = 40 A 168 S DYNAMIC CHARACTERISTICS CISS Input Capacitance COSS Output Capacitance CRSS Reverse Transfer Capacitance 175 230 Rg Series Gate Resistance 1.2 2.4 Ω Qg Gate Charge Total (4.5 V) 21 29 nC Qgd Gate Charge, Gate-to-Drain Qgs Gate Charge, Gate-to-Source Qg(th) Gate Charge at Vth QOSS Output Charge td(on) Turnon Delay Time tr Rise Time td(off) Turn Off Delay Time tf Fall Time VGS = 0 V, VDS = 12.5 V, ƒ = 1 MHz VDS = 12.5 V, ID = 40 A VDS = 15 V, VGS = 0 V VDS = 12.5 V, VGS = 4.5 V, ID = 40 A RG = 2 Ω 3150 4100 pF 2530 3300 pF pF 5.2 nC 8.3 nC 4.8 nC 55 nC 16.6 ns 30 ns 20 ns 12.7 ns DIODE CHARACTERISTICS VSD Diode Forward Voltage IS = 40 A, VGS = 0 V 0.85 1 V Qrr Reverse Recovery Charge VDD = 15 V, IF = 40 A, di/dt = 300 A/μs 72 nC trr Reverse Tecovery Time VDD = 15 V, IF = 40 A, di/dt = 300 A/μs 45 ns 5.2 Thermal Information TA = 25°C (unless otherwise noted) THERMAL METRIC MIN RθJC Thermal resistance, junction-to-case (1) RθJA Thermal resistance, junction-to-ambient (1) (1) (2) (2) TYP MAX UNIT 0.8 °C/W 50 °C/W RθJC is determined with the device mounted on a 1 inch (2.54 cm) square, 2 oz. (0.071 mm thick) Cu pad on a 1.5 inch × 1.5 inch (3.81 cm × 3.81 cm), 0.060 inch (1.52 mm) thick FR4 board. RθJC is specified by design, whereas RθJA is determined by the user’s board design. Device mounted on FR4 material with 1 inch2 (6.45 cm2) of 2 oz. (0.071 mm thick) Cu. Submit Documentation Feedback Copyright © 2011–2015, Texas Instruments Incorporated Product Folder Links: CSD16415Q5 3 CSD16415Q5 SLPS259A – DECEMBER 2011 – REVISED SEPTEMBER 2015 GATE www.ti.com GATE Source N-Chan 5x6 QFN TTA MIN Rev3 N-Chan 5x6 QFN TTA MAX Rev3 Max RθJA = 50°C/W when mounted on 1 inch2 (6.45 cm2) of 2 oz. (0.071 mm thick) Cu. Source Max RθJA = 125°C/W when mounted on minimum pad area of 2 oz. (0.071 mm thick) Cu. DRAIN DRAIN M0137-02 M0137-01 5.3 Typical MOSFET Characteristics TA = 25°C (unless otherwise noted) Figure 1. Transient Thermal Impedance 4 Submit Documentation Feedback Copyright © 2011–2015, Texas Instruments Incorporated Product Folder Links: CSD16415Q5 CSD16415Q5 www.ti.com SLPS259A – DECEMBER 2011 – REVISED SEPTEMBER 2015 Typical MOSFET Characteristics (continued) TA = 25°C (unless otherwise noted) 100 80 60 40 20 VGS = 4.5 V VGS = 10 V 80 70 60 50 40 30 20 10 0 0 0.05 0.1 0.15 0.2 0.25 VDS - Drain-to-Source Voltage (V) TC = 125° C TC = 25° C TC = -55° C 90 IDS - Drain-to-Source Current (A) IDS - Drain-to-Source Current (A) 100 0 1.5 0.3 2 2.5 3 VGS - Gate-to-Source Voltage (V) D002 Figure 2. Saturation Characteristics Figure 3. Transfer Characteristics 10 Ciss = Cgd + Cgs Coss = Cds + Cgd Crss = Cgd 10000 C - Capacitance (pF) VGS - Gate-to-Source Voltage (V) D003 50000 12 8 6 4 1000 100 2 10 0 0 10 20 30 40 Qg - Gate Charge (nC) ID = 40 A 50 0 60 5 D004 25 D005 Figure 5. Capacitance 2.1 RDS(on) - On-State Resistance (m:) 5 1.9 1.7 1.5 1.3 1.1 0.9 0.7 -75 10 15 20 VDS - Drain-to-Source Voltage (V) VDS = 12.5 V Figure 4. Gate Charge VGS(th) - Threshold Voltage (V) 3.5 TC = 25° C, I D = 40 A TC = 125° C, I D = 40 A 4.5 4 3.5 3 2.5 2 1.5 1 0.5 0 -50 -25 0 25 50 75 100 TC - Case Temperature (° C) 125 150 175 0 1 D006 2 3 4 5 6 7 8 VGS - Gate-to-Source Voltage (V) 9 10 D007 ID = 250 µA Figure 6. Threshold Voltage vs Temperature Figure 7. On-Resistance vs Gate Voltage Submit Documentation Feedback Copyright © 2011–2015, Texas Instruments Incorporated Product Folder Links: CSD16415Q5 5 CSD16415Q5 SLPS259A – DECEMBER 2011 – REVISED SEPTEMBER 2015 www.ti.com Typical MOSFET Characteristics (continued) TA = 25°C (unless otherwise noted) 100 1.5 1.4 1.3 1.2 1.1 1 0.9 0.8 0.7 -75 TC = 25° C TC = 125° C VGS = 10 V ISD - Source-to-Drain Current (A) Normalized On-State Resistance 1.6 10 1 0.1 0.01 0.001 0.0001 -50 -25 0 25 50 75 100 TC - Case Temperature (° C) 125 150 175 0 0.2 D008 0.4 0.6 0.8 VSD - Source-to-Drain Voltage (V) 1 D009 ID = 40 A Figure 8. On-Resistance vs Temperature Figure 9. Typical Diode Forward Voltage 1000 IAV - Peak Avalanche Current (A) IDS - Drain-to-Source Current (A) 1000 100 10 1 100 ms 10 ms 0.1 0.1 1 ms 100 µs 1 10 VDS - Drain-to-Source Voltage (V) 100 TC = 25q C TC = 125q C 100 10 1 0.001 0.01 D010 0.1 1 TAV - Time in Avalanche (ms) 10 100 D011 Single Pulse, Max RθJC = 0.8°C/W Figure 10. Maximum Safe Operating Area Figure 11. Single-Pulse Unclamped Inductive Switching IDS - Drain-to-Source Current (A) 120 100 80 60 40 20 0 -50 -25 0 25 50 75 100 125 TC - Case Temperature (° C) 150 175 D012 Figure 12. Maximum Drain Current vs Temperature 6 Submit Documentation Feedback Copyright © 2011–2015, Texas Instruments Incorporated Product Folder Links: CSD16415Q5 CSD16415Q5 www.ti.com SLPS259A – DECEMBER 2011 – REVISED SEPTEMBER 2015 6 Device and Documentation Support 6.1 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support. 6.2 Trademarks NexFET, E2E are trademarks of Texas Instruments. All other trademarks are the property of their respective owners. 6.3 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 6.4 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. Submit Documentation Feedback Copyright © 2011–2015, Texas Instruments Incorporated Product Folder Links: CSD16415Q5 7 CSD16415Q5 SLPS259A – DECEMBER 2011 – REVISED SEPTEMBER 2015 www.ti.com 7 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 7.1 Q5 Package Dimensions K L L c1 E1 E2 b D2 4 4 5 5 e 3 6 3 6 E D1 7 7 2 2 8 8 1 1 q Top View Bottom View Side View A q c E1 Front View M0140-01 DIM MILLIMETERS MIN INCHES MAX MIN TYP MAX A 0.950 1.050 0.037 0.039 b 0.360 0.460 0.014 0.018 c 0.150 0.250 0.006 0.010 c1 0.150 0.250 0.006 0.010 D1 4.900 5.100 0.193 0.201 D2 4.320 4.520 0.170 0.178 E 4.900 5.100 0.193 0.201 E1 5.900 6.100 0.232 0.240 E2 3.920 4.12 0.154 e 8 TYP 1.27 K 0.760 L 0.510 θ 0.00 0.162 0.050 0.030 0.710 0.020 Submit Documentation Feedback 0.028 Copyright © 2011–2015, Texas Instruments Incorporated Product Folder Links: CSD16415Q5 CSD16415Q5 www.ti.com SLPS259A – DECEMBER 2011 – REVISED SEPTEMBER 2015 7.2 Recommended PCB Pattern F1 F7 8 F3 1 F2 F11 F5 F9 5 4 F6 F8 F4 F10 M0139-01 DIM MILLIMETERS INCHES MIN MAX MIN MAX F1 6.205 6.305 0.244 0.248 F2 4.460 4.560 0.176 0.180 F3 4.460 4.560 0.176 0.180 F4 0.650 0.700 0.026 0.028 F5 0.620 0.670 0.024 0.026 F6 0.630 0.680 0.025 0.027 F7 0.700 0.800 0.028 0.031 F8 0.650 0.700 0.026 0.028 F9 0.620 0.670 0.024 0.026 F10 4.900 5.000 0.193 0.197 F11 4.460 4.560 0.176 0.180 For recommended circuit layout for PCB designs, see Reducing Ringing Through PCB Layout Techniques (SLPA005). Submit Documentation Feedback Copyright © 2011–2015, Texas Instruments Incorporated Product Folder Links: CSD16415Q5 9 CSD16415Q5 SLPS259A – DECEMBER 2011 – REVISED SEPTEMBER 2015 www.ti.com K0 4.00 ±0.10 (See Note 1) 0.30 ±0.05 2.00 ±0.05 +0.10 –0.00 12.00 ±0.30 Ø 1.50 1.75 ±0.10 7.3 Q5 Tape and Reel Information 5.50 ±0.05 B0 R 0.30 MAX A0 8.00 ±0.10 Ø 1.50 MIN R 0.30 TYP A0 = 6.50 ±0.10 B0 = 5.30 ±0.10 K0 = 1.40 ±0.10 M0138-01 Notes: 1. 10 sprocket hole pitch cumulative tolerance ±0.2 2. Camber not to exceed 1 mm in 100 mm, noncumulative over 250 mm 3. Material: black, static-dissipative polystyrene 4. All dimensions are in mm (unless otherwise specified) 5. A0 and B0 measured on a plane 0.3 mm above the bottom of the pocket 6. MSL1 260°C (IR and Convection) PbF Reflow Compatible 10 Submit Documentation Feedback Copyright © 2011–2015, Texas Instruments Incorporated Product Folder Links: CSD16415Q5 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) CSD16415Q5 ACTIVE VSON-CLIP DQH 8 2500 RoHS-Exempt & Green SN Level-1-260C-UNLIM -55 to 150 CSD16415 CSD16415Q5T ACTIVE VSON-CLIP DQH 8 250 RoHS-Exempt & Green SN Level-1-260C-UNLIM -55 to 150 CSD16415 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of