CSD16570Q5B

Order Now Product Folder Support & Community Tools & Software Technical Documents CSD16570Q5B SLPS496A – JULY 2014 – REVISED MAY 2017 CSD16570Q5B 25-V N-Channel NexFET™ Power MOSFET 1 Features • • • • • • • • 1 Product Summary Extremely Low Resistance Low Qg and Qgd Low Thermal Resistance Avalanche Rated Pb Free Terminal Plating RoHS Compliant Halogen Free SON 5-mm × 6-mm Plastic Package TA = 25°C 25 V Qg Gate Charge Total (4.5 V) 95 nC Qgd Gate Charge Gate-to-Drain RDS(on) Drain-to-Source On-Resistance VGS(th) Threshold Voltage This 25 V, 0.49 mΩ, SON 5 × 6 mm NexFET™ power MOSFET is designed to minimize resistance for ORing and hot swap applications and is not designed for switching applications. Top Icon VGS = 10 V 0.49 mΩ 1.5 V Device Qty Media Package Ship 2500 13-Inch Reel CSD16570Q5BT 250 7-Inch Reel SON 5 × 6 mm Plastic Package Tape and Reel Absolute Maximum Ratings TA = 25°C VALUE UNIT VDS Drain-to-Source Voltage 25 V VGS Gate-to-Source Voltage ±20 V Continuous Drain Current (Package limited) 100 Continuous Drain Current (Silicon limited), TC = 25°C 456 1 8 D ID S 2 7 D IDM 4 mΩ CSD16570Q5B S G nC 0.68 (1) For all available packages, see the orderable addendum at the end of the data sheet. 3 Description 3 31 VGS = 4.5 V Ordering Information(1) ORing and Hot Swap Applications S UNIT Drain-to-Source Voltage 2 Applications • TYPICAL VALUE VDS 6 D 5 D Continuous Drain Current(1) 59 Pulsed Drain Current(2) 400 Power Dissipation(1) 3.2 Power Dissipation, TC = 25°C 195 TJ, Tstg Operating Junction and Storage Temperature Range –55 to 150 °C EAS Avalanche Energy, single pulse ID = 98 A, L = 0.1 mH, RG = 25 Ω 480 mJ PD D P0093-01 A A W (1) Typical RθJA = 40°C/W on a 1-inch2 , 2-oz. Cu pad on a 0.06-inch thick FR4 PCB. (2) Max RθJC = 0.8°C/W, Pulse duration ≤ 100 μs, duty cycle ≤1% . . RDS(on) vs VGS Gate Charge 10 TC = 25°C, I D = 50A TC = 125°C, I D = 50A VGS - Gate-to-Source Voltage (V) RDS(on) - On-State Resistance (mΩ) 2 1.8 1.6 1.4 1.2 1 0.8 0.6 0.4 0.2 0 0 2 4 6 8 10 12 14 16 VGS - Gate-to- Source Voltage (V) 18 20 G001 ID = 50A VDS = 12.5V 9 8 7 6 5 4 3 2 1 0 0 20 40 60 80 100 120 140 160 180 200 Qg - Gate Charge (nC) G001 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. CSD16570Q5B SLPS496A – JULY 2014 – REVISED MAY 2017 www.ti.com Table of Contents 1 2 3 4 5 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Specifications......................................................... 1 1 1 2 3 5.1 Electrical Characteristics........................................... 3 5.2 Thermal Information .................................................. 3 5.3 Typical MOSFET Characteristics.............................. 4 6 Device and Documentation Support.................... 7 6.1 Receiving Notification of Documentation Updates.... 7 6.2 6.3 6.4 6.5 7 Community Resources.............................................. Trademarks ............................................................... Electrostatic Discharge Caution ................................ Glossary .................................................................... 7 7 7 7 Mechanical, Packaging, and Orderable Information ............................................................. 8 7.1 7.2 7.3 7.4 Q5B Package Dimensions ........................................ 8 Recommended PCB Pattern..................................... 9 Recommended Stencil Pattern ................................. 9 Q5B Tape and Reel Information ............................. 10 4 Revision History Changes from Original (July 2014) to Revision A Page • Added the Receiving Notification of Documentation Updates and Community Resource sections to Device and Documentation Support. ........................................................................................................................................................ 7 • Changed the dimension between pads 3 and 4 from 0.028 inches: to 0.050 inches in the Recommended PCB Pattern section diagram.......................................................................................................................................................... 9 2 Submit Documentation Feedback Copyright © 2014–2017, Texas Instruments Incorporated Product Folder Links: CSD16570Q5B CSD16570Q5B www.ti.com SLPS496A – JULY 2014 – REVISED MAY 2017 5 Specifications 5.1 Electrical Characteristics (TA = 25°C unless otherwise stated) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT STATIC CHARACTERISTICS BVDSS Drain-to-Source Voltage VGS = 0 V, ID = 250 μA IDSS Drain-to-Source Leakage Current VGS = 0 V, VDS = 20 V 1 μA IGSS Gate-to-Source Leakage Current VDS = 0 V, VGS = 20 V 100 nA VGS(th) Gate-to-Source Threshold Voltage VDS = VGS, ID = 250 μA RDS(on) Drain-to-Source On-Resistance gfs Transconductance 25 1.1 V 1.5 1.9 V VGS = 4.5 V, ID = 50 A 0.68 0.82 mΩ VGS = 10 V, ID = 50 A 0.49 0.59 mΩ VDS = 2.5 V, ID = 50 A 278 S DYNAMIC CHARACTERISTICS Ciss Input Capacitance Coss Output Capacitance 10700 14000 pF 1660 2160 pF Crss RG Reverse Transfer Capacitance 996 1290 pF Series Gate Resistance 1.8 3.6 Ω Qg Gate Charge Total (4.5 V) 95 124 nC Qg Gate Charge Total (10 V) 192 250 nC Qgd Gate Charge Gate-to-Drain Qgs Gate Charge Gate-to-Source Qg(th) Gate Charge at Vth Qoss Output Charge td(on) Turn On Delay Time tr Rise Time td(off) Turn Off Delay Time tf Fall Time VGS = 0 V, VDS = 12 V, ƒ = 1 MHz VDS = 12.5 V, ID = 50 A VDS = 12.5 V, VGS = 0 V VDS = 12.5 V, VGS = 10 V, IDS = 50 A, RG = 0 Ω 31 nC 29 nC 15 nC 35 nC 5 ns 43 ns 156 ns 72 ns DIODE CHARACTERISTICS VSD Diode Forward Voltage Qrr Reverse Recovery Charge trr Reverse Recovery Time ISD = 50 A, VGS = 0 V 0.8 VDS= 12.5 V, IF = 50 A, di/dt = 300A/μs 34 1 nC V 21 ns 5.2 Thermal Information (TA = 25°C unless otherwise stated) THERMAL METRIC MIN TYP MAX RθJC Junction-to-Case Thermal Resistance (1) 0.8 RθJA Junction-to-Ambient Thermal Resistance (1) (2) 50 (1) (2) UNIT °C/W RθJC is determined with the device mounted on a 1-inch2 (6.45-cm2), 2-oz. (0.071-mm thick) Cu pad on a 1.5-inches × 1.5-inches (3.81-cm × 3.81-cm), 0.06-inch (1.52-mm) thick FR4 PCB. RθJC is specified by design, whereas RθJA is determined by the user’s board design. Device mounted on FR4 material with 1-inch2 (6.45-cm2), 2-oz. (0.071-mm thick) Cu. Submit Documentation Feedback Copyright © 2014–2017, Texas Instruments Incorporated Product Folder Links: CSD16570Q5B 3 CSD16570Q5B SLPS496A – JULY 2014 – REVISED MAY 2017 GATE www.ti.com GATE Source N-Chan 5x6 QFN TTA MIN Rev3 N-Chan 5x6 QFN TTA MAX Rev3 Max RθJA = 50°C/W when mounted on 1 inch2 (6.45 cm2) of 2-oz. (0.071-mm thick) Cu. Source Max RθJA = 125°C/W when mounted on a minimum pad area of 2-oz. (0.071-mm thick) Cu. DRAIN DRAIN M0137-02 M0137-01 5.3 Typical MOSFET Characteristics (TA = 25°C unless otherwise stated) Figure 1. Transient Thermal Impedance 4 Submit Documentation Feedback Copyright © 2014–2017, Texas Instruments Incorporated Product Folder Links: CSD16570Q5B CSD16570Q5B www.ti.com SLPS496A – JULY 2014 – REVISED MAY 2017 Typical MOSFET Characteristics (continued) 200 200 180 180 IDS - Drain-to-Source Current (A) IDS - Drain-to-Source Current (A) (TA = 25°C unless otherwise stated) 160 140 120 100 80 60 VGS =10V VGS =6V VGS =4.5V 40 20 0 0 160 140 120 100 80 60 20 0 0.02 0.04 0.06 0.08 0.1 0.12 0.14 0.16 0.18 0.2 VDS - Drain-to-Source Voltage (V) G001 TC = 125°C TC = 25°C TC = −55°C 40 0 0.5 1 1.5 2 2.5 3 VGS - Gate-to-Source Voltage (V) 3.5 4 G001 VDS = 5 V Figure 2. Saturation Characteristics Figure 3. Transfer Characteristics 100000 9 8 C − Capacitance (pF) VGS - Gate-to-Source Voltage (V) 10 7 6 5 4 3 10000 1000 Ciss = Cgd + Cgs Coss = Cds + Cgd Crss = Cgd 2 1 0 0 20 40 100 60 80 100 120 140 160 180 200 Qg - Gate Charge (nC) G001 ID = 50 A 0 5 25 G001 VDS = 12.5 V Figure 4. Gate Charge Figure 5. Capacitance 2.1 2 RDS(on) - On-State Resistance (mΩ) VGS(th) - Threshold Voltage (V) 10 15 20 VDS - Drain-to-Source Voltage (V) 1.9 1.7 1.5 1.3 1.1 0.9 0.7 −75 −50 −25 0 25 50 75 100 125 150 175 TC - Case Temperature (ºC) G001 TC = 25°C, I D = 50A TC = 125°C, I D = 50A 1.8 1.6 1.4 1.2 1 0.8 0.6 0.4 0.2 0 0 2 4 6 8 10 12 14 16 VGS - Gate-to- Source Voltage (V) 18 20 G001 ID = 250 µA Figure 6. Threshold Voltage vs Temperature Figure 7. On-State Resistance vs Gate-to-Source Voltage Submit Documentation Feedback Copyright © 2014–2017, Texas Instruments Incorporated Product Folder Links: CSD16570Q5B 5 CSD16570Q5B SLPS496A – JULY 2014 – REVISED MAY 2017 www.ti.com Typical MOSFET Characteristics (continued) (TA = 25°C unless otherwise stated) 1.6 100 VGS = 4.5V VGS = 10V ISD − Source-to-Drain Current (A) Normalized On-State Resistance 1.8 1.4 1.2 1 0.8 0.6 −75 −50 −25 0 25 50 75 100 125 150 175 TC - Case Temperature (ºC) G001 TC = 25°C TC = 125°C 10 1 0.1 0.01 0.001 0.0001 0 0.2 0.4 0.6 0.8 VSD − Source-to-Drain Voltage (V) 1 G001 ID = 50 A Figure 8. Normalized On-State Resistance vs Temperature Figure 9. Typical Diode Forward Voltage 1000 200 10us 100us 1ms 10ms DC IAV - Peak Avalanche Current (A) IDS - Drain-to-Source Current (A) 5000 100 10 1 0.1 0.1 1 10 VDS - Drain-to-Source Voltage (V) 100 TC = 25ºC TC = 125ºC 100 10 0.01 0.1 TAV - Time in Avalanche (mS) G001 1 G001 Single Pulse, Max RθJC = 0.8°C/W Figure 10. Maximum Safe Operating Area Figure 11. Single Pulse Unclamped Inductive Switching IDS - Drain- to- Source Current (A) 120 100 80 60 40 20 0 −50 −25 0 25 50 75 100 125 TC - Case Temperature (ºC) 150 175 G001 Figure 12. Maximum Drain Current vs Temperature 6 Submit Documentation Feedback Copyright © 2014–2017, Texas Instruments Incorporated Product Folder Links: CSD16570Q5B CSD16570Q5B www.ti.com SLPS496A – JULY 2014 – REVISED MAY 2017 6 Device and Documentation Support 6.1 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. 6.2 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support. 6.3 Trademarks NexFET, E2E are trademarks of Texas Instruments. 6.4 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 6.5 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. Submit Documentation Feedback Copyright © 2014–2017, Texas Instruments Incorporated Product Folder Links: CSD16570Q5B 7 CSD16570Q5B SLPS496A – JULY 2014 – REVISED MAY 2017 www.ti.com 7 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 7.1 Q5B Package Dimensions K H D3 6 D1 4 5 e 6 4 3 3 5 D2 7 2 E 2 7 • 1 8 1 8 L b (8x) c1 E1 d1 Top View d2 Bottom View Side View • Front View DIM MILLIMETERS MIN NOM MAX A 0.80 1.00 1.05 b 0.36 0.41 0.46 c 0.15 0.20 0.25 c1 0.15 0.20 0.25 c2 0.20 0.25 0.30 D1 4.90 5.00 5.10 D2 4.12 4.22 4.32 D3 3.90 4.00 4.10 d 0.20 0.25 0.30 d1 0.085 TYP d2 0.319 0.369 0.419 E 4.90 5.00 5.10 E1 5.90 6.00 6.10 E2 3.48 3.58 3.68 e H 0.36 0.46 0.56 L 0.46 0.56 0.66 L1 0.57 0.67 0.77 θ 0° — — K 8 1.27 TYP 1.40 TYP Submit Documentation Feedback Copyright © 2014–2017, Texas Instruments Incorporated Product Folder Links: CSD16570Q5B CSD16570Q5B www.ti.com SLPS496A – JULY 2014 – REVISED MAY 2017 7.2 Recommended PCB Pattern For recommended circuit layout for PCB designs, see application note SLPA005 – Reducing Ringing Through PCB Layout Techniques. 7.3 Recommended Stencil Pattern (0.020) 0.508 x4 (0.011) 0.286 (0.014) 0.350 (0.022) 0.562 x 4 (0.029) 0.746 x 8 2.186 (0.086) 4.318 (0.170) 0.300 (0.012) 1.270 (0.050) (0.030) 0.766 (0.051) 1.294 x8 (0.060) 1.525 1.270 (0.050) (0.042) 1.072 (0.259) 6.586 Submit Documentation Feedback Copyright © 2014–2017, Texas Instruments Incorporated Product Folder Links: CSD16570Q5B 9 CSD16570Q5B SLPS496A – JULY 2014 – REVISED MAY 2017 www.ti.com K0 4.00 ±0.10 (See Note 1) 0.30 ±0.05 2.00 ±0.05 +0.10 –0.00 12.00 ±0.30 Ø 1.50 1.75 ±0.10 7.4 Q5B Tape and Reel Information 5.50 ±0.05 B0 R 0.30 MAX A0 8.00 ±0.10 Ø 1.50 MIN R 0.30 TYP A0 = 6.50 ±0.10 B0 = 5.30 ±0.10 K0 = 1.40 ±0.10 M0138-01 Notes: 1. 10-sprocket hole-pitch cumulative tolerance ±0.2 2. Camber not to exceed 1 mm in 100 mm, noncumulative over 250 mm 3. Material: black static-dissipative polystyrene 4. All dimensions are in mm (unless otherwise specified). 5. A0 and B0 measured on a plane 0.3 mm above the bottom of the pocket. 10 Submit Documentation Feedback Copyright © 2014–2017, Texas Instruments Incorporated Product Folder Links: CSD16570Q5B PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) CSD16570Q5B ACTIVE VSON-CLIP DNK 8 2500 Pb-Free (RoHS Exempt) NIPDAU | SN Level-1-260C-UNLIM -55 to 150 CSD16570 CSD16570Q5BT ACTIVE VSON-CLIP DNK 8 250 Pb-Free (RoHS Exempt) NIPDAU | SN Level-1-260C-UNLIM -55 to 150 CSD16570 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of