CSD17310Q5A

CSD17310Q5A www.ti.com SLPS255A – FEBRUARY 2010 – REVISED JULY 2010 30V, N-Channel NexFET™ Power MOSFETs Check for Samples: CSD17310Q5A FEATURES 1 • • • • • • • • 2 PRODUCT SUMMARY Optimized for 5V Gate Drive Ultralow Qg and Qgd Low Thermal Resistance Avalanche Rated Pb Free Terminal Plating RoHS Compliant Halogen Free SON 5-mm × 6-mm Plastic Package VDS Drain to Source Voltage 30 V Qg Gate Charge Total (4.5V) 8.9 nC Qgd Gate Charge Gate to Drain RDS(on) VGS(th) • DESCRIPTION The NexFET™ power MOSFET has been designed to minimize losses in power conversion applications, and optimized for 5V gate drive applications. Top View 1 8 D S 2 7 D S 3 6 D G 4 mΩ VGS = 4.5V 4.5 mΩ VGS = 8V 3.9 mΩ Threshold Voltage 1.3 V ORDERING INFORMATION Notebook Point of Load Point-of-Load Synchronous Buck in Networking, Telecom and Computing Systems Optimized for Synchronous FET Applications S nC 5.7 Device Package Media CSD17310Q5A SON 5-mm × 6-mm Plastic Package 13-Inch Reel APPLICATIONS • • Drain to Source On Resistance 2.1 VGS = 3V Qty Ship 2500 Tape and Reel ABSOLUTE MAXIMUM RATINGS TA = 25°C unless otherwise stated VALUE UNIT VDS Drain to Source Voltage 30 V VGS Gate to Source Voltage +10 / –8 V Continuous Drain Current, TC = 25°C 100 A Continuous Drain Current(1) 21 A IDM Pulsed Drain Current, TA = 25°C(2) 134 A PD Power Dissipation(1) 3.1 W TJ, TSTG Operating Junction and Storage Temperature Range –55 to 150 °C EAS Avalanche Energy, single pulse ID = 58A, L = 0.1mH, RG = 25Ω 168 mJ ID (1) RqJA = 40°C/W on 1-inch2 (6.45-cm2), 2-oz. (0.071-mm thick) Cu pad on a 0.06-inch (1.52-mm) thick FR4 PCB. (2) Pulse duration ≤300ms, duty cycle ≤2% D 5 D P0093-01 Text 4 Spacing RDS(on) vs VGS Text 4 Spacing GATE CHARGE 8 ID = 20A 14 VGS - Gate-to-Source Voltage - V RDS(on) - On-State Resistance - mΩ 16 12 10 T C = 125°C 8 6 4 T C = 25°C 2 0 ID = 20A VDS = 15V 7 6 5 4 3 2 1 0 0 1 2 3 4 5 6 7 8 VGS - Gate-to-Source Voltage - V 9 10 G006 0 2 4 6 8 10 Qg - Gate Charge - nC 12 14 16 G003 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. NexFET is a trademark of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2010, Texas Instruments Incorporated CSD17310Q5A SLPS255A – FEBRUARY 2010 – REVISED JULY 2010 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise stated) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Static Characteristics BVDSS Drain to Source Voltage VGS = 0V, ID = 250mA IDSS Drain to Source Leakage Current VGS = 0V, VDS = 24V IGSS Gate to Source Leakage Current VDS = 0V, VGS = +10/-8V VGS(th) Gate to Source Threshold Voltage VDS = VGS, ID = 250mA RDS(on) gfs Drain to Source On Resistance Transconductance 30 0.9 V 1 mA 100 nA 1.3 1.8 V VGS = 3V, ID = 20A 5.7 7.8 mΩ VGS = 4.5V, ID = 20A 4.5 5.9 mΩ VGS = 8V, ID = 20A 3.9 5.1 mΩ VDS = 15V, ID = 20A 85 S Dynamic Characteristics Ciss Input Capacitance Coss Output Capacitance 1200 1560 pF 630 820 Crss pF Reverse Transfer Capacitance 59 77 pF RG Series Gate Resistance 0.9 1.8 Ω Qg Gate Charge Total (4.5V) 8.9 11.6 nC Qgd Gate Charge Gate to Drain Qgs Gate Charge Gate to Source Qg(th) Gate Charge at Vth Qoss Output Charge td(on) Turn On Delay Time tr Rise Time td(off) Turn Off Delay Time tf Fall Time VGS = 0V, VDS = 15V, f = 1MHz VDS = 15V, IDS = 20A VDS = 12.8V, VGS = 0V VDS = 15V, VGS = 4.5V, IDS = 20A, RG = 2Ω 2.1 nC 2.7 nC 1.4 nC 15.9 nC 6.5 ns 11.6 ns 15 ns 5 ns Diode Characteristics VSD Diode Forward Voltage Qrr Reverse Recovery Charge trr Reverse Recovery Time ISD = 20A, VGS = 0V 0.85 VDD= 12.8V, IF = 20A, di/dt = 300A/ms 1 V 21 nC 22 ns THERMAL CHARACTERISTICS (TA = 25°C unless otherwise stated) PARAMETER RqJC RqJA (1) (2) Thermal Resistance Junction to Ambient (1) (2) 2 TYP MAX UNIT 1.9 °C/W 51 °C/W 2 RqJC is determined with the device mounted on a 1-inch (6.45-cm ), 2-oz. (0.071-mm thick) Cu pad on a 1.5-inch × 1.5-inch (3.81-cm × 3.81-cm), 0.06-inch (1.52-mm) thick FR4 PCB. RqJC is specified by design, whereas RqJA is determined by the user’s board design. Device mounted on FR4 material with 1-inch2 (6.45-cm2), 2-oz. (0.071-mm thick) Cu. Text Text Text Text 2 MIN Thermal Resistance Junction to Case (1) and and and and br br br br Added Added Added Added Submit Documentation Feedback for for for for Spacing Spacing Spacing Spacing Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): CSD17310Q5A CSD17310Q5A www.ti.com SLPS255A – FEBRUARY 2010 – REVISED JULY 2010 GATE GATE Source N-Chan 5x6 QFN TTA MIN Rev3 N-Chan 5x6 QFN TTA MAX Rev3 Max RqJA = 51°C/W when mounted on 1 inch2 (6.45 cm2) of 2-oz. (0.071-mm thick) Cu. Source Max RqJA = 123°C/W when mounted on a minimum pad area of 2-oz. (0.071-mm thick) Cu. DRAIN DRAIN M0137-02 M0137-01 TYPICAL MOSFET CHARACTERISTICS (TA = 25°C unless otherwise stated) ZqJA - Normalized Thermal Impedance 10 1 0.5 0.3 0.1 Duty Cycle = t1/t2 0.1 0.05 P 0.01 0.02 0.01 t1 t2 Single Pulse 0.001 0.001 0.01 Typical RqJA = 98°C/W (min Cu) TJ = P ´ ZqJA ´ RqJA 0.1 1 tp - Pulse Duration - s 10 100 1k G012 Figure 1. Transient Thermal Impedance Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): CSD17310Q5A 3 CSD17310Q5A SLPS255A – FEBRUARY 2010 – REVISED JULY 2010 www.ti.com TYPICAL MOSFET CHARACTERISTICS (continued) (TA = 25°C unless otherwise stated) TEXT ADDED FOR SPACING TEXT ADDED FOR SPACING 60 60 IDS - Drain-to-Source Current - A IDS - Drain-to-Source Current - A VDS = 5V 50 VGS = 8V 40 VGS = 4.5V 30 VGS = 3.5V 20 VGS = 3V VGS = 2.5V 10 0 50 T C = 125°C 40 30 T C = 25°C 20 T C = -55°C 10 0 0 0.2 0.4 0.6 0.8 VDS - Drain-to-Source Voltage - V 1 1 1.2 1.4 1.6 1.8 2 2.2 VGS - Gate-to-Source Voltage - V G001 Figure 2. Saturation Characteristics TEXT ADDED FOR SPACING TEXT ADDED FOR SPACING ID = 20A VDS = 15V 7 f = 1MHz VGS = 0V 2.5 6 C - Capacitance - nF VGS - Gate-to-Source Voltage - V G002 3 5 4 3 2 Coss = Cds + Cgd 2 Ciss = Cgd + Cgs 1.5 1 Crss = Cgd 0.5 1 0 0 0 2 4 6 8 10 Qg - Gate Charge - nC 12 14 16 0 5 10 15 20 VDS - Drain-to-Source Voltage - V G003 Figure 4. Gate Charge TEXT ADDED FOR SPACING 30 G004 TEXT ADDED FOR SPACING 16 RDS(on) - On-State Resistance - mΩ ID = 250µA 1.6 1.4 1.2 1 0.8 0.6 0.4 0.2 0 -75 25 Figure 5. Capacitance 1.8 VGS(th) - Threshold Voltage - V 2.6 Figure 3. Transfer Characteristics 8 ID = 20A 14 12 10 T C = 125°C 8 6 4 T C = 25°C 2 0 -25 25 75 T C - Case Temperature - °C 125 175 0 1 G005 Figure 6. Threshold Voltage vs. Temperature 4 2.4 2 3 4 5 6 7 8 VGS - Gate-to-Source Voltage - V 9 10 G006 Figure 7. On-State Resistance vs. Gate-to-Source Voltage Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): CSD17310Q5A CSD17310Q5A www.ti.com SLPS255A – FEBRUARY 2010 – REVISED JULY 2010 TYPICAL MOSFET CHARACTERISTICS (continued) (TA = 25°C unless otherwise stated) TEXT ADDED FOR SPACING TEXT ADDED FOR SPACING 100 ID = 20A VGS = 8V 1.4 ISD - Source-to-Drain Current - A Normalized On-State Resistance 1.6 1.2 1 0.8 0.6 0.4 0.2 -75 10 1 T C = 125°C 0.1 T C = 25°C 0.01 0.001 0.0001 -25 25 75 T C - Case Temperature - °C 125 175 0 0.2 G007 Figure 8. Normalized On-State Resistance vs. Temperature TEXT ADDED FOR SPACING TEXT ADDED FOR SPACING I(AV) - Peak Avalanche Current - A IDS - Drain-to-Source Current - A 1ms 10 10ms 0.01 0.01 G008 1k 100 0.1 1 Figure 9. Typical Diode Forward Voltage 1k 1 0.4 0.6 0.8 VSD - Source-to-Drain Voltage - V 1001 100ms Area Limited by RDS(on) 1s Single Pulse Typical R θJA = 98°C/W (min Cu) DC 0.1 1 10 VDS - Drain-to-Source Voltage - V 100 100 10 T C = 25°C T C = 125°C 1 0.01 G009 Figure 10. Maximum Safe Operating Area 0.1 1 10 t(AV) - Time in Avalanche - ms 100 G010 Figure 11. Single Pulse Unclamped Inductive Switching TEXT ADDED FOR SPACING IDS - Drain-to-Source Current - A 120 100 80 60 40 20 0 -50 -25 0 25 50 75 100 125 T C - Case Temperature - °C 150 175 G011 Figure 12. Maximum Drain Current vs. Temperature Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): CSD17310Q5A 5 CSD17310Q5A SLPS255A – FEBRUARY 2010 – REVISED JULY 2010 www.ti.com MECHANICAL DATA Q5A Package Dimensions L E2 H K 7 D2 3 4 b 4 5 5 6 3 6 e D1 7 2 2 8 8 1 1 q L1 Top View Bottom View Side View c A q E1 E Front View M0135-01 DIM 6 MILLIMETERS MIN NOM MAX A 0.90 1.00 1.10 b 0.33 0.41 0.51 c 0.20 0.25 0.34 D1 4.80 4.90 5.00 D2 3.61 3.81 4.02 E 5.90 6.00 6.10 E1 5.70 5.75 5.80 E2 3.38 3.58 3.78 e 1.17 1.27 1.37 H 0.41 0.56 0.71 K 1.10 L 0.51 0.61 0.71 L1 0.06 0.13 0.20 q 0° Submit Documentation Feedback 12° Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): CSD17310Q5A CSD17310Q5A www.ti.com SLPS255A – FEBRUARY 2010 – REVISED JULY 2010 DIM Recommended PCB Pattern F1 F7 F3 8 1 F2 F11 F5 F9 5 4 F6 MILLIMETERS INCHES MIN MAX MIN MAX F1 6.205 6.305 0.244 0.248 F2 4.46 4.56 0.176 0.18 F3 4.46 4.56 0.176 0.18 F4 0.65 0.7 0.026 0.028 F5 0.62 0.67 0.024 0.026 F6 0.63 0.68 0.025 0.027 F7 0.7 0.8 0.028 0.031 F8 0.65 0.7 0.026 0.028 F9 0.62 0.67 0.024 0.026 F10 4.9 5 0.193 0.197 F11 4.46 4.56 0.176 0.18 F8 F4 F10 M0139-01 For recommended circuit layout for PCB designs, see application note SLPA005 – Reducing Ringing Through PCB Layout Techniques. K0 4.00 ±0.10 (See Note 1) 0.30 ±0.05 2.00 ±0.05 +0.10 –0.00 12.00 ±0.30 Ø 1.50 1.75 ±0.10 Q5A Tape and Reel Information 5.50 ±0.05 B0 R 0.30 MAX A0 8.00 ±0.10 Ø 1.50 MIN A0 = 6.50 ±0.10 B0 = 5.30 ±0.10 K0 = 1.40 ±0.10 R 0.30 TYP M0138-01 Notes: 1. 10-sprocket hole-pitch cumulative tolerance ±0.2 2. Camber not to exceed 1mm in 100mm, noncumulative over 250mm 3. Material: black static-dissipative polystyrene 4. All dimensions are in mm (unless otherwise specified) 5. A0 and B0 measured on a plane 0.3mm above the bottom of the pocket Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): CSD17310Q5A 7 CSD17310Q5A SLPS255A – FEBRUARY 2010 – REVISED JULY 2010 www.ti.com REVISION HISTORY Changes from Original (February 2010) to Revision A Page • Updated the Q5A Package Dimensions table. DIM c MAX was 0.30, DIM D2 MAX was 3.96, DIM e MIN was blank MAX was blank, DIM H NOM was 0.51 MAX was 0.61 ....................................................................................................... 6 • Deleted Note 6 from the Q5A Tape and Reel Information - "MSL1 260°C (IR and convection) PbF reflow compatible" ........................................................................................................................................................................... 7 • Deleted the Package Marking Information section ............................................................................................................... 7 8 Submit Documentation Feedback Copyright © 2010, Texas Instruments Incorporated Product Folder Link(s): CSD17310Q5A PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) CSD17310Q5A ACTIVE VSONP DQJ 8 2500 RoHS-Exempt & Green SN Level-1-260C-UNLIM -55 to 150 CSD17310 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of