CSD17484F4T

CSD17484F4 SLPS550D – MAY 2015 – REVISED FEBRUARY 2022 CSD17484F4 30-V N-Channel FemtoFET™ MOSFET Product Summary 1 Features • • • • • • • • TA = 25°C Low on-resistance Ultra-low Qg and Qgd Low-threshold voltage Ultra-small footprint (0402 Case Size) – 1.0 mm × 0.6 mm Ultra-low profile – 0.2-mm height Integrated ESD protection diode – Rated > 4-kV HBM – Rated > 2-kV CDM Lead and halogen free RoHS compliant • • UNIT VDS Drain-to-Source Voltage 30 V Qg Gate Charge Total (4.5 V) 920 pC Qgd Gate Charge Gate-to-Drain 75 RDS(on) Drain-to-Source On-Resistance VGS(th) Threshold Voltage pC VGS = 1.8 V 170 VGS = 2.5 V 125 VGS = 4.5 V 107 VGS = 8.0 V 99 0.85 mΩ V Device Information(1) DEVICE QTY CSD17484F4 3000 CSD17484F4T 2 Applications • • TYPICAL VALUE (1) Optimized for load switch applications Optimized for general purpose switching applications Battery applications Handheld and mobile applications 250 MEDIA PACKAGE SHIP 7-Inch Reel Femto (0402) 1.00-mm × 0.60-mm Land Grid Array (LGA) Tape and Reel For all available packages, see the orderable addendum at the end of the data sheet. Absolute Maximum Ratings TA = 25°C 3 Description This 99-mΩ, 30-V, N-Channel FemtoFET™ MOSFET is designed and optimized to minimize the footprint in many handheld and mobile applications. This technology is capable of replacing standard small signal MOSFETs while providing at least a 60% reduction in footprint size. VALUE UNIT VDS Drain-to-Source Voltage 30 V VGS Gate-to-Source Voltage 12 V ID Continuous Drain Current(1) 3.0 A 18 A IDM IG PD V(ESD) Continuous Gate Clamp Current 35 Pulsed Gate Clamp Current(2) 350 Power Dissipation 500 Human-Body Model (HBM) 4 Charged-Device Model (CDM) 2 TJ, Tstg Operating Junction, Storage Temperature EAS Avalanche Energy, Single Pulse ID = 7.1 A, L = 0.1 mH, RG = 25 Ω (1) 0.2 Pulsed Drain Current(1) (2) m 0m (2) mA mW kV –55 to 150 °C 2.5 mJ Typical RθJA = 85°C/W on 1-in2 (6.45-cm2), 2-oz (0.071-mm) thick Cu pad on a 0.06-in (1.52-mm) thick FR4 PCB. Pulse duration ≤ 100 μs, duty cycle ≤ 1%. 60 1. 0. 00 m m D m m Figure 3-1. Typical Part Dimensions G S Figure 3-2. Top View An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. CSD17484F4 www.ti.com SLPS550D – MAY 2015 – REVISED FEBRUARY 2022 Table of Contents 1 Features............................................................................1 2 Applications..................................................................... 1 3 Description.......................................................................1 4 Revision History.............................................................. 2 5 Specifications.................................................................. 3 5.1 Electrical Characteristics.............................................3 5.2 Thermal Information....................................................3 5.3 Typical MOSFET Characteristics................................ 4 6 Device and Documentation Support..............................7 6.1 Receiving Notification of Documentation Updates......7 6.2 Trademarks................................................................. 7 7 Mechanical, Packaging, and Orderable Information.... 8 7.1 Mechanical Dimensions.............................................. 8 7.2 Recommended Minimum PCB Layout........................9 7.3 Recommended Stencil Pattern................................... 9 4 Revision History Changes from Revision C (December 2019) to Revision D (February 2022) Page • Added FemtoFET Surface Mount Guide note.................................................................................................... 9 Changes from Revision B (September 2017) to Revision C (December 2019) Page • Changed On-State Resistance vs Gate-to-Source Voltage by truncating VGS from 20 V to 12 V...................... 4 Changes from Revision A (August 2017) to Revision B (September 2017) Page • Deleted the CSD68830F4 Embossed Carrier Tape Dimensions section............................................................9 Changes from Revision * (May 2015) to Revision A (August 2017) Page • Added the Section 6.1 and the Section 6 sections ............................................................................................ 7 • Updated the Section 7 section............................................................................................................................8 2 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: CSD17484F4 CSD17484F4 www.ti.com SLPS550D – MAY 2015 – REVISED FEBRUARY 2022 5 Specifications 5.1 Electrical Characteristics TA = 25°C (unless otherwise stated) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 100 nA STATIC CHARACTERISTICS BVDSS Drain-to-source voltage VGS = 0 V, IDS = 250 μA IDSS Drain-to-source leakage current VGS = 0 V, VDS = 24 V IGSS Gate-to-source leakage current VDS = 0 V, VGS = 12 V VGS(th) Gate-to-source threshold voltage VDS = VGS, IDS = 250 μA RDS(on) Drain-to-source on-resistance gfs Transconductance 30 V 50 nA 0.85 1.10 V VGS = 1.8 V, IDS = 0.5 A 170 270 VGS = 2.5 V, IDS = 0.5 A 125 160 VGS = 4.5 V, IDS = 0.5 A 107 128 VGS = 8 V, IDS = 0.5 A 99 121 VDS = 15 V, IDS = 0.5 A 4 0.65 mΩ S DYNAMIC CHARACTERISTICS Ciss Input capacitance 150 Coss Output capacitance Crss Reverse transfer capacitance RG Series gate resistance Qg Gate charge total (4.5 V) Qg Gate charge total (8.0 V) Qgd Gate charge gate-to-drain Qgs Qg(th) Qoss Output charge td(on) Turnon delay time tr Rise time td(off) Turnoff delay time tf Fall time VGS = 0 V, VDS = 15 V, ƒ = 1 MHz 195 pF 44 57 pF 2.2 2.9 pF 920 1200 pC 1570 2040 pC 8 VDS = 15 V, IDS = 0.5 A Ω 75 pC Gate charge gate-to-source 280 pC Gate charge at Vth 140 pC 1400 pC 3 ns VDS = 15 V, VGS = 0 V VDS = 15 V, VGS = 4.5 V, IDS = 0.5 A, RG = 2 Ω 1 ns 11 ns 4 ns DIODE CHARACTERISTICS VSD Diode forward voltage Qrr Reverse recovery charge trr Reverse recovery time ISD = 0.5 A, VGS = 0 V VDS= 15 V, IF = 0.5 A, di/dt = 300 A/μs 0.73 0.9 V 1300 pC 6.2 ns 5.2 Thermal Information TA = 25°C (unless otherwise stated) THERMAL METRIC RθJA (1) (2) TYPICAL VALUES Junction-to-ambient thermal resistance(1) 85 Junction-to-ambient thermal resistance(2) 245 UNIT °C/W Device mounted on FR4 material with 1-in2 (6.45-cm2), 2-oz (0.071-mm) thick Cu. Device mounted on FR4 material with minimum Cu mounting area. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: CSD17484F4 3 CSD17484F4 www.ti.com SLPS550D – MAY 2015 – REVISED FEBRUARY 2022 5.3 Typical MOSFET Characteristics TA = 25°C (unless otherwise stated) 10 VGS = 1.8 V VGS = 2.5 V VGS = 3.8 V VGS = 4.5 V 9 8 IDS - Drain-to-Source Current (A) IDS - Drain-to-Source Current (A) 10 7 6 5 4 3 2 1 TC = 125°C TC = 25°C TC = -55°C 9 8 7 6 5 4 3 2 1 0 0 0 0.25 0.5 0.75 1 1.25 1.5 VDS - Drain-to-Source Voltage (V) 1.75 2 0 0.5 D002 1 1.5 2 2.5 3 VGS - Gate-to-Source Voltage (V) Figure 5-1. Saturation Characteristics 3.5 4 D003 VDS = 5 V Figure 5-2. Transfer Characteristics Figure 5-3. Transient Thermal Impedance 4 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: CSD17484F4 CSD17484F4 www.ti.com SLPS550D – MAY 2015 – REVISED FEBRUARY 2022 1000 7 6 C - Capacitance (pF) VGS - Gate-to-Source Voltage (V) 8 5 4 3 100 Ciss = Cgd + Cgs Coss = Cds + Cgd Crss = Cgd 10 2 1 1 0 0 0.2 0.4 0.6 0.8 1 Qg - Gate Charge (nC) ID = 0.5 A 1.2 1.4 0 1.6 3 D004 6 9 12 15 18 21 24 VDS - Drain-to-Source Voltage (V) 27 30 D005 Figure 5-5. Capacitance VDS = 15 V Figure 5-4. Gate Charge 250 RDS(on) - On-State Resistance (m:) VGS(th) - Threshold Voltage (V) 1.15 1.05 0.95 0.85 0.75 0.65 0.55 0.45 0.35 -75 -25 0 25 50 75 100 TC - Case Temperature (°C) 125 150 175 175 150 125 100 75 0 2 D006 Figure 5-6. Threshold Voltage vs Temperature 4 6 8 VGS - Gate-to-Source Voltage (V) 10 12 D007 Figure 5-7. On-State Resistance vs Gate-to-Source Voltage 1.5 10 VGS = 2.5 V VGS = 4.5 V ISD - Source-To-Drain Current (A) Normalized On-State Resistance 200 50 -50 ID = 250 µA 1.4 TC = 25qC, ID = 0.5 A TC = 125qC, ID = 0.5 A 225 1.3 1.2 1.1 1 0.9 TC = 25qC TC = 125qC 1 0.1 0.01 0.001 0.8 0.7 -75 0.0001 0 -50 -25 0 25 50 75 100 TC - Case Temperature (qC) 125 150 175 D008 ID = 0.5 A 0.2 0.4 0.6 0.8 VSD - Source-To-Drain Voltage (V) 1 D009 Figure 5-9. Typical Diode Forward Voltage Figure 5-8. Normalized On-State Resistance vs Temperature Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: CSD17484F4 5 CSD17484F4 www.ti.com SLPS550D – MAY 2015 – REVISED FEBRUARY 2022 100 IAV - Peak Avalanche Current (A) IDS - Drain-To-Source Current (A) 100 10 1 0.1 100 ms 10 ms 0.01 0.01 1 ms 100 µs 10 µs 0.1 1 10 VDS - Drain-To-Source Voltage (V) 50 TC = 25q C TC = 125q C 10 1 0.1 0.001 0.01 0.1 TAV - Time in Avalanche (ms) D010 Single pulse, typical RθJA = 85°C/W Figure 5-10. Maximum Safe Operating Area 1 D011 Figure 5-11. Single Pulse Unclamped Inductive Switching IDS - Drain-to-Source Current (A) 3.5 3 2.5 2 1.5 1 0.5 0 -50 -25 0 25 50 75 100 125 TA - Ambient Temperature (°C) 150 175 D012 Figure 5-12. Maximum Drain Current vs Temperature 6 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: CSD17484F4 CSD17484F4 www.ti.com SLPS550D – MAY 2015 – REVISED FEBRUARY 2022 6 Device and Documentation Support 6.1 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. 6.2 Trademarks FemtoFET™ is a trademark of Texas Instruments. All trademarks are the property of their respective owners. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: CSD17484F4 7 CSD17484F4 www.ti.com SLPS550D – MAY 2015 – REVISED FEBRUARY 2022 7 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 7.1 Mechanical Dimensions A. B. C. All linear dimensions are in millimeters (dimensions and tolerancing per AME T14.5M-1994). This drawing is subject to change without notice. This package is a PB-free solder land design. Table 7-1. Pin Configuration POSITION 8 DESIGNATION Pin 1 Gate Pin 2 Source Pin 3 Drain Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: CSD17484F4 CSD17484F4 www.ti.com SLPS550D – MAY 2015 – REVISED FEBRUARY 2022 7.2 Recommended Minimum PCB Layout (0.25) 2X (0.25) PKG 0.05 MIN ALL AROUND 2X (0.15) 1 3 SYMM (0.35) (0.5) EXAMPLE STENCIL DESIGN 2 YJC0003A(R0.05) TYP PicoStar TM - 0.35 mm max height SOLDER MASK OPENING (0.65) LAND PATTERN EXAMPLE A. B. PicoStar TM METAL UNDER SOLDER MASK SOLDER MASK DEFINED All dimensions are in millimeters. SCALE:50X For more information, see FemtoFET Surface Mount Guide (SLRA003D). 7.3 Recommended Stencil Pattern 2X (0.25) 2X (0.2) PKG (0.25) 1 SYMM (0.4) (0.5) 3 2 2X (0.15) (R0.05) TYP (0.65) 2X SOLDER MASK EDGE A. All dimensions are in millimeters. SOLDER PASTE EXAMPLE ON 0.075 - 0.1 mm THICK STENCIL SCALE:50X 4220651/B 08/2015 NOTES: (continued) 4. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). www.ti.com Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: CSD17484F4 9 PACKAGE OPTION ADDENDUM www.ti.com 11-Jan-2022 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) CSD17484F4 ACTIVE PICOSTAR YJJ 3 3000 RoHS & Green NIAU Level-1-260C-UNLIM -55 to 150 G2 CSD17484F4T ACTIVE PICOSTAR YJJ 3 250 RoHS & Green NIAU Level-1-260C-UNLIM -55 to 150 G2 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of