CSD17506Q5A
www.ti.com
SLPS304B – DECEMBER 2010 – REVISED JUNE 2012
30V, N-Channel NexFET™ Power MOSFETs
Check for Samples: CSD17506Q5A
PRODUCT SUMMARY
FEATURES
1
•
•
•
•
•
•
•
2
TA = 25°C unless otherwise stated
Ultralow Qg and Qgd
Low Thermal Resistance
Avalanche Rated
Pb Free Terminal Plating
RoHS Compliant
Halogen Free
SON 5-mm × 6-mm Plastic Package
•
30
V
Qg
Gate Charge Total (4.5V)
8.3
nC
Qgd
Gate Charge Gate to Drain
RDS(on)
Drain to Source On Resistance
VGS(th)
Threshold Voltage
DESCRIPTION
The NexFET™ power MOSFET has been designed
to minimize losses in power conversion applications.
Top View
8
D
S
2
7
D
S
3
6
D
5
4
mΩ
VGS = 10V
3.2
mΩ
1.3
V
Package
Media
CSD17506Q5A
SON 5-mm × 6-mm
Plastic Package
13-Inch
Reel
Qty
Ship
2500
Tape and
Reel
Text Added For Spacing
ABSOLUTE MAXIMUM RATINGS
TA = 25°C unless otherwise stated
VALUE
UNIT
VDS
Drain to Source Voltage
30
V
VGS
Gate to Source Voltage
±20
V
Continuous Drain Current, TC = 25°C
100
A
Continuous Drain Current(1)
23
A
IDM
Pulsed Drain Current, TA = 25°C(2)
150
A
PD
Power Dissipation(1)
3.2
W
TJ,
TSTG
Operating Junction and Storage Temperature
Range
–55 to 150
°C
EAS
Avalanche Energy, single pulse
ID = 72A, L = 0.1mH, RG = 25Ω
259
mJ
(1) Typical RθJA = 39°C/W on a 1-inch2 (6.45-cm2), 2-oz. (0.071mm thick) Cu pad on a 0.06-inch (1.52-mm) thick FR4 PCB.
(2) Pulse duration ≤300μs, duty cycle ≤2%
D
G
nC
4.2
Device
ID
1
2.3
VGS = 4.5V
Text Added For Spacing
ORDERING INFORMATION
Point-of-Load Synchronous Buck in
Networking, Telecom, and Computing Systems
Synchronous or Control FET Applications
S
UNIT
Drain to Source Voltage
APPLICATIONS
•
TYPICAL VALUE
VDS
D
P0093-01
TEXT ADDED FOR SPACING
TEXT ADDED FOR SPACING
RDS(on) vs VGS
TEXT ADDED FOR SPACING
TEXT ADDED FOR SPACING
GATE CHARGE
16
10
14
VGS - Gate-to-Source Voltage (V)
RDS(on) - On-State Resistance - mΩ
ID = 20A
12
10
8
6
4
TC = 25°C
TC = 125ºC
2
0
0
1
2
3
ID = 20A
VDD = 15V
9
8
7
6
5
4
3
2
1
4
5
6
7
VGS - Gate-to- Source Voltage - V
8
9
10
0
0
2
4
6
8
10
12
14
16
18
Qg - Gate Charge - nC (nC)
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
NexFET is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2010–2012, Texas Instruments Incorporated
CSD17506Q5A
SLPS304B – DECEMBER 2010 – REVISED JUNE 2012
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ELECTRICAL CHARACTERISTICS
(TA = 25°C unless otherwise stated)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Static Characteristics
BVDSS
Drain to Source Voltage
VGS = 0V, IDS = 250μA
IDSS
Drain to Source Leakage Current
VGS = 0V, VDS = 24V
IGSS
Gate to Source Leakage Current
VDS = 0V, VGS = 20V
VGS(th)
Gate to Source Threshold Voltage
VDS = VGS, IDS = 250μA
RDS(on)
Drain to Source On Resistance
gfs
Transconductance
30
1
V
1
μA
100
nA
1.3
1.8
V
VGS = 4.5V, IDS = 20A
4.2
5.3
mΩ
VGS = 10V, IDS = 20A
3.2
4
mΩ
VDS = 15V, IDS = 20A
76
S
Dynamic Characteristics
Ciss
Input Capacitance
VGS = 0V, VDS = 15V,
f = 1MHz
1270
1650
pF
Coss
Output Capacitance
860
1120
pF
Crss
Reverse Transfer Capacitance
50
65
pF
RG
Series Gate Resistance
1.1
2.2
Ω
Qg
Gate Charge Total (4.5V)
8.3
11
nC
Qgd
Gate Charge Gate to Drain
2.3
nC
Qgs
Gate Charge Gate to Source
3.1
nC
Qg(th)
Gate Charge at Vth
1.6
nC
Qoss
Output Charge
23
nC
td(on)
Turn On Delay Time
7.5
ns
tr
Rise Time
13
ns
td(off)
Turn Off Delay Time
13
ns
tf
Fall Time
5.3
ns
VDS = 15V, IDS = 20A
VDS = 14V, VGS = 0V
VDS = 15V, VGS = 4.5V,
IDS = 20A, RG = 2Ω
Diode Characteristics
VSD
Diode Forward Voltage
Qrr
Reverse Recovery Charge
trr
Reverse Recovery Time
ISD = 20A, VGS = 0V
0.8
VDD = 14V, IF = 20A, di/dt = 300A/μs
1
V
33
nC
27
ns
THERMAL CHARACTERISTICS
(TA = 25°C unless otherwise stated)
PARAMETER
RθJC
Thermal Resistance Junction to Case (1)
RθJA
Thermal Resistance Junction to Ambient (1) (2)
(1)
(2)
2
MIN
TYP
MAX
UNIT
1
°C/W
50
°C/W
RθJC is determined with the device mounted on a 1-inch2 (6.45-cm2), 2-oz. (0.071-mm thick) Cu pad on a 1.5-inch × 1.5-inch (3.81-cm ×
3.81-cm), 0.06-inch (1.52-mm) thick FR4 PCB. RθJC is specified by design, whereas RθJA is determined by the user’s board design.
Device mounted on FR4 material with 1-inch2 (6.45-cm2), 2-oz. (0.071-mm thick) Cu.
Copyright © 2010–2012, Texas Instruments Incorporated
CSD17506Q5A
www.ti.com
GATE
SLPS304B – DECEMBER 2010 – REVISED JUNE 2012
GATE
Source
N-Chan 5x6 QFN TTA MIN Rev3
N-Chan 5x6 QFN TTA MAX Rev3
Max RθJA = 50°C/W
when mounted on
1 inch2 (6.45 cm2) of 2oz. (0.071-mm thick)
Cu.
Source
Max RθJA = 120°C/W
when mounted on a
minimum pad area of
2-oz. (0.071-mm thick)
Cu.
DRAIN
DRAIN
M0137-02
M0137-01
TEXT ADDED FOR SPACING
TEXT ADDED FOR SPACING
TEXT ADDED FOR SPACING
TEXT ADDED FOR SPACING
TYPICAL MOSFET CHARACTERISTICS
(TA = 25°C unless otherwise stated)
Figure 1. Transient Thermal Impedance
Copyright © 2010–2012, Texas Instruments Incorporated
3
CSD17506Q5A
SLPS304B – DECEMBER 2010 – REVISED JUNE 2012
www.ti.com
TYPICAL MOSFET CHARACTERISTICS (continued)
(TA = 25°C unless otherwise stated)
TEXT ADDED FOR SPACING
TEXT ADDED FOR SPACING
TEXT ADDED FOR SPACING
TEXT ADDED FOR SPACING
80
100
60
50
40
30
VGS = 10V
VGS = 8.0V
VGS = 6.0V
VGS = 4.5V
VGS = 4.0V
20
10
0
0
0.1
0.2
0.3
0.4
0.5
0.6
IDS - Drain-to-Source Current - A
IDS - Drain-to-Source Current - A
VDS = 5V
70
10
1
0.1
0.01
0.001
0.7
TC = 125°C
TC = 25°C
TC = −55°C
0
0.5
1
VDS - Drain-to-Source Voltage - V
2
2.5
3
3.5
Figure 2. Saturation Characteristics
Figure 3. Transfer Characteristics
TEXT ADDED FOR SPACING
TEXT ADDED FOR SPACING
TEXT ADDED FOR SPACING
TEXT ADDED FOR SPACING
10
4
100
Ciss = Cgd + Cgs
Coss = Cds + Cgd
Crss = Cgd
ID = 20A
VDD = 15V
9
8
10
C − Capacitance − nF
VGS - Gate-to-Source Voltage (V)
1.5
VGS - Gate-to-Source Voltage - V
7
6
5
4
3
1
0.1
2
1
0
0
2
4
6
8
10
12
14
16
0.01
18
0
5
10
Qg - Gate Charge - nC (nC)
15
20
25
Figure 4. Gate Charge
Figure 5. Capacitance
TEXT ADDED FOR SPACING
TEXT ADDED FOR SPACING
TEXT ADDED FOR SPACING
TEXT ADDED FOR SPACING
16
2.1
ID = 20A
RDS(on) - On-State Resistance - mΩ
VGS(th) - Threshold Voltage - V
ID = 250µA
1.8
1.5
1.2
0.9
0.6
0.3
0
−75
−25
25
75
125
TC - Case Temperature - ºC
Figure 6. Threshold Voltage vs. Temperature
4
30
VDS - Drain-to-Source Voltage - V
175
14
12
10
8
6
4
TC = 25°C
TC = 125ºC
2
0
0
1
2
3
4
5
6
7
8
9
10
VGS - Gate-to- Source Voltage - V
Figure 7. On-State Resistance vs. Gate-to-Source Voltage
Copyright © 2010–2012, Texas Instruments Incorporated
CSD17506Q5A
www.ti.com
SLPS304B – DECEMBER 2010 – REVISED JUNE 2012
TYPICAL MOSFET CHARACTERISTICS (continued)
(TA = 25°C unless otherwise stated)
TEXT ADDED FOR SPACING
TEXT ADDED FOR SPACING
TEXT ADDED FOR SPACING
TEXT ADDED FOR SPACING
1.6
100
ID = 20A
VGS = 10V
ISD − Source-to-Drain Current - A
Normalized On-State Resistance
1.8
1.4
1.2
1
0.8
0.6
0.4
0.2
−75
−25
25
75
125
10
1
0.1
0.01
0.001
0.0001
175
TC = 25°C
TC = 125°C
0
0.2
0.4
0.6
0.8
Figure 8. Normalized On-State Resistance vs. Temperature
Figure 9. Typical Diode Forward Voltage
TEXT ADDED FOR SPACING
TEXT ADDED FOR SPACING
TEXT ADDED FOR SPACING
TEXT ADDED FOR SPACING
1000
1ms
10ms
100ms
1s
DC
I(AV) - Peak Avalanche Current - A
IDS - Drain-to-Source Current - A
2000
1000
100
10
1
0.1
1
VSD − Source-to-Drain Voltage - V
TC - Case Temperature - ºC
Single Pulse
Typical RthetaJA =96ºC/W(min Cu)
0.01
0.01
0.1
1
10
VDS - Drain-to-Source Voltage - V
50
TC = 125°C
TC = 25°C
100
10
1
0.01
G001
0.1
1
10
t(AV) - Time in Avalanche - ms
Figure 10. Maximum Safe Operating Area
Figure 11. Single Pulse Unclamped Inductive Switching
TEXT ADDED FOR SPACING
TEXT ADDED FOR SPACING
TEXT ADDED FOR SPACING
IDS - Drain- to- Source Current - A
120
100
80
60
40
20
0
−50
−25
0
25
50
75
100
125
150
175
TC - Case Temperature - ºC
Figure 12. Maximum Drain Current vs. Temperature
Copyright © 2010–2012, Texas Instruments Incorporated
5
CSD17506Q5A
SLPS304B – DECEMBER 2010 – REVISED JUNE 2012
www.ti.com
MECHANICAL DATA
Q5A Package Dimensions
E2
L
K
H
2
7
8
8
2
7
1
1
q
3
5
4
6
3
4
D2
6
D1
5
e
b
L1
Top View
Bottom View
Side View
q
A
c
E1
E
Front View
M0135-01
DIM
6
MILLIMETERS
MIN
NOM
MAX
A
0.90
1.00
1.10
b
0.33
0.41
0.51
c
0.20
0.25
0.34
D1
4.80
4.90
5.00
D2
3.61
3.81
4.02
E
5.90
6.00
6.10
E1
5.70
5.75
5.80
E2
3.38
3.58
3.78
e
1.17
1.27
1.37
H
0.41
0.56
0.71
K
1.10
L
0.51
0.61
0.71
L1
0.06
0.13
0.20
θ
0°
12°
Copyright © 2010–2012, Texas Instruments Incorporated
CSD17506Q5A
www.ti.com
SLPS304B – DECEMBER 2010 – REVISED JUNE 2012
Recommended PCB Pattern
4.900 (0.193)
0.605 (0.024)
5
4
0.630 (0.025)
0.620 (0.024)
1.270
(0.050)
4.460
(0.176)
8
1
0.650 (0.026)
3.102 (0.122)
0.700 (0.028)
1.798 (0.071)
M0139-01
NOTE: Dimensions are in mm (inches).
TEXT ADDED FOR SPACING
Stencil Recommendation
0.500 (0.020)
1.235 (0.049)
0.500 (0.020)
1.585 (0.062)
4
5
0.450
(0.018)
1.570
(0.062)
0.620 (0.024)
1.270
(0.050)
1.570
(0.062)
4.260
(0.168)
8
1
PCB Pattern
0.632 (0.025)
3.037 (0.120)
1.088 (0.043)
Stencil Opening
M0209-01
NOTE: Dimensions are in mm (inches).
TEXT
ADDED
FOR
SPACING
For recommended circuit layout for PCB designs, see application note SLPA005 – Reducing Ringing Through
PCB Layout Techniques.
Copyright © 2010–2012, Texas Instruments Incorporated
7
CSD17506Q5A
SLPS304B – DECEMBER 2010 – REVISED JUNE 2012
www.ti.com
Q5A Tape and Reel Information
K0
4.00 ±0.10 (See Note 1)
0.30 ±0.05
+0.10
2.00 ±0.05
Ø 1.50 –0.00
1.75 ±0.10
5.50 ±0.05
12.00 ±0.30
B0
R 0.30 MAX
A0
8.00 ±0.10
Ø 1.50 MIN
R 0.30 TYP
A0 = 6.50 ±0.10
B0 = 5.30 ±0.10
K0 = 1.40 ±0.10
M0138-01
NOTES: 1. 10-sprocket hole-pitch cumulative tolerance ±0.2
2. Camber not to exceed 1mm in 100mm, noncumulative over 250mm
3. Material: black static-dissipative polystyrene
4. All dimensions are in mm (unless otherwise specified)
5. A0 and B0 measured on a plane 0.3mm above the bottom of the pocket
spacer
REVISION HISTORY
Changes from Original (December 2010) to Revision A
Page
•
Changed VGS in the Abs Max Ratings table From: +20/-12V To: ±20V ............................................................................... 1
•
Changed from +20/-12V to 20V ............................................................................................................................................ 2
Changes from Revision A (July 2011) to Revision B
Page
•
Changed Figure 10, Maximum Safe Operating Area ........................................................................................................... 5
8
Copyright © 2010–2012, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
6-Feb-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
CSD17506Q5A
ACTIVE
Package Type Package Pins Package
Drawing
Qty
VSONP
DQJ
8
2500
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Pb-Free (RoHS
Exempt)
SN
Level-1-260C-UNLIM
Op Temp (°C)
Device Marking
(4/5)
-55 to 150
CSD17506
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
