CSD17579Q3A

Sample & Buy Product Folder Support & Community Tools & Software Technical Documents CSD17579Q3A SLPS527A – SEPTEMBER 2014 – REVISED JANUARY 2016 CSD17579Q3A 30 V N-Channel NexFET™ Power MOSFETs 1 Features • • • • • • • • Product Summary Low Qg and Qgd Low RDS(on) Low Thermal Resistance Avalanche Rated Pb-Free RoHS Compliant Halogen Free SON 3.3 mm × 3.3 mm Plastic Package 1 TA = 25°C 30 V Qg Gate Charge Total (4.5 V) 5.3 nC Qgd Gate Charge Gate-to-Drain RDS(on) Drain-to-Source On-Resistance VGS(th) Threshold Voltage mΩ VGS = 10 V 8.7 mΩ 1.5 V DEVICE MEDIA QTY PACKAGE SHIP 13-Inch Reel 2500 CSD17579Q3AT 7-Inch Reel 250 SON 3.3 × 3.3 mm Plastic Package Tape and Reel (1) For all available packages, see the orderable addendum at the end of the data sheet. Absolute Maximum Ratings This 30 V, 8.7 mΩ, SON 3.3 mm × 3.3 mm NexFET™ power MOSFET is designed to minimize losses in power conversion applications. Top View TA = 25°C VALUE UNIT VDS Drain-to-Source Voltage 30 V VGS Gate-to-Source Voltage ±20 V Continuous Drain Current (Package limited) 20 Continuous Drain Current (Silicon limited), TC = 25°C 39 ID 8 1 (1) D IDM S 2 7 D S 3 6 D PD D G nC 11.8 CSD17579Q3A 3 Description S 1.2 VGS = 4.5 V . Ordering Information(1) Point-of-Load Synchronous Buck Converter for Applications in Networking, Telecom, and Computing Systems Optimized for Control FET Applications • UNIT Drain-to-Source Voltage 2 Applications • TYPICAL VALUE VDS 5 4 D P0093-01 Continuous Drain Current 11 Pulsed Drain Current(2) 106 Power Dissipation(1) 2.5 Power Dissipation, TC = 25°C 29 A A W TJ, Tstg Operating Junction Temperature, Storage Temperature –55 to 150 °C EAS Avalanche Energy, single pulse ID = 17 A, L = 0.1 mH, RG = 25 Ω 14 mJ (1) Typical RθJA = 50°C/W on a 1 inch2, 2 oz. Cu pad on a 0.06 inch thick FR4 PCB. (2) Max RθJC = 5.4 °C/W, pulse duration ≤100 μs, duty cycle ≤1% . . RDS(on) vs VGS Gate Charge 10 TC = 25°C, I D = 8 A TC = 125°C, I D = 8 A 27 VGS - Gate-to-Source Voltage (V) RDS(on) - On-State Resistance (m:) 30 24 21 18 15 12 9 6 3 0 ID = 8 A, VDS = 15 V 9 8 7 6 5 4 3 2 1 0 0 2 4 6 8 10 12 14 16 VGS - Gate-to-Source Voltage (V) 18 20 D007 0 2 4 6 8 Qg - Gate Charge (nC) 10 12 D004 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. CSD17579Q3A SLPS527A – SEPTEMBER 2014 – REVISED JANUARY 2016 www.ti.com Table of Contents 1 2 3 4 5 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Specifications......................................................... 1 1 1 2 3 5.1 Electrical Characteristics.......................................... 3 5.2 Thermal Information .................................................. 3 5.3 Typical MOSFET Characteristics.............................. 4 6 Device and Documentation Support.................... 7 6.1 6.2 6.3 6.4 7 Community Resources.............................................. Trademarks ............................................................... Electrostatic Discharge Caution ................................ Glossary .................................................................... 7 7 7 7 Mechanical, Packaging, and Orderable Information ............................................................. 8 7.1 7.2 7.3 7.4 Q3A Package Dimensions ........................................ 8 Q3A Recommended PCB Pattern ............................ 9 Q3A Recommended Stencil Pattern ......................... 9 Q3A Tape and Reel Information ............................. 10 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Original (September 2014) to Revision A Page • Updated Power Dissipation value in Absolute Maximum Ratings table. ............................................................................... 1 • Added Community Resources section .................................................................................................................................. 7 • Updated Package Dimensions drawing.................................................................................................................................. 8 • Updated PCB drawing. .......................................................................................................................................................... 9 • Updated Stencil Pattern drawing. .......................................................................................................................................... 9 2 Submit Documentation Feedback Copyright © 2014–2016, Texas Instruments Incorporated Product Folder Links: CSD17579Q3A CSD17579Q3A www.ti.com SLPS527A – SEPTEMBER 2014 – REVISED JANUARY 2016 5 Specifications 5.1 Electrical Characteristics (TA = 25°C unless otherwise stated) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT STATIC CHARACTERISTICS BVDSS Drain-to-source voltage VGS = 0 V, ID = 250 μA IDSS Drain-to-source leakage current VGS = 0 V, VDS = 24 V 1 μA IGSS Gate-to-source leakage current VDS = 0 V, VGS = 20 V 100 nA VGS(th) Gate-to-source threshold voltage VDS = VGS, ID = 250 μA RDS(on) Drain-to-source on-resistance gfs Transconductance 30 1.1 V 1.5 1.9 V VGS = 4.5 V, ID = 8 A 11.8 14.2 mΩ VGS = 10 V, ID = 8 A 8.7 10.2 mΩ VDS = 3 V, ID = 8 A 37 S DYNAMIC CHARACTERISTICS Ciss Input capacitance Coss Output capacitance Crss Reverse transfer capacitance RG Series gate resistance Qg Gate charge total (4.5 V) Qg Gate charge total (10 V) Qgd Gate charge gate-to-drain Qgs Gate charge gate-to-source Qg(th) Gate charge at Vth Qoss Output charge td(on) VGS = 0 V, VDS = 15 V, ƒ = 1 MHz VDS = 15 V, ID = 8 A 768 998 pF 93 121 pF 38 49 pF 1.9 3.8 Ω 5.3 6.9 nC 11.5 15.0 nC 1.2 nC 2.2 nC 1.1 nC 3.0 nC Turn on delay time 2 ns tr Rise time 5 ns td(off) Turn off delay time 11 ns tf Fall time 1 ns VDS = 15 V, VGS = 0 V VDS = 15 V, VGS = 10 V, IDS = 8 A, RG = 0 Ω DIODE CHARACTERISTICS VSD Diode forward voltage Qrr Reverse recovery charge trr Reverse recovery time ISD = 8 A, VGS = 0 V 0.8 VDS= 15 V, IF = 8 A, di/dt = 300 A/μs 3.4 1.0 nC V 5 ns 5.2 Thermal Information (TA = 25°C unless otherwise stated) THERMAL METRIC (1) RθJC Junction-to-case thermal resistance RθJA Junction-to-ambient thermal resistance (1) (2) (1) (2) MIN TYP MAX UNIT 5.4 °C/W 60 °C/W RθJC is determined with the device mounted on a 1 inch2 (6.45 cm2), 2 oz. (0.071 mm thick) Cu pad on a 1.5 inch × 1.5 inch (3.81 cm × 3.81 cm), 0.06 inch (1.52 mm) thick FR4 PCB. RθJC is specified by design, whereas RθJA is determined by the user’s board design. Device mounted on FR4 material with 1 inch2 (6.45 cm2), 2 oz. (0.071 mm thick) Cu. Submit Documentation Feedback Copyright © 2014–2016, Texas Instruments Incorporated Product Folder Links: CSD17579Q3A 3 CSD17579Q3A SLPS527A – SEPTEMBER 2014 – REVISED JANUARY 2016 GATE www.ti.com GATE Source Source Max RθJA = 60°C/W when mounted on 1 inch2 (6.45 cm2) of 2 oz. (0.071 mm thick) Cu. Max RθJA = 145°C/W when mounted on a minimum pad area of 2 oz. (0.071 mm thick) Cu. DRAIN DRAIN M0161-02 M0161-01 5.3 Typical MOSFET Characteristics (TA = 25°C unless otherwise stated) Figure 1. Transient Thermal Impedance 4 Submit Documentation Feedback Copyright © 2014–2016, Texas Instruments Incorporated Product Folder Links: CSD17579Q3A CSD17579Q3A www.ti.com SLPS527A – SEPTEMBER 2014 – REVISED JANUARY 2016 Typical MOSFET Characteristics (continued) (TA = 25°C unless otherwise stated) 50 IDS - Drain-to-Source Current (A) IDS - Drain-to-Source Current (A) 50 40 30 20 10 VGS = 4.5 V VGS = 6 V VGS = 10 V 45 40 35 30 25 20 15 10 TC = 125°C TC = 25°C TC = -55°C 5 0 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 VDS - Drain-to-Source Voltage (V) 0.9 1 0 0.5 1 1.5 2 2.5 3 VGS - Gate-to-Source Voltage (V) D002 3.5 4 D003 VDS = 5 V Figure 2. Saturation Characteristics Figure 3. Transfer Characteristics 10000 Ciss = Cgd + Cgs Coss = Cds + Cgd Crss = Cgd 9 8 C - Capacitance (pF) VGS - Gate-to-Source Voltage (V) 10 7 6 5 4 3 1000 100 2 1 10 0 0 2 4 6 8 Qg - Gate Charge (nC) ID = 8 A 10 0 12 3 6 D004 Figure 4. Gate Charge 30 D005 Figure 5. Capacitance 30 RDS(on) - On-State Resistance (m:) VGS(th) - Threshold Voltage (V) 27 VDS = 15 V 2.1 1.9 1.7 1.5 1.3 1.1 0.9 0.7 -75 9 12 15 18 21 24 VDS - Drain-to-Source Voltage (V) TC = 25°C, I D = 8 A TC = 125°C, I D = 8 A 27 24 21 18 15 12 9 6 3 0 -50 -25 0 25 50 75 100 TC - Case Temperature (°C) 125 150 175 0 2 D006 4 6 8 10 12 14 16 VGS - Gate-to-Source Voltage (V) 18 20 D007 ID = 250 µA Figure 6. Threshold Voltage vs Temperature Figure 7. On-State Resistance vs Gate-to-Source Voltage Submit Documentation Feedback Copyright © 2014–2016, Texas Instruments Incorporated Product Folder Links: CSD17579Q3A 5 CSD17579Q3A SLPS527A – SEPTEMBER 2014 – REVISED JANUARY 2016 www.ti.com Typical MOSFET Characteristics (continued) (TA = 25°C unless otherwise stated) 100 1.6 VGS = 4.5 V VGS = 10 V ISD - Source-to-Drain Current (A) Normalized On-State Resistance 1.8 1.4 1.2 1 0.8 0.6 -75 TC = 25°C TC = 125°C 10 1 0.1 0.01 0.001 0.0001 -50 -25 0 25 50 75 100 TC - Case Temperature (°C) 125 150 0 175 0.1 0.2 D008 0.3 0.4 0.5 0.6 0.7 0.8 VSD - Source-to-Drain Voltage (V) 0.9 1 D010 D009 ID = 8 A Figure 8. Normalized On-State Resistance vs Temperature Figure 9. Typical Diode Forward Voltage IAV - Peak Avalanche Current (A) IDS - Drain-to-Source Current (A) 1000 100 10 1 DC 10 ms 1 ms 0.1 0.1 100 µs 10 µs 1 10 VDS - Drain-to-Source Voltage (V) 100 D010 100 70 50 TC = 25qC TC = 125qC 30 20 10 7 5 3 2 1 0.01 0.02 0.03 0.050.07 0.1 0.2 0.3 TAV - Time in Avalanche (ms) 0.5 0.7 1 D011 Single Pulse, Max RθJC = 5.4°C/W Figure 10. Maximum Safe Operating Area Figure 11. Single Pulse Unclamped Inductive Switching IDS - Drain-to-Source Current (A) 25 20 15 10 5 0 -50 -25 0 25 50 75 100 125 TC - Case Temperature (°C) 150 175 D012 Figure 12. Maximum Drain Current vs Temperature 6 Submit Documentation Feedback Copyright © 2014–2016, Texas Instruments Incorporated Product Folder Links: CSD17579Q3A CSD17579Q3A www.ti.com SLPS527A – SEPTEMBER 2014 – REVISED JANUARY 2016 6 Device and Documentation Support 6.1 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support. 6.2 Trademarks NexFET, E2E are trademarks of Texas Instruments. All other trademarks are the property of their respective owners. 6.3 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 6.4 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. Submit Documentation Feedback Copyright © 2014–2016, Texas Instruments Incorporated Product Folder Links: CSD17579Q3A 7 CSD17579Q3A SLPS527A – SEPTEMBER 2014 – REVISED JANUARY 2016 www.ti.com 7 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 7.1 Q3A Package Dimensions 3.1 2.9 B A PIN 1 INDEX AREA 3.25 3.05 2X 0.15 MAX 2X (0.2) 3.5 TYP 3.1 C 0.9 MAX SEATING PLANE 0.05 0.00 (0.2) 1.74±0.1 4X 0.52 0.32 0.565±0.1 (0.15) TYP EXPOSED THERMAL PAD NOTE 3 4 5 9 2X 1.95 2.45±0.1 0.65 TYP 8 1 4X 0.55 0.25 8X 4X 1.45 2X NOTE 4 0.35 0.25 0.1 0.05 C B C A 4222499/A 12/2015 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance. 4. Metalized features are supplier options and may not be on the package. 5. All dimensions do not include mold flash or protrusions. 8 Submit Documentation Feedback Copyright © 2014–2016, Texas Instruments Incorporated Product Folder Links: CSD17579Q3A CSD17579Q3A www.ti.com SLPS527A – SEPTEMBER 2014 – REVISED JANUARY 2016 7.2 Q3A Recommended PCB Pattern (1.775) PKG 0.05 MIN ALL SIDES (0.635) TYP (0.56) 4X (0.3) 4X (0.6) 1 8 4X (0.3) (R0.05) TYP (0.975) TYP 9 SYMM (2.45) 3X (0.65) 3X (0.65) 4 5 (R0.05) TYP SOLDER MASK OPENING (0.207) METAL UNDER SOLDER MASK (0.245) ( 0.2) VIA TYP (0.905) TYP (1.55) LAND PATTERN EXAMPLE 1. This package is designed to be soldered to a thermal pad on the board. For more information, see QFN/SON PCB Attachment application report, SLUA271. 2. Vias are optional depending on application, refer to device data sheet. If some or all are implemented, recommended via locations are shown. For recommended circuit layout for PCB designs, see application note SLPA005 – Reducing Ringing Through PCB Layout Techniques. 7.3 Q3A Recommended Stencil Pattern (0.905) PKG 8X (0.6) (0.208) SOLDER MASK EDGE 1 8 8X (0.3) (0.663) SYMM 9 (1.325) 6X (0.65) 4X 1.125 5 4 (R0.05) TYP 4X 0.705 METAL TYP (3.1) 1. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. Submit Documentation Feedback Copyright © 2014–2016, Texas Instruments Incorporated Product Folder Links: CSD17579Q3A 9 CSD17579Q3A SLPS527A – SEPTEMBER 2014 – REVISED JANUARY 2016 www.ti.com 1.75 ±0.10 7.4 Q3A Tape and Reel Information 4.00 ±0.10 (See Note 1) Ø 1.50 +0.10 –0.00 1.30 3.60 5.50 ±0.05 12.00 +0.30 –0.10 8.00 ±0.10 2.00 ±0.05 3.60 M0144-01 Notes: 1. 10-sprocket hole-pitch cumulative tolerance ±0.2 2. Camber not to exceed 1 mm in 100 mm, noncumulative over 250 mm 3. Material: black static-dissipative polystyrene 4. All dimensions are in mm, unless otherwise specified. 5. Thickness: 0.30 ±0.05 mm 6. MSL1 260°C (IR and convection) PbF-reflow compatible 10 Submit Documentation Feedback Copyright © 2014–2016, Texas Instruments Incorporated Product Folder Links: CSD17579Q3A PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) CSD17579Q3A ACTIVE VSONP DNH 8 2500 RoHS & Green SN Level-1-260C-UNLIM CSD17579Q3AT ACTIVE VSONP DNH 8 250 RoHS & Green SN Level-1-260C-UNLIM 17579 -55 to 150 17579 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of