CSD17579Q5A

Sample & Buy Product Folder Support & Community Tools & Software Technical Documents CSD17579Q5A SLPS524 – MARCH 2015 CSD17579Q5A 30 V N-Channel NexFET™ Power MOSFETs 1 Features • • • • • • • • Product Summary Low Qg and Qgd Low RDS(on) Low Thermal Resistance Avalanche Rated Pb-Free Terminal Plating RoHS Compliant Halogen Free SON 5 mm × 6 mm Plastic Package 1 TA = 25°C 30 V Qg Gate Charge Total (4.5 V) 5.4 nC Qgd Gate Charge Gate-to-Drain RDS(on) Drain-to-Source On-Resistance VGS(th) Threshold Voltage mΩ VGS = 10 V 8.4 mΩ 1.5 V Device Media Qty Package Ship 13-Inch Reel 2500 CSD17579Q5AT 7-Inch Reel 250 SON 5 x 6 mm Plastic Package Tape and Reel (1) For all available packages, see the orderable addendum at the end of the data sheet. Absolute Maximum Ratings This 30 V, 8.4 mΩ, SON 5 mm x 6mm NexFET™ power MOSFET is designed to minimize losses in power conversion applications. Top View TA = 25°C VALUE UNIT VDS Drain-to-Source Voltage 30 V VGS Gate-to-Source Voltage ±20 V Continuous Drain Current (Package limited) 25 Continuous Drain Current (Silicon limited), TC = 25°C 46 ID 8 1 (1) S 2 7 D S 3 6 D 14 Pulsed Drain Current(2) 105 Power Dissipation(1) 3.1 Power Dissipation, TC = 25°C 36 TJ, Tstg Operating Junction and Storage Temperature Range –55 to 150 °C EAS Avalanche Energy, single pulse ID = 17 A, L = 0.1 mH 14.5 mJ PD D 5 4 D P0093-01 A Continuous Drain Current D IDM G nC 11.6 CSD17579Q5A 3 Description S 1.2 VGS = 4.5 V . Ordering Information(1) Point-of-Load Synchronous Buck Converter for Applications in Networking, Telecom, and Computing Systems Optimized for Control FET Applications • UNIT Drain-to-Source Voltage 2 Applications • TYPICAL VALUE VDS A W (1) Typical RθJA = 40°C/W on a 1 inch2, 2 oz. Cu pad on a 0.06 inch thick FR4 PCB. (2) Max RθJC = 4.3 °C/W, pulse duration ≤100 μs, duty cycle ≤1% . . RDS(on) vs VGS Gate Charge 10 TC = 25° C, I D = 8 A TC = 125° C, I D = 8 A 24 VGS - Gate-to-Source Voltage (V) RDS(on) - On-State Resistance (m:) 28 20 16 12 8 4 0 ID = 8 A 9 VDS = 15 V 8 7 6 5 4 3 2 1 0 0 2 4 6 8 10 12 14 16 VGS - Gate-to-Source Voltage (V) 18 20 D007 0 1.5 3 4.5 6 7.5 Qg - Gate Charge (nC) 9 10.5 12 D004 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. CSD17579Q5A SLPS524 – MARCH 2015 www.ti.com Table of Contents 1 2 3 4 5 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Specifications......................................................... 6.1 Trademarks ............................................................... 7 6.2 Electrostatic Discharge Caution ................................ 7 6.3 Glossary .................................................................... 7 1 1 1 2 3 7 7.1 7.2 7.3 7.4 5.1 Electrical Characteristics........................................... 3 5.2 Thermal Information .................................................. 3 5.3 Typical MOSFET Characteristics.............................. 4 6 Mechanical, Packaging, and Orderable Information ............................................................. 8 Device and Documentation Support.................... 7 Q5A Package Dimensions ........................................ 8 Recommended PCB Pattern..................................... 9 Recommended Stencil Opening ............................. 10 Q5A Tape and Reel Information ............................. 10 4 Revision History 2 DATE REVISION NOTES March 2015 * Initial release. Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: CSD17579Q5A CSD17579Q5A www.ti.com SLPS524 – MARCH 2015 5 Specifications 5.1 Electrical Characteristics (TA = 25°C unless otherwise stated) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT STATIC CHARACTERISTICS BVDSS Drain-to-Source Voltage VGS = 0 V, ID = 250 μA IDSS Drain-to-Source Leakage Current VGS = 0 V, VDS = 24 V 1 μA IGSS Gate-to-Source Leakage Current VDS = 0 V, VGS = 20 V 100 nA VGS(th) Gate-to-Source Threshold Voltage VDS = VGS, ID = 250 μA RDS(on) Drain-to-Source On-Resistance gƒs Transconductance 30 1.0 V 1.5 2.0 V VGS = 4.5 V, ID = 8 A 11.6 13.3 mΩ VGS = 10 V, ID = 8 A 8.4 9.7 mΩ VDS = 3 V, ID = 8 A 36 S DYNAMIC CHARACTERISTICS Ciss Input Capacitance Coss Output Capacitance Crss Reverse Transfer Capacitance RG Series Gate Resistance Qg Gate Charge Total (4.5 V) Qg Gate Charge Total (10 V) Qgd Gate Charge Gate-to-Drain Qgs Gate Charge Gate-to-Source Qg(th) Gate Charge at Vth Qoss Output Charge td(on) VGS = 0 V, VDS = 15 V, ƒ = 1 MHz VDS = 15 V, ID = 8 A 796 1030 pF 95 124 pF 40 52 pF 1.9 3.8 Ω 5.4 7 nC 11.6 15.1 nC 1.2 nC 2.3 nC 1.1 nC 2.9 nC Turn On Delay Time 3 ns tr Rise Time 7 ns td(off) Turn Off Delay Time 13 ns tƒ Fall Time 1 ns VDS = 15 V, VGS = 0 V VDS = 15 V, VGS = 10 V, IDS = 8 A, RG = 0 Ω DIODE CHARACTERISTICS VSD Diode Forward Voltage Qrr Reverse Recovery Charge trr Reverse Recovery Time ISD = 8 A, VGS = 0 V 0.8 VDS= 15 V, IF = 8 A, di/dt = 300 A/μs 4.2 1.0 nC V 5.7 ns 5.2 Thermal Information (TA = 25°C unless otherwise stated) THERMAL METRIC (1) RθJC Junction-to-Case Thermal Resistance RθJA Junction-to-Ambient Thermal Resistance (1) (2) (1) (2) MIN TYP MAX 4.3 50 UNIT °C/W RθJC is determined with the device mounted on a 1 inch2 (6.45 cm2), 2 oz. (0.071 mm thick) Cu pad on a 1.5 inches × 1.5 inches (3.81 cm × 3.81 cm), 0.06 inch (1.52 mm) thick FR4 PCB. RθJC is specified by design, whereas RθJA is determined by the user’s board design. Device mounted on FR4 material with 1 inch2 (6.45-cm2), 2 oz. (0.071 mm thick) Cu. Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: CSD17579Q5A 3 CSD17579Q5A SLPS524 – MARCH 2015 GATE www.ti.com GATE Source N-Chan 5x6 QFN TTA MIN Rev3 N-Chan 5x6 QFN TTA MAX Rev3 Max RθJA = 50°C/W when mounted on 1 inch2 (6.45 cm2) of 2 oz. (0.071 mm thick) Cu. Source Max RθJA = 140°C/W when mounted on a minimum pad area of 2 oz. (0.071 mm thick) Cu. DRAIN DRAIN M0137-02 M0137-01 5.3 Typical MOSFET Characteristics (TA = 25°C unless otherwise stated) Figure 1. Transient Thermal Impedance 4 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: CSD17579Q5A CSD17579Q5A www.ti.com SLPS524 – MARCH 2015 Typical MOSFET Characteristics (continued) (TA = 25°C unless otherwise stated) 50 45 IDS - Drain-to-Source Current (A) IDS - Drain-to-Source Current (A) 50 40 35 30 25 20 15 10 VGS = 4.5 V VGS = 6 V VGS = 10 V 5 0 0 0.05 0.1 0.15 0.2 0.25 0.3 VDS - Drain-to-Source Voltage (V) 0.35 TC = 125° C TC = 25° C TC = -55° C 40 30 20 10 0 1.25 0.4 1.75 2.25 2.75 3.25 VGS - Gate-to-Source Voltage (V) D002 3.75 D003 VDS = 5 V Figure 2. Saturation Characteristics Figure 3. Transfer Characteristics 10000 Ciss = Cgd + Cgs Coss = Cds + Cgd Crss = Cgd 9 8 C - Capacitance (pF) VGS - Gate-to-Source Voltage (V) 10 7 6 5 4 3 1000 100 2 1 10 0 0 1.5 3 4.5 6 7.5 Qg - Gate Charge (nC) ID = 8 A 9 10.5 0 12 5 D004 30 D005 Figure 5. Capacitance 28 RDS(on) - On-State Resistance (m:) 2.1 VGS(th) - Threshold Voltage (V) 25 VDS = 15 V Figure 4. Gate Charge 1.9 1.7 1.5 1.3 1.1 0.9 0.7 -75 10 15 20 VDS - Drain-to-Source Voltage (V) TC = 25° C, I D = 8 A TC = 125° C, I D = 8 A 24 20 16 12 8 4 0 -50 -25 0 25 50 75 100 TC - Case Temperature (° C) 125 150 175 0 2 D006 4 6 8 10 12 14 16 VGS - Gate-to-Source Voltage (V) 18 20 D007 ID = 250 µA Figure 6. Threshold Voltage vs Temperature Figure 7. On-State Resistance vs Gate-to-Source Voltage Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: CSD17579Q5A 5 CSD17579Q5A SLPS524 – MARCH 2015 www.ti.com Typical MOSFET Characteristics (continued) (TA = 25°C unless otherwise stated) 100 1.8 VGS = 4.5 V VGS = 10 V ISD - Source-to-Drain Current (A) Normalized On-State Resistance 2 1.6 1.4 1.2 1 0.8 0.6 0.4 -75 TC = 25° C TC = 125° C 10 1 0.1 0.01 0.001 0.0001 -50 -25 0 25 50 75 100 TC - Case Temperature (° C) 125 150 175 0 0.2 D008 0.4 0.6 0.8 VSD - Source-to-Drain Voltage (V) 1 D009 ID = 8 A Figure 8. Normalized On-State Resistance vs Temperature Figure 9. Typical Diode Forward Voltage 100 IAV - Peak Avalanche Current (A) IDS - Drain-to-Source Current (A) 1000 100 10 1 DC 10 ms 1 ms 0.1 0.1 100 µs 10 µs 1 10 VDS - Drain-to-Source Voltage (V) 100 TC = 25q C TC = 125q C 10 1 0.01 0.1 TAV - Time in Avalanche (ms) D010 0.7 D011 Single Pulse, Max RθJC = 4.3°C/W Figure 10. Maximum Safe Operating Area Figure 11. Single Pulse Unclamped Inductive Switching IDS - Drain-to-Source Current (A) 30 25 20 15 10 5 0 -50 -25 0 25 50 75 100 125 TC - Case Temperature (° C) 150 175 D012 Figure 12. Maximum Drain Current vs Temperature 6 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: CSD17579Q5A CSD17579Q5A www.ti.com SLPS524 – MARCH 2015 6 Device and Documentation Support 6.1 Trademarks NexFET is a trademark of Texas Instruments. All other trademarks are the property of their respective owners. 6.2 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 6.3 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: CSD17579Q5A 7 CSD17579Q5A SLPS524 – MARCH 2015 www.ti.com 7 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 2 3 4 5 4 5 6 3 6 7 2 7 1 8 1 DIM 8 8 7.1 Q5A Package Dimensions MILLIMETERS MIN NOM MAX A 0.90 1.00 1.10 b 0.33 0.41 0.51 c 0.20 0.25 0.34 D1 4.80 4.90 5.00 D2 3.61 3.81 4.02 E 5.90 6.00 6.10 E1 5.70 5.75 5.80 E2 3.38 3.58 3.78 E3 3.03 3.13 3.23 e 1.17 1.27 1.37 e1 0.27 0.37 0.47 e2 0.15 0.25 0.35 H 0.41 0.56 0.71 K 1.10 L 0.51 0.61 0.71 L1 0.06 0.13 0.20 θ 0° Submit Documentation Feedback 12° Copyright © 2015, Texas Instruments Incorporated Product Folder Links: CSD17579Q5A CSD17579Q5A www.ti.com SLPS524 – MARCH 2015 7.2 Recommended PCB Pattern F1 F7 F3 8 1 F2 F11 F5 F9 5 4 F6 F8 F4 F10 M0139-01 DIM MILLIMETERS INCHES MIN MAX MIN MAX F1 6.205 6.305 0.244 0.248 F2 4.46 4.56 0.176 0.18 F3 4.46 4.56 0.176 0.18 F4 0.65 0.7 0.026 0.028 F5 0.62 0.67 0.024 0.026 F6 0.63 0.68 0.025 0.027 F7 0.7 0.8 0.028 0.031 F8 0.65 0.7 0.026 0.028 F9 0.62 0.67 0.024 0.026 F10 4.9 5 0.193 0.197 F11 4.46 4.56 0.176 0.18 For recommended circuit layout for PCB designs, see application note SLPA005 – Reducing Ringing Through PCB Layout Techniques. Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: CSD17579Q5A 9 CSD17579Q5A SLPS524 – MARCH 2015 www.ti.com 7.3 Recommended Stencil Opening (0.020) 8x 0.500 (0.020) 0.500 5 4 0.500 (0.020) 8x 1.585 (0.062) 1.235 (0.049) (0.024) 0.620 (0.170) 4.310 0.385 (0.015) 1.270 (0.050) 1 8 1.570 (0.062) 4x 0.615 (0.024) 1.105 (0.044) 3.020 (0.119) K0 4.00 ±0.10 (See Note 1) 0.30 ±0.05 2.00 ±0.05 +0.10 –0.00 12.00 ±0.30 Ø 1.50 1.75 ±0.10 7.4 Q5A Tape and Reel Information 5.50 ±0.05 B0 R 0.30 MAX A0 8.00 ±0.10 Ø 1.50 MIN A0 = 6.50 ±0.10 B0 = 5.30 ±0.10 K0 = 1.40 ±0.10 R 0.30 TYP M0138-01 Notes: 1. 10-sprocket hole-pitch cumulative tolerance ±0.2 2. Camber not to exceed 1 mm in 100 mm, noncumulative over 250 mm 3. Material: black static-dissipative polystyrene 4. All dimensions are in mm (unless otherwise specified) 5. A0 and B0 measured on a plane 0.3 mm above the bottom of the pocket 10 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated Product Folder Links: CSD17579Q5A PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) CSD17579Q5A ACTIVE VSONP DQJ 8 2500 RoHS-Exempt & Green SN Level-1-260C-UNLIM CSD17579Q5AT ACTIVE VSONP DQJ 8 250 RoHS-Exempt & Green SN Level-1-260C-UNLIM CSD17579 -55 to 150 CSD17579 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of