CSD18503Q5AT

Sample & Buy Product Folder Support & Community Tools & Software Technical Documents Reference Design CSD18503Q5A SLPS358C – JUNE 2012 – REVISED JUNE 2015 CSD18503Q5A 40 V N-Channel NexFET™ Power MOSFET 1 Features • • • • • • • • 1 Product Summary Ultra-Low Qg and Qgd Low Thermal Resistance Avalanche Rated Logic Level Pb Free Terminal Plating RoHS Compliant Halogen Free SON 5 mm × 6 mm Plastic Package TA = 25°C 40 V Qg Gate charge total (4.5 V) 13 nC Qgd Gate charge gate-to-drain RDS(on) Drain-to-source on-resistance VGS(th) Threshold voltage DEVICE 8 1 7 2 mΩ V MEDIA 250 7-Inch Reel PACKAGE SHIP SON 5 mm × 6 mm Plastic Package Tape and Reel VALUE UNIT Drain-to-source voltage 40 V VGS Gate-to-source voltage ±20 V Continuous drain current (package limited), TC = 25°C 100 Continuous drain current (silicon limited), TC = 25°C 121 D IDM D 6 D 5 D D P0093-01 Continuous drain current, TA = 25°C(1) 19 Pulsed drain current, TA = 25°C(2) 321 Power dissipation(1) 3.1 Power dissipation, TC = 25°C 120 TJ, Tstg Operating junction, Storage temperature EAS Avalanche energy, single pulse ID = 56 A, L = 0.1 mH, RG = 25 Ω A A W –55 to 150 °C 157 mJ (1) Typical RθJA = 40°C/W on a 1 inch2, 2 oz. Cu pad on a 0.06 inch thick FR4 PCB. (2) Max RθJC = 1.3°C/W, pulse duration ≤100 μs, duty cycle ≤1% Text added for spacing RDS(on) vs VGS Gate Charge 14 10 TC = 25°C, I D = 22 A TC = 125°C, I D = 22 A 12 VGS - Gate-to-Source Voltage (V) RDS(on) - On-State Resistance (m:) 3.4 VDS PD 4 VGS = 10 V Absolute Maximum Ratings ID G mΩ TA = 25°C Top View 3 nC 4.7 (1) For all available packages, see the orderable addendum at the end of the data sheet. This 40 V, 3.4 mΩ, 5 x 6 mm SON NexFET™ power MOSFET is designed to minimize losses in power conversion applications. S 4.3 VGS = 4.5 V 1.8 2500 13-Inch Reel CSD18503Q5AT 3 Description S QTY CSD18503Q5A DC-DC Conversion Secondary Side Synchronous Rectifier Battery Motor Control S UNIT Drain-to-source voltage Ordering Information(1) 2 Applications • • • TYPICAL VALUE VDS 10 8 6 4 2 ID = 22 A VDS = 20 V 8 6 4 2 0 0 0 2 4 6 8 10 12 14 16 VGS - Gate-to-Source Voltage (V) 18 20 D007 0 5 10 15 20 Qg - Gate Charge (nC) 25 30 D004 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. CSD18503Q5A SLPS358C – JUNE 2012 – REVISED JUNE 2015 www.ti.com Table of Contents 1 2 3 4 5 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Specifications......................................................... 1 1 1 2 3 5.1 Electrical Characteristics........................................... 3 5.2 Thermal Information .................................................. 3 5.3 Typical MOSFET Characteristics.............................. 4 6 Device and Documentation Support.................... 7 6.1 6.2 6.3 6.4 7 Community Resources.............................................. Trademarks ............................................................... Electrostatic Discharge Caution ................................ Glossary .................................................................... 7 7 7 7 Mechanical, Packaging, and Orderable Information ............................................................. 8 7.1 7.2 7.3 7.4 Q5A Package Dimensions ........................................ 8 Recommended PCB Pattern..................................... 9 Recommended Stencil Opening ............................. 10 Q5A Tape and Reel Information ............................. 10 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision B (November 2012) to Revision C Page • Added part number to title ..................................................................................................................................................... 1 • Added 7-inch reel to Ordering Information table ................................................................................................................... 1 • Updated Continuous Drain Current ....................................................................................................................................... 1 • Updated Pulsed Drain Current .............................................................................................................................................. 1 • Updated pulsed current conditions ........................................................................................................................................ 1 • Updated Max RθJC ................................................................................................................................................................. 3 • Updated Figure 1 ................................................................................................................................................................... 4 • Updated SOA in Figure 10 .................................................................................................................................................... 6 • Updated Figure 12 ................................................................................................................................................................. 6 • Added Community Resources ............................................................................................................................................... 7 • Updated package dimensions ............................................................................................................................................... 8 • Added Recommended Stencil Opening ............................................................................................................................... 10 Changes from Revision A (October 2012) to Revision B Page • Added line for max power dissipation with case temperature held to 25° C .......................................................................... 1 • Changed the RDS(on) vs VGS and GATE CHARGE graphs...................................................................................................... 1 • Changed Max RθJA = 121°C/W To: Max RθJA = 125°C/W ...................................................................................................... 4 • Changed the Typical MOSFET Characteristics section ......................................................................................................... 4 Changes from Original (June 2012) to Revision A Page • Changed the Transconductance TYP value From: 127 S To: 100 S..................................................................................... 3 • Changed the Turn On and Turn Off Delay Time, Rise andFall Time Test Conditions From: IDS = 22 A, RG = 2 Ω To: IDS = 22 A, RG = 0 Ω ............................................................................................................................................................... 3 • Changed the Qrr Reverse Recovery Charge TYP value From: 22 nC To: 52 nC .................................................................. 3 2 Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: CSD18503Q5A CSD18503Q5A www.ti.com SLPS358C – JUNE 2012 – REVISED JUNE 2015 5 Specifications 5.1 Electrical Characteristics (TA = 25°C unless otherwise stated) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT STATIC CHARACTERISTICS BVDSS Drain to-source voltage VGS = 0 V, ID = 250 μA IDSS Drain-to-source leakage current VGS = 0 V, VDS = 32 V 1 μA IGSS Gate-to-source leakage current VDS = 0 V, VGS = 20 V 100 nA VGS(th) Gate-to-source threshold voltage VDS = VGS, ID = 250 μA RDS(on) Drain-to-source on-resistance gfs Transconductance 40 1.5 V 1.8 2.3 V VGS = 4.5 V, ID = 22 A 4.7 6.2 mΩ VGS = 10 V, ID = 22 A 3.4 4.3 mΩ VDS = 20 V, ID = 22 A 100 S DYNAMIC CHARACTERISTICS Ciss Input capacitance Coss Output capacitance Crss Reverse transfer capacitance RG Series gate resistance Qg Gate charge total (4.5 V) 13 16 Qg Gate charge total (10 V) 27 32 Qgd Gate charge gate-to-drain Qgs Gate charge gate-to-source Qg(th) Gate charge at Vth Qoss Output charge td(on) VGS = 0 V, VDS = 20 V, ƒ = 1 MHz VDS = 20 V, ID = 22 A 2200 2640 pF 510 612 pF 13 16 pF 1.2 2.4 Ω nC 4.3 nC 4.5 nC 3.8 nC 30 nC Turn on delay time 4.5 ns tr Rise time 8.8 ns td(off) Turn off delay time 15 ns tf Fall time 2.6 ns VDS = 20 V, VGS = 0 V VDS = 20 V, VGS = 10 V, IDS = 22 A, RG = 0 DIODE CHARACTERISTICS VSD Diode forward voltage Qrr Reverse recovery charge trr Reverse recovery time ISD = 22 A, VGS = 0 V 0.8 VDS= 20 V, IF = 22 A, di/dt = 300 A/μs 52 1 nC V 37 ns 5.2 Thermal Information (TA = 25°C unless otherwise stated) MAX UNIT RθJC Junction-to-case thermal resistance (1) THERMAL METRIC 1.3 °C/W RθJA Junction-to-ambient thermal resistance (1) (2) 50 °C/W (1) (2) MIN TYP RθJC is determined with the device mounted on a 1 inch2 (6.45 cm2), 2 oz. (0.071 mm thick) Cu pad on a 1.5 inch × 1.5 inch (3.81 cm × 3.81 cm), 0.06 inch (1.52 mm) thick FR4 PCB. RθJC is specified by design, whereas RθJA is determined by the user’s board design. Device mounted on FR4 material with 1 inch2 (6.45 cm2), 2 oz. (0.071 mm thick) Cu. Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: CSD18503Q5A 3 CSD18503Q5A SLPS358C – JUNE 2012 – REVISED JUNE 2015 GATE www.ti.com GATE Source N-Chan 5x6 QFN TTA MIN Rev3 N-Chan 5x6 QFN TTA MAX Rev3 Max RθJA = 50°C/W when mounted on 1 inch2 (6.45 cm2) of 2 oz. (0.071 mm thick) Cu. Source Max RθJA = 125°C/W when mounted on a minimum pad area of 2 oz. (0.071 mm thick) Cu. DRAIN DRAIN M0137-02 M0137-01 5.3 Typical MOSFET Characteristics (TA = 25°C unless otherwise stated) Figure 1. Transient Thermal Impedance 4 Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: CSD18503Q5A CSD18503Q5A www.ti.com SLPS358C – JUNE 2012 – REVISED JUNE 2015 Typical MOSFET Characteristics (continued) (TA = 25°C unless otherwise stated) 100 80 60 40 20 VGS = 4.5 V VGS = 6.5 V VGS = 10 V TC = 125°C TC = 25°C TC = -55°C 90 IDS - Drain-to-Source Current (A) IDS - Drain-to-Source Current (A) 100 80 70 60 50 40 30 20 10 0 0 0 0.1 0.2 0.3 0.4 0.5 0.6 VDS - Drain-to-Source Voltage (V) 0.7 0.8 1 1.5 2 2.5 3 3.5 4 VGS - Gate-to-Source Voltage (V) D002 4.5 5 D003 VDS = 5 V Figure 2. Saturation Characteristics Figure 3. Transfer Characteristics 20000 Ciss = Cgd + Cgs Coss = Cds + Cgd Crss = Cgd 10000 8 C - Capacitance (pF) VGS - Gate-to-Source Voltage (V) 10 6 4 1000 100 2 0 10 0 5 10 15 20 Qg - Gate Charge (nC) ID = 22 A 25 30 0 5 10 15 20 25 30 VDS - Drain-to-Source Voltage (V) D004 Figure 4. Gate Charge D005 Figure 5. Capacitance 14 RDS(on) - On-State Resistance (m:) VGS(th) - Threshold Voltage (V) 40 VDS = 20 V 2.4 2.2 2 1.8 1.6 1.4 1.2 1 0.8 -75 35 TC = 25°C, I D = 22 A TC = 125°C, I D = 22 A 12 10 8 6 4 2 0 -50 -25 0 25 50 75 100 TC - Case Temperature (°C) 125 150 175 0 2 D006 4 6 8 10 12 14 16 VGS - Gate-to-Source Voltage (V) 18 20 D007 ID = 250 µA Figure 6. Threshold Voltage vs Temperature Figure 7. On-State Resistance vs Gate-to-Source Voltage Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: CSD18503Q5A 5 CSD18503Q5A SLPS358C – JUNE 2012 – REVISED JUNE 2015 www.ti.com Typical MOSFET Characteristics (continued) (TA = 25°C unless otherwise stated) 100 2 VGS = 4.5 V VGS = 10 V ISD - Source-to-Drain Current (A) Normalized On-State Resistance 2.2 1.8 1.6 1.4 1.2 1 0.8 0.6 0.4 -75 TC = 25°C TC = 125°C 10 1 0.1 0.01 0.001 0.0001 -50 -25 0 25 50 75 100 TC - Case Temperature (°C) 125 150 0 175 0.2 D008 0.4 0.6 0.8 VSD - Source-to-Drain Voltage (V) 1 D009 ID = 22 A Figure 8. Normalized On-State Resistance vs Temperature Figure 9. Typical Diode Forward Voltage 100 1000 100 10 1 100 ms 10 ms 0.1 0.1 TC = 25q C TC = 125q C IAV - Peak Avalanche Current (A) IDS - Drain-to-Source Current (A) 5000 1 ms 100 µs 1 10 VDS - Drain-to-Source Voltage (V) 100 10 0.01 0.1 TAV - Time in Avalanche (ms) D010 1 D011 Single Pulse, Max RθJC = 1.3°C/W Figure 10. Maximum Safe Operating Area Figure 11. Single Pulse Unclamped Inductive Switching IDS - Drain-to-Source Current (A) 120 100 80 60 40 20 0 -50 -25 0 25 50 75 100 125 TC - Case Temperature (°C) 150 175 D012 Figure 12. Maximum Drain Current vs Temperature 6 Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: CSD18503Q5A CSD18503Q5A www.ti.com SLPS358C – JUNE 2012 – REVISED JUNE 2015 6 Device and Documentation Support 6.1 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support. 6.2 Trademarks NexFET, E2E are trademarks of Texas Instruments. All other trademarks are the property of their respective owners. 6.3 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 6.4 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: CSD18503Q5A 7 CSD18503Q5A SLPS358C – JUNE 2012 – REVISED JUNE 2015 www.ti.com 7 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 2 3 4 5 4 5 6 3 6 7 2 7 1 8 1 DIM 8 8 7.1 Q5A Package Dimensions MILLIMETERS MIN NOM MAX A 0.90 1.00 1.10 b 0.33 0.41 0.51 c 0.20 0.25 0.34 D1 4.80 4.90 5.00 D2 3.61 3.81 4.02 E 5.90 6.00 6.10 E1 5.70 5.75 5.80 E2 3.38 3.58 3.78 E3 3.03 3.13 3.23 e 1.17 1.27 1.37 e1 0.27 0.37 0.47 e2 0.15 0.25 0.35 H 0.41 0.56 0.71 K 1.10 L 0.51 0.61 0.71 L1 0.06 0.13 0.20 θ 0° Submit Documentation Feedback 12° Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: CSD18503Q5A CSD18503Q5A www.ti.com SLPS358C – JUNE 2012 – REVISED JUNE 2015 7.2 Recommended PCB Pattern F1 F7 F3 8 1 F2 F11 F5 F9 5 4 F6 F8 F4 F10 M0139-01 DIM MILLIMETERS INCHES MIN MAX MIN MAX F1 6.205 6.305 0.244 0.248 F2 4.46 4.56 0.176 0.18 F3 4.46 4.56 0.176 0.18 F4 0.65 0.7 0.026 0.028 F5 0.62 0.67 0.024 0.026 F6 0.63 0.68 0.025 0.027 F7 0.7 0.8 0.028 0.031 F8 0.65 0.7 0.026 0.028 F9 0.62 0.67 0.024 0.026 F10 4.9 5 0.193 0.197 F11 4.46 4.56 0.176 0.18 For recommended circuit layout for PCB designs, see application note SLPA005 – Reducing Ringing Through PCB Layout Techniques. Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: CSD18503Q5A 9 CSD18503Q5A SLPS358C – JUNE 2012 – REVISED JUNE 2015 www.ti.com 7.3 Recommended Stencil Opening (0.020) 8x 0.500 (0.020) 0.500 5 4 0.500 (0.020) 8x 1.585 (0.062) 1.235 (0.049) (0.024) 0.620 (0.170) 4.310 0.385 (0.015) 1.270 (0.050) 1 8 1.570 (0.062) 4x 0.615 (0.024) 1.105 (0.044) 3.020 (0.119) K0 4.00 ±0.10 (See Note 1) 0.30 ±0.05 2.00 ±0.05 +0.10 –0.00 12.00 ±0.30 Ø 1.50 1.75 ±0.10 7.4 Q5A Tape and Reel Information 5.50 ±0.05 B0 R 0.30 MAX A0 8.00 ±0.10 Ø 1.50 MIN R 0.30 TYP A0 = 6.50 ±0.10 B0 = 5.30 ±0.10 K0 = 1.40 ±0.10 M0138-01 Notes: 1. 10-sprocket hole-pitch cumulative tolerance ±0.2 2. Camber not to exceed 1 mm in 100 mm, noncumulative over 250 mm 3. Material: black static-dissipative polystyrene 4. All dimensions are in mm (unless otherwise specified) 5. A0 and B0 measured on a plane 0.3 mm above the bottom of the pocket 10 Submit Documentation Feedback Copyright © 2012–2015, Texas Instruments Incorporated Product Folder Links: CSD18503Q5A PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) CSD18503Q5A ACTIVE VSONP DQJ 8 2500 RoHS-Exempt & Green SN Level-1-260C-UNLIM -55 to 150 CSD18503 CSD18503Q5AT ACTIVE VSONP DQJ 8 250 RoHS-Exempt & Green SN Level-1-260C-UNLIM -55 to 150 CSD18503 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of