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CSD18511KTT
SLPS684 – JULY 2017
CSD18511KTT 40-V N-Channel NexFET™ Power MOSFET
1 Features
•
•
•
•
•
•
•
•
1
Product Summary
Low Qg and Qgd
Low RDS(ON)
Low-Thermal Resistance
Avalanche Rated
Lead-Free Terminal Plating
RoHS Compliant
Halogen Free
D2PAK Plastic Package
TA = 25°C
UNIT
Drain-to-Source Voltage
40
V
Qg
Gate Charge Total (10 V)
63.9
nC
Qgd
Gate Charge Gate-to-Drain
RDS(on)
Drain-to-Source On-Resistance
VGS(th)
Threshold Voltage
9.7
nC
VGS = 4.5 V
3.2
VGS = 10 V
2.1
mΩ
1.8
V
Device Information(1)
2 Applications
•
•
TYPICAL VALUE
VDS
Secondary Side Synchronous Rectifier
Motor Control
DEVICE
QTY
CSD18511KTT
500
CSD18511KTTT
50
MEDIA
PACKAGE
SHIP
13-Inch Reel
D2PAK
Plastic Package
Tape
and
Reel
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
3 Description
This 40-V, 2.1-mΩ, D2PAK (TO-263) NexFET™
power MOSFET is designed to minimize losses in
power conversion applications.
Drain (Pin 2)
Absolute Maximum Ratings
TA = 25°C
VALUE
UNIT
VDS
Drain-to-Source Voltage
40
V
VGS
Gate-to-Source Voltage
±20
V
Continuous Drain Current (Package Limited)
110
Continuous Drain Current (Silicon Limited),
TC = 25°C
194
Continuous Drain Current (Silicon Limited),
TC = 100°C
137
IDM
Pulsed Drain Current(1)
400
A
PD
Power Dissipation
188
W
TJ,
Tstg
Operating Junction,
Storage Temperature
–55 to 175
°C
EAS
Avalanche Energy, Single Pulse
ID = 56 A, L = 0.1 mH, RG = 25 Ω
156
mJ
ID
Gate
(Pin 1)
Source (Pin 3)
A
(1) Max RθJC = 0.8°C/W, pulse duration ≤ 100 μs, duty cycle ≤
1%.
RDS(on) vs VGS
Gate Charge
10
TC = 25° C, I D = 100 A
TC = 125° C, I D = 100 A
9
VGS - Gate-to-Source Voltage (V)
RDS(on) - On-State Resistance (m:)
10
8
7
6
5
4
3
2
1
0
ID = 100 A
9 VDS = 20 V
8
7
6
5
4
3
2
1
0
0
2
4
6
8
10
12
14
16
VGS - Gate-to-Source Voltage (V)
18
20
D007
0
10
20
30
40
50
Qg - Gate Charge (nC)
60
70
D004
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
CSD18511KTT
SLPS684 – JULY 2017
www.ti.com
Table of Contents
1
2
3
4
5
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Specifications.........................................................
6.2
6.3
6.4
6.5
1
1
1
2
3
7
5.1 Electrical Characteristics........................................... 3
5.2 Thermal Information .................................................. 3
5.3 Typical MOSFET Characteristics.............................. 4
6
Community Resources..............................................
Trademarks ...............................................................
Electrostatic Discharge Caution ................................
Glossary ....................................................................
7
7
7
7
Mechanical, Packaging, and Orderable
Information ............................................................. 8
7.1 KTT Package Dimensions ........................................ 8
7.2 Recommended PCB Pattern..................................... 9
7.3 Recommended Stencil Opening (0.125 mm Stencil
Thickness).................................................................. 9
Device and Documentation Support.................... 7
6.1 Receiving Notification of Documentation Updates.... 7
4 Revision History
2
DATE
REVISION
NOTES
July 2017
*
Initial release.
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SLPS684 – JULY 2017
5 Specifications
5.1 Electrical Characteristics
TA = 25°C (unless otherwise stated)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
STATIC CHARACTERISTICS
BVDSS
Drain-to-source voltage
VGS = 0 V, ID = 250 μA
IDSS
Drain-to-source leakage current
VGS = 0 V, VDS = 32 V
1
μA
IGSS
Gate-to-source leakage current
VDS = 0 V, VGS = 20 V
100
nA
VGS(th)
Gate-to-source threshold voltage
VDS = VGS, ID = 250 μA
V
RDS(on)
Drain-to-source on-resistance
gfs
Transconductance
40
1.5
V
1.8
2.4
VGS = 4.5 V, ID = 100 A
3.2
4.2
VGS = 10 V, ID = 100 A
2.1
2.6
VDS = 4 V, ID = 100 A
249
mΩ
S
DYNAMIC CHARACTERISTICS
Ciss
Input capacitance
Coss
Output capacitance
4570
5940
pF
454
591
pF
Crss
RG
Reverse transfer capacitance
235
306
pF
Series gate resistance
0.9
1.8
Qg
Gate charge total (4.5 V)
31
nC
Qg
Gate charge total (10 V)
Qgd
Gate charge gate-to-drain
Qgs
Gate charge gate-to-source
Qg(th)
Gate charge at Vth
Qoss
Output charge
td(on)
VGS = 0 V, VDS = 20 V, ƒ = 1 MHz
VDS = 20 V, ID = 100 A
Ω
64
nC
9.7
nC
17.9
nC
7.4
nC
20.7
nC
Turnon delay time
8
ns
tr
Rise time
6
ns
td(off)
Turnoff delay time
17
ns
tf
Fall time
3
ns
VDS = 20 V, VGS = 0 V
VDS = 20 V, VGS = 10 V,
IDS = 100 A, RG = 0 Ω
DIODE CHARACTERISTICS
VSD
Diode forward voltage
Qrr
Reverse recovery charge
trr
Reverse recovery time
ISD = 100 A, VGS = 0 V
0.9
VDS= 20 V, IF = 100 A,
di/dt = 300 A/μs
62
1.0
nC
V
31
ns
5.2 Thermal Information
TA = 25°C (unless otherwise stated)
MAX
UNIT
RθJC
Junction-to-case thermal resistance
THERMAL METRIC
MIN
TYP
0.8
°C/W
RθJA
Junction-to-ambient thermal resistance
62
°C/W
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SLPS684 – JULY 2017
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5.3 Typical MOSFET Characteristics
TA = 25°C (unless otherwise stated)
200
200
175
175
IDS - Drain-to-Source Current (A)
IDS - Drain-to-Source Current (A)
Figure 1. Transient Thermal Impedance
150
125
100
75
50
VGS = 4.5 V
VGS = 8 V
VGS = 10 V
25
0
TC = 125° C
TC = 25° C
TC = -55° C
150
125
100
75
50
25
0
0
0.1
0.2
0.3 0.4 0.5 0.6 0.7 0.8
VDS - Drain-to-Source Voltage (V)
0.9
1
1
1.5
D002
2
2.5
3
3.5
4
VGS - Gate-to-Source Voltage (V)
4.5
5
D003
VDS = 5 V
Figure 2. Saturation Characteristics
4
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Figure 3. Transfer Characteristics
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SLPS684 – JULY 2017
Typical MOSFET Characteristics (continued)
TA = 25°C (unless otherwise stated)
10000
9
8
C - Capacitance (pF)
VGS - Gate-to-Source Voltage (V)
10
7
6
5
4
3
Ciss = Cgd + Cgs
Coss = Cds + Cgd
Crss = Cgd
1000
2
1
100
0
0
10
20
30
40
50
Qg - Gate Charge (nC)
VDS = 20 V
60
0
70
10
20
30
VDS - Drain-to-Source Voltage (V)
D004
Figure 5. Capacitance
2.6
10
2.4
9
RDS(on) - On-State Resistance (m:)
VGS(th) - Threshold Voltage (V)
D005
ID = 100 A
Figure 4. Gate Charge
2.2
2
1.8
1.6
1.4
1.2
1
0.8
0.6
-75
40
TC = 25° C, I D = 100 A
TC = 125° C, I D = 100 A
8
7
6
5
4
3
2
1
0
-50
-25
0
0
25 50 75 100 125 150 175 200
TC - Case Temperature (qC)
D006
2
4
6
8
10
12
14
16
VGS - Gate-to-Source Voltage (V)
18
20
D007
ID = 250 µA
Figure 7. On-State Resistance vs Gate-to-Source Voltage
Figure 6. Threshold Voltage vs Temperature
100
2
VGS = 4.5 V
VGS = 10 V
ISD - Source-to-Drain Current (A)
Normalized On-State Resistance
2.2
1.8
1.6
1.4
1.2
1
0.8
0.6
0.4
-75
TC = 25qC
TC = 125qC
10
1
0.1
0.01
0.001
0.0001
-50
-25
0
25 50 75 100 125 150 175 200
TC - Case Temperature (° C)
D008
0
0.2
0.4
0.6
0.8
VSD - Source-to-Drain Voltage (V)
1
D009
ID = 100 A
Figure 8. Normalized On-State Resistance vs Temperature
Figure 9. Typical Diode Forward Voltage
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Typical MOSFET Characteristics (continued)
TA = 25°C (unless otherwise stated)
100
IAV - Peak Avalanche Current (A)
IDS - Drain-to-Source Current (A)
1000
100
10
1
DC
10 ms
0.1
0.1
1 ms
100 µs
10 µs
1
10
VDS - Drain-to-Source Voltage (V)
100
10
TC = 25q C
TC = 125q C
1
0.01
0.1
TAV - Time in Avalanche (ms)
D010
1
D011
Single pulse, max RθJC = 0.8°C/W
Figure 10. Maximum Safe Operating Area
Figure 11. Single Pulse Unclamped Inductive Switching
IDS - Drain-to-Source Current (A)
150
125
100
75
50
25
0
-50
-25
0
25
50
75 100 125
TC - Case Temperature (qC)
150
175
200
D012
Max RθJC = 0.8°C/W
Figure 12. Maximum Drain Current vs Temperature
6
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SLPS684 – JULY 2017
6 Device and Documentation Support
6.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
6.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
6.3 Trademarks
NexFET, E2E, PowerPAD are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
6.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
6.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
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SLPS684 – JULY 2017
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7 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
7.1 KTT Package Dimensions
15.5
14.7
9.25
9.05
A
B
3
10.26
10.06
2X 5.08
2
1
2[.0]X 1.36
1.23
2[.0]X 0.9
0.77
1.75 MAX
0.25
C A
B
1.4
1.17
0.47
0.34
C
4.7
4.4
8
0
0.25
0
1.32
1.22
2.6
2
0.25
GAGE PLANE
7.48
7.08
8°
0°
8.55
8.15
0.25
GAGE PLANE
NOTE 3
2.6
2
OPTIONAL LEAD FORM
EXPOSED
THERMAL PAD
Notes:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning
and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Features may not exist and shape may vary per different assembly sites.
Table 1. Pin Configuration
POSITION
8
DESIGNATION
Pin 1
Gate
Pin 2 / Tab
Drain
Pin 3
Source
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SLPS684 – JULY 2017
7.2 Recommended PCB Pattern
PKG
(3.4)
(6.9)
(R0.05) TYP
PKG
SYMM
(5.08)
(8.55)
2X (1.05)
2X (3.82)
(7.48)
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
0.07 MIN
ALL AROUND
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
For recommended circuit layout for PCB designs, see Reducing Ringing Through PCB Layout Techniques
(SLPA005).
7.3 Recommended Stencil Opening (0.125 mm Stencil Thickness)
(1.17) TYP
42X (0.97)
(0.48) TYP
2X (3.82)
2X (1.05)
42X (0.95)
(R0.05) TYP
(1.15) TYP
SYMM
(5.08)
(6.9)
PKG
Notes:
1. This package is designed to be soldered to a thermal pad on the board. See PowerPAD™ Thermally
Enhanced Package (SLMA002) and PowerPAD™
Made Easy (SLMA004) for more information.
2. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525
may have alternate design recommendations.
3. Board assembly site may have different recommendations for stencil design.
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
(3)
Device Marking
(4/5)
(6)
CSD18511KTT
ACTIVE
DDPAK/
TO-263
KTT
3
500
RoHS-Exempt
& Green
SN
Level-2-260C-1 YEAR
-55 to 175
CSD18511KTT
CSD18511KTTT
ACTIVE
DDPAK/
TO-263
KTT
3
50
RoHS-Exempt
& Green
SN
Level-2-260C-1 YEAR
-55 to 175
CSD18511KTT
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of