CSD18541F5T

CSD18541F5 SLPS571B – MAY 2016 – REVISED FEBRUARY 2022 CSD18541F5 60-V N-Channel FemtoFET™ MOSFET Product Summary 1 Features • • • • • • • TA = 25°C Low on-resistance Ultra-low Qg and Qgd Ultra-small footprint – 1.53 mm × 0.77 mm Low profile – 0.36-mm height Integrated ESD protection diode Lead and halogen free RoHS compliant UNIT VDS Drain-to-Source Voltage 60 V Qg Gate Charge Total (10 V) 11 nC Qgd Gate Charge Gate-to-Drain 1.6 RDS(on) Drain-to-Source On-Resistance VGS(th) Threshold Voltage nC VGS = 4.5 V 57 VGS = 10 V 54 mΩ 1.75 V Device Information 2 Applications • • TYPICAL VALUE Optimized for industrial load switch applications Optimized for general purpose switching applications DEVICE QTY CSD18541F5 3000 CSD18541F5T 250 MEDIA PACKAGE SHIP 7-Inch Reel Femto 1.53-mm × 0.77-mm SMD Lead Less Tape and Reel 1. For all available packages, see the orderable addendum at the end of the data sheet. 3 Description Absolute Maximum Ratings This 54-mΩ, 60-V, N-Channel FemtoFET™ MOSFET technology is designed and optimized to minimize the footprint in many space constrained industrial load switch applications. This technology is capable of replacing standard small signal MOSFETs while providing a significant reduction in footprint size. 0.36 mm TA = 25°C VALUE UNIT VDS Drain-to-Source Voltage 60 V VGS Gate-to-Source Voltage ±20 V ID Continuous Drain Current 2.2 A IDM Pulsed Drain Current (1)(2) 21 A PD Power Dissipation 500 mW TJ, Tstg Operating Junction Temperature, Storage Temperature –55 to 150 °C EAS Avalanche Energy, Single Pulse ID = 12.8 A, L = 0.1 mH, RG = 25 Ω 8.2 mJ G 0.77 mm 1.53 mm S Typical Part Dimensions D Top View An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. CSD18541F5 www.ti.com SLPS571B – MAY 2016 – REVISED FEBRUARY 2022 Table of Contents 1 Features............................................................................1 2 Applications..................................................................... 1 3 Description.......................................................................1 4 Revision History.............................................................. 2 5 Specifications.................................................................. 3 5.1 Electrical Characteristics.............................................3 5.2 Thermal Information....................................................3 5.3 Typical MOSFET Characteristics................................ 3 6 Device and Documentation Support..............................7 6.1 Receiving Notification of Documentation Updates......7 6.2 Community Resources................................................7 6.3 Trademarks................................................................. 7 7 Mechanical, Packaging, and Orderable Information.... 8 7.1 Mechanical Dimensions.............................................. 8 7.2 Recommended Minimum PCB Layout........................9 7.3 Recommended Stencil Pattern................................... 9 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision A (December 2016) to Revision B (February 2022) Page • Changed ultra-low profile bullet from 0.35 mm to 0.36 mm in height................................................................. 1 • Updated ultra-low profile image height from 0.35 mm to 0.36 mm..................................................................... 1 • Changed ultra-low profile image height from 0.35 mm to 0.36 mm.................................................................... 8 • Added FemtoFET Surface Mount Guide note.................................................................................................... 9 Changes from Revision * (May 2016) to Revision A (August 2017) Page • Added the Section 6.1 section to Section 6 ....................................................................................................... 7 • Added Table 7-1 to the Section 7.1 section........................................................................................................ 8 • Updated the Section 7.2 .................................................................................................................................... 9 • Updated the Section 7.3 .................................................................................................................................... 9 2 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: CSD18541F5 CSD18541F5 www.ti.com SLPS571B – MAY 2016 – REVISED FEBRUARY 2022 5 Specifications 5.1 Electrical Characteristics TA = 25°C (unless otherwise stated) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT STATIC CHARACTERISTICS BVDSS Drain-to-source voltage VGS = 0 V, IDS = 250 μA IDSS Drain-to-source leakage current VGS = 0 V, VDS = 48 V IGSS Gate-to-source leakage current VDS = 0 V, VGS = 20 V VGS(th) Gate-to-source threshold voltage VDS = VGS, IDS = 250 μA RDS(on) Drain-to-source on-resistance gfs Transconductance 60 V 1 µA 10 µA 1.75 2.2 V VGS = 4.5 V, IDS = 1 A 57 75 VGS = 10 V, IDS = 1 A 54 65 VDS = 6 V, IDS = 1 A 7.7 1.4 mΩ S DYNAMIC CHARACTERISTICS Ciss Input capacitance 598 Coss Output capacitance Crss Reverse transfer capacitance RG Series gate resistance Qg Gate charge total (10 V) Qgd Gate charge gate-to-drain Qgs Gate charge gate-to-source Qg(th) Gate charge at Vth Qoss Output charge td(on) tr td(off) Turnoff delay time tf Fall time VGS = 0 V, VDS = 30 V, ƒ = 1 MHz 777 pF 47 61 pF 8.1 10.5 pF 1200 1600 Ω 11 14 nC 1.6 nC 1.5 nC 0.8 nC 3.2 nC Turnon delay time 572 ns Rise time 540 ns 1076 ns 496 ns VDS = 30 V, IDS = 1 A VDS = 30 V, VGS = 0 V VDS = 30 V, VGS = 4.5 V, IDS = 1 A, RG = 0 Ω DIODE CHARACTERISTICS VSD Diode forward voltage ISD = 1 A, VGS = 0 V 0.8 1 V 5.2 Thermal Information TA = 25°C (unless otherwise stated) THERMAL METRIC RθJA (1) (2) MIN TYP resistance(1) 85 Junction-to-ambient thermal resistance(2) 245 Junction-to-ambient thermal MAX UNIT °C/W Device mounted on FR4 material with 1-in2 (6.45-cm2), 2-oz (0.071-mm) thick Cu. Device mounted on FR4 material with minimum Cu mounting area. 5.3 Typical MOSFET Characteristics TA = 25°C (unless otherwise stated) Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: CSD18541F5 3 CSD18541F5 www.ti.com SLPS571B – MAY 2016 – REVISED FEBRUARY 2022 Figure 5-1. Transient Thermal Impedance 10 VGS = 4.5 V VGS = 6.0 V VGS = 10 V 8 7 IDS - Drain-to-Source Current (A) IDS - Drain-to-Source Current (A) 9 6 5 4 3 2 1 TC = 125°C TC = 25°C TC = -55°C 9 8 7 6 5 4 3 2 1 0 0 0 0.1 0.2 0.3 0.4 0.5 VDS - Drain-to-Source Voltage (V) 0.6 0 0.5 D002 Figure 5-2. Saturation Characteristics 1 1.5 2 2.5 3 VGS - Gate-to-Source Voltage (V) 3.5 4 D003 VDS = 5 V Figure 5-3. Transfer Characteristics 4 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: CSD18541F5 CSD18541F5 www.ti.com SLPS571B – MAY 2016 – REVISED FEBRUARY 2022 1000 9 8 C - Capacitance (pF) VGS - Gate-to-Source Voltage (V) 10 7 6 5 4 3 100 10 2 Ciss = Cgd + Cgs Coss = Cds + Cgd Crss = Cgd 1 1 0 0 2 4 6 8 Qg - Gate Charge (nC) ID = 1 A 10 0 12 6 D004 12 18 24 30 36 42 48 VDS - Drain-to-Source Voltage (V) 54 60 D005 Figure 5-5. Capacitance VDS = 30 V Figure 5-4. Gate Charge 120 RDS(on) - On-State Resistance (m:) VGS(th) - Threshold Voltage (V) 2.2 2.05 1.9 1.75 1.6 1.45 1.3 1.15 1 -75 -50 -25 0 25 50 75 100 TC - Case Temperature (°C) 125 150 80 70 60 50 0 2 4 6 8 10 12 14 16 VGS - Gate-to-Source Voltage (V) 18 20 D007 Figure 5-7. On-State Resistance vs Gate-to-Source Voltage 1.8 100 VGS = 4.5 V VGS = 10 V ISD - Source-To-Drain Current (A) Normalized On-State Resistance 90 D006 Figure 5-6. Threshold Voltage vs Temperature 1.4 1.2 1 0.8 0.6 -75 100 40 175 ID = 250 µA 1.6 TC = 25°C, ID = 1 A TC = 125°C, ID = 1 A 110 TC = 25qC TC = 125qC 10 1 0.1 0.01 0.001 0.0001 0 -50 -25 0 25 50 75 100 TC - Case Temperature (qC) 125 150 175 D008 ID = 1 A 0.2 0.4 0.6 0.8 VSD - Source-To-Drain Voltage (V) 1 D009 Figure 5-9. Typical Diode Forward Voltage Figure 5-8. Normalized On-State Resistance vs Temperature Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: CSD18541F5 5 CSD18541F5 www.ti.com SLPS571B – MAY 2016 – REVISED FEBRUARY 2022 100 IAV - Peak Avalanche Current (A) IDS - Drain-To-Source Current (A) 100 10 1 0.1 100 ms 10 ms 0.01 0.1 1 ms 100 µs 10 µs 1 10 VDS - Drain-To-Source Voltage (V) 100 TC = 25q C TC = 125q C 10 1 0.001 0.01 TAV - Time in Avalanche (ms) D010 Single pulse, typ RθJA = 245°C/W Figure 5-10. Maximum Safe Operating Area (SOA) 0.1 D011 Figure 5-11. Single Pulse Unclamped Inductive Switching IDS - Drain-to-Source Current (A) 3.5 3 2.5 2 1.5 1 0.5 0 -50 -25 0 25 50 75 100 125 TA - Ambient Temperature (°C) 150 175 D012 Figure 5-12. Maximum Drain Current vs Temperature 6 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: CSD18541F5 CSD18541F5 www.ti.com SLPS571B – MAY 2016 – REVISED FEBRUARY 2022 6 Device and Documentation Support 6.1 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. 6.2 Community Resources 6.3 Trademarks FemtoFET™ is a trademark of Texas Instruments. All trademarks are the property of their respective owners. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: CSD18541F5 7 CSD18541F5 www.ti.com SLPS571B – MAY 2016 – REVISED FEBRUARY 2022 7 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 7.1 Mechanical Dimensions 0.77 0.69 A B PIN 1 INDEX AREA 1.53 1.45 C 0.36 MAX SEATING PLANE 3 0.5 (R0.05) TYP 1 1 3X 3X 0.40 0.38 0.16 0.14 0.015 TOP B A 4222132/A 06/2015 A. B. C. All linear dimensions are in millimeters (dimensions and tolerancing per AME T14.5M-1994). This drawing is subject to change without notice. This package is a PB-free solder land design. Table 7-1. Pin Configuration 8 POSITION DESIGNATION Pin 1 Gate Pin 2 Source Pin 3 Drain Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: CSD18541F5 YJK0003A PicoStar TM - 0.35 mm max height PicoStar TM CSD18541F5 www.ti.com SLPS571B – MAY 2016 – REVISED FEBRUARY 2022 7.2 Recommended Minimum PCB Layout 3X (0.39) (0.05) MIN ALL AROUND 1 (R0.05) TYP 3X (0.15) SYMM SOLDER MASK OPENING TYP (0.5) 3 YJK0003A EXAMPLE STENCIL DESIGN TM METAL UNDER PicoStar - 0.35 mm max height SOLDER MASK SYMM TYP A. B. PicoStar TM All dimensions are in millimeters. LAND PATTERN EXAMPLE SOLDER MASK DEFINED For more information, see FemtoFET Surface Mount Guide (SLRA003D). SCALE:50X 7.3 Recommended Stencil Pattern 3X (0.39) 1 3X (0.2) (R0.05) TYP 2X (0.15) SYMM (0.15) (0.525) 4222132/B 08/2016 NOTES: (continued) 3 4. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). SOLDER MASK EDGE SYMM TYP A. All dimensions are in millimeters. SOLDER PASTE EXAMPLE ON 0.075 - 0.1 mm THICK STENCIL SCALE:50X www.ti.com Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: CSD18541F5 9 PACKAGE OPTION ADDENDUM www.ti.com 11-Jan-2022 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) CSD18541F5 ACTIVE PICOSTAR YJK 3 3000 RoHS & Green NIAU Level-1-260C-UNLIM -55 to 150 1T CSD18541F5T ACTIVE PICOSTAR YJK 3 250 RoHS & Green NIAU Level-1-260C-UNLIM -55 to 150 1T (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of