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CSD18563Q5A
SLPS444C – JULY 2013 – REVISED JANUARY 2016
CSD18563Q5A 60 V N-Channel NexFET™ Power MOSFET
1 Features
•
•
•
•
•
•
•
•
•
1
Product Summary
Ultra-Low Qg and Qgd
Soft Body Diode for Reduced Ringing
Low Thermal Resistance
Avalanche Rated
Logic Level
Pb-Free Terminal Plating
RoHS Compliant
Halogen Free
SON 5 mm × 6 mm Plastic Package
TA = 25°C
Low-Side FET for Industrial Buck Converter
Secondary Side Synchronous Rectifier
Motor Control
60
V
Qg
Gate Charge Total (10 V)
15.0
nC
Qgd
Gate Charge Gate-to-Drain
RDS(on)
Drain-to-Source On-Resistance
VGS(th)
Threshold Voltage
2.9
8.6
mΩ
VGS = 10 V
5.7
mΩ
2.0
V
DEVICE
MEDIA
QTY
PACKAGE
SHIP
CSD18563Q5A
13-Inch Reel
2500
CSD18563Q5AT
7-Inch Reel
250
SON 5 × 6 mm
Plastic Package
Tape and
Reel
Absolute Maximum Ratings
This 5.7 mΩ, 60 V SON 5 mm × 6 mm NexFET™
power MOSFET was designed to pair with the
CSD18537NQ5A control FET and act as the sync
FET for a complete industrial buck converter chipset
solution.
TA = 25°C
VALUE
UNIT
VDS
Drain-to-Source Voltage
60
V
VGS
Gate-to-Source Voltage
±20
V
Continuous Drain Current (Package limited)
100
Continuous Drain Current (Silicon limited),
TC = 25°C
93
ID
(1)
Top View
IDM
8
1
D
S
2
7
D
S
3
6
D
PD
5
4
Continuous Drain Current
15
Pulsed Drain Current(2)
251
Power Dissipation(1)
3.2
Power Dissipation, TC = 25°C
116
A
A
W
TJ,
Tstg
Operating Junction Temperature,
Storage Temperature
–55 to 150
°C
EAS
Avalanche Energy, single pulse
ID = 54 A, L = 0.1 mH, RG = 25 Ω
146
mJ
(1) Typical RθJA = 40°C/W on a 1 inch2, 2 oz. Cu pad on a 0.06
inch thick FR4 PCB.
(2) Max RθJC = 1.3°C/W, pulse duration ≤100 μs, duty cycle ≤1%.
D
G
nC
VGS = 4.5 V
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
3 Description
S
UNIT
Drain-to-Source Voltage
.
Ordering Information(1)
2 Applications
•
•
•
TYPICAL VALUE
VDS
D
P0093-01
RDS(on) vs VGS
Gate Charge
10
TC = 25°C, I D = 18A
TC = 125°C, I D = 18A
21
VGS - Gate-to-Source Voltage (V)
RDS(on) - On-State Resistance (mΩ)
24
18
15
12
9
6
3
0
0
2
4
6
8
10
12
14
16
VGS - Gate-to- Source Voltage (V)
18
20
G001
ID = 18A
VDS = 30V
9
8
7
6
5
4
3
2
1
0
0
2
4
6
8
10
12
Qg - Gate Charge (nC)
14
16
G001
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
CSD18563Q5A
SLPS444C – JULY 2013 – REVISED JANUARY 2016
www.ti.com
Table of Contents
1
2
3
4
5
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Specifications.........................................................
1
1
1
2
3
5.1 Electrical Characteristics........................................... 3
5.2 Thermal Information .................................................. 3
5.3 Typical MOSFET Characteristics.............................. 4
6
Device and Documentation Support.................... 7
6.1
6.2
6.3
6.4
7
Community Resources..............................................
Trademarks ...............................................................
Electrostatic Discharge Caution ................................
Glossary ....................................................................
7
7
7
7
Mechanical, Packaging, and Orderable
Information ............................................................. 8
7.1
7.2
7.3
7.4
Q5A Package Dimensions ........................................ 8
Recommended PCB Pattern..................................... 9
Recommended Stencil Opening ............................. 10
Q5A Tape and Reel Information ............................. 10
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision B (January 2015) to Revision C
Page
•
Added "Soft Body Diode for Reduced Ringing" under Features ........................................................................................... 1
•
Added "Low-Side FET for Industrial Buck Converter" to Applications ................................................................................... 1
•
Updated the part description ................................................................................................................................................. 1
•
Added the Community Resources section ............................................................................................................................. 7
Changes from Revision A (January 2014) to Revision B
Page
•
Increased silicon limited continuous drain current to 93 A .................................................................................................... 1
•
Increased Pulsed Drain Current to 251 ................................................................................................................................. 1
•
Added line for max power dissipation with case temperature held to 25° C .......................................................................... 1
•
Updated pulsed current conditions ........................................................................................................................................ 1
•
Changed Figure 1 to normalized RθJC curve ......................................................................................................................... 4
•
Updated SOA in Figure 10 .................................................................................................................................................... 6
Changes from Original (July 2013) to Revision A
Page
•
Added more information to description................................................................................................................................... 1
•
Added small reel order number .............................................................................................................................................. 1
•
Removed TC = 25°C condition from continuous drain current (package limited) in Absolute Maximum Ratings table ......... 1
•
Changed Typ RθJA = 99°C/W to: RθJA = 100°C/W in Figure 1 ............................................................................................... 4
•
Added the Recommended Stencil Opening section............................................................................................................. 10
2
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SLPS444C – JULY 2013 – REVISED JANUARY 2016
5 Specifications
5.1 Electrical Characteristics
(TA = 25°C unless otherwise stated)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
STATIC CHARACTERISTICS
BVDSS
Drain-to-source voltage
VGS = 0 V, ID = 250 μA
IDSS
Drain-to-source leakage current
VGS = 0 V, VDS = 48 V
1
μA
IGSS
Gate-to-source leakage current
VDS = 0 V, VGS = 20 V
100
nA
VGS(th)
Gate-to-source threshold voltage
VDS = VGS, ID = 250 μA
RDS(on)
Drain-to-source on resistance
gfs
Transconductance
60
1.7
V
2.0
2.4
V
VGS = 4.5 V, ID = 18 A
8.6
10.8
mΩ
VGS = 10 V, ID = 18 A
5.7
6.8
mΩ
VDS = 30 V, ID = 18 A
60
S
DYNAMIC CHARACTERISTICS
Ciss
Input capacitance
Coss
Output capacitance
1150
1500
pF
280
364
pF
Crss
RG
Reverse transfer capacitance
3.9
5.1
pF
Series gate resistance
1.5
3.0
Ω
Qg
Gate charge total (4.5 V)
7.3
9.5
Qg
Gate charge total (10 V)
15
20
Qgd
Gate charge gate-to-drain
Qgs
Gate charge gate-to-source
Qg(th)
Gate charge at Vth
Qoss
Output charge
td(on)
VGS = 0 V, VDS = 30 V, ƒ = 1 MHz
VDS = 30 V, ID = 18 A
nC
2.9
nC
3.3
nC
2.3
nC
36
nC
Turn on delay time
3.2
ns
tr
Rise time
6.3
ns
td(off)
Turn off delay time
11.4
ns
tf
Fall time
1.7
ns
VDS = 30 V, VGS = 0 V
VDS = 30 V, VGS = 10 V, IDS = 18 A, RG = 0 Ω
DIODE CHARACTERISTICS
VSD
Diode forward voltage
Qrr
Reverse recovery charge
trr
Reverse recovery time
ISD = 18 A, VGS = 0 V
0.8
VDS= 30 V, IF = 18 A, di/dt = 300 A/μs
1
V
63
nC
49
ns
5.2 Thermal Information
(TA = 25°C unless otherwise stated)
THERMAL METRIC
MIN
TYP
MAX
RθJC
Junction-to-case thermal resistance (1)
1.3
RθJA
Junction-to-ambient thermal resistance (1) (2)
50
(1)
(2)
UNIT
°C/W
RθJC is determined with the device mounted on a 1 inch2 (6.45 cm2), 2 oz. (0.071 mm thick) Cu pad on a 1.5 inch × 1.5 inch (3.81 cm ×
3.81 cm), 0.06 inch (1.52 mm) thick FR4 PCB. RθJC is specified by design, whereas RθJA is determined by the user’s board design.
Device mounted on FR4 material with 1 inch2 (6.45 cm2), 2 oz. (0.071 mm thick) Cu.
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CSD18563Q5A
SLPS444C – JULY 2013 – REVISED JANUARY 2016
GATE
www.ti.com
GATE
Source
N-Chan 5x6 QFN TTA MIN Rev3
N-Chan 5x6 QFN TTA MAX Rev3
Max RθJA = 50°C/W
when mounted on
1 inch2 (6.45 cm2) of
2 oz. (0.071 mm thick)
Cu.
Source
Max RθJA = 125°C/W
when mounted on a
minimum pad area of
2 oz. (0.071 mm thick)
Cu.
DRAIN
DRAIN
M0137-02
M0137-01
5.3 Typical MOSFET Characteristics
(TA = 25°C unless otherwise stated)
Figure 1. Transient Thermal Impedance
4
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SLPS444C – JULY 2013 – REVISED JANUARY 2016
Typical MOSFET Characteristics (continued)
200
100
180
90
IDS - Drain-to-Source Current (A)
IDS - Drain-to-Source Current (A)
(TA = 25°C unless otherwise stated)
160
140
120
100
80
60
VGS =10V
VGS =6V
VGS =4.5V
40
20
0
0
1
2
3
4
VDS - Drain-to-Source Voltage (V)
80
70
60
50
40
30
TC = 125°C
TC = 25°C
TC = −55°C
20
10
0
5
VDS = 5V
0
1
Figure 2. Saturation Characteristics
C − Capacitance (pF)
VGS - Gate-to-Source Voltage (V)
ID = 18A
VDS = 30V
8
7
6
5
4
3
6
G001
Ciss = Cgd + Cgs
Coss = Cds + Cgd
Crss = Cgd
1000
100
10
2
1
0
0
2
4
6
8
10
12
Qg - Gate Charge (nC)
14
1
16
0
10
20
30
40
50
VDS - Drain-to-Source Voltage (V)
G001
Figure 4. Gate Charge
60
G001
Figure 5. Capacitance
2.6
24
RDS(on) - On-State Resistance (mΩ)
ID = 250uA
VGS(th) - Threshold Voltage (V)
5
Figure 3. Transfer Characteristics
20000
10000
10
9
2
3
4
VGS - Gate-to-Source Voltage (V)
G001
2.4
2.2
2
1.8
1.6
1.4
1.2
1
−75
−25
25
75
125
TC - Case Temperature (ºC)
Figure 6. Threshold Voltage vs Temperature
175
TC = 25°C, I D = 18A
TC = 125°C, I D = 18A
21
18
15
12
9
6
3
0
0
2
G001
4
6
8
10
12
14
16
VGS - Gate-to- Source Voltage (V)
18
20
G001
Figure 7. On-State Resistance vs Gate-To-Source Voltage
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Typical MOSFET Characteristics (continued)
(TA = 25°C unless otherwise stated)
2.1
100
VGS = 4.5V
VGS = 10V
ISD − Source-to-Drain Current (A)
Normalized On-State Resistance
2.4
1.8
1.5
1.2
0.9
0.6
TC = 25°C
TC = 125°C
10
1
0.1
0.01
0.001
ID =18A
0.3
−75
−25
25
75
125
TC - Case Temperature (ºC)
175
0.0001
0
Figure 8. Normalized On-State Resistance vs Temperature
10us
100us
1ms
10ms
DC
TC = 25ºC
TC = 125ºC
IAV - Peak Avalanche Current (A)
IDS - Drain-to-Source Current (A)
G001
100
100
10
1
Single Pulse
Max RthetaJC = 1.3ºC/W
0.1
0.1
1
Figure 9. Typical Diode Forward Voltage
5000
1000
0.2
0.4
0.6
0.8
VSD − Source-to-Drain Voltage (V)
G001
1
10
VDS - Drain-to-Source Voltage (V)
100
10
0.01
0.1
TAV - Time in Avalanche (mS)
G001
Figure 10. Maximum Safe Operating Area
1
G001
Figure 11. Single Pulse Unclamped Inductive Switching
IDS - Drain- to- Source Current (A)
120
100
80
60
40
20
0
−50
−25
0
25
50
75
100 125
TC - Case Temperature (ºC)
150
175
G001
Figure 12. Maximum Drain Current vs Temperature
6
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SLPS444C – JULY 2013 – REVISED JANUARY 2016
6 Device and Documentation Support
6.1 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
6.2 Trademarks
NexFET, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
6.3 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
6.4 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
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SLPS444C – JULY 2013 – REVISED JANUARY 2016
www.ti.com
7 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision
of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
2
3
4
5
4
5
6
3
6
7
2
7
1
8
1
DIM
8
8
7.1 Q5A Package Dimensions
MILLIMETERS
MIN
NOM
MAX
A
0.90
1.00
1.10
b
0.33
0.41
0.51
c
0.20
0.25
0.34
D1
4.80
4.90
5.00
D2
3.61
3.81
4.02
E
5.90
6.00
6.10
E1
5.70
5.75
5.80
E2
3.38
3.58
3.78
E3
3.03
3.13
3.23
e
1.17
1.27
1.37
e1
0.27
0.37
0.47
e2
0.15
0.25
0.35
H
0.41
0.56
0.71
K
1.10
L
0.51
0.61
0.71
L1
0.06
0.13
0.20
θ
0°
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SLPS444C – JULY 2013 – REVISED JANUARY 2016
7.2 Recommended PCB Pattern
F1
F7
F3
8
1
F2
F11
F5
F9
5
4
F6
F8
F4
F10
M0139-01
DIM
MILLIMETERS
INCHES
MIN
MAX
MIN
MAX
F1
6.205
6.305
0.244
0.248
F2
4.46
4.56
0.176
0.18
F3
4.46
4.56
0.176
0.18
F4
0.65
0.7
0.026
0.028
F5
0.62
0.67
0.024
0.026
F6
0.63
0.68
0.025
0.027
F7
0.7
0.8
0.028
0.031
F8
0.65
0.7
0.026
0.028
F9
0.62
0.67
0.024
0.026
F10
4.9
5
0.193
0.197
F11
4.46
4.56
0.176
0.18
For recommended circuit layout for PCB designs, see application note SLPA005 – Reducing Ringing Through
PCB Layout Techniques.
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7.3 Recommended Stencil Opening
(0.020) 8x
0.500
(0.020)
0.500
5
4
0.500
(0.020) 8x
1.585
(0.062)
1.235
(0.049)
(0.024)
0.620
(0.170) 4.310
0.385
(0.015)
1.270 (0.050)
1
8
1.570 (0.062)
4x
0.615
(0.024)
1.105
(0.044)
3.020
(0.119)
K0
4.00 ±0.10 (See Note 1)
0.30 ±0.05
2.00 ±0.05
+0.10
–0.00
12.00 ±0.30
Ø 1.50
1.75 ±0.10
7.4 Q5A Tape and Reel Information
5.50 ±0.05
B0
R 0.30 MAX
A0
8.00 ±0.10
Ø 1.50 MIN
R 0.30 TYP
A0 = 6.50 ±0.10
B0 = 5.30 ±0.10
K0 = 1.40 ±0.10
M0138-01
Notes:
1. 10-sprocket hole-pitch cumulative tolerance ±0.2
2. Camber not to exceed 1 mm in 100 mm, noncumulative over 250 mm
3. Material: black static-dissipative polystyrene
4. All dimensions are in mm (unless otherwise specified).
5. A0 and B0 measured on a plane 0.3 mm above the bottom of the pocket.
10
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PACKAGE OPTION ADDENDUM
www.ti.com
25-Apr-2017
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
CSD18563Q5A
ACTIVE
VSONP
DQJ
8
2500
Pb-Free (RoHS
Exempt)
CU SN
Level-1-260C-UNLIM
-55 to 150
CSD18563
CSD18563Q5A-P
PREVIEW
VSONP
DQJ
8
2500
Pb-Free (RoHS
Exempt)
CU SN
Level-1-260C-UNLIM
-55 to 150
CSD18563
CSD18563Q5AT
ACTIVE
VSONP
DQJ
8
250
Pb-Free (RoHS
Exempt)
CU SN
Level-1-260C-UNLIM
-55 to 150
CSD18563
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
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25-Apr-2017
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
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used in or for Designers’ applications) with all applicable regulations, laws and other applicable requirements. Designer represents that, with
respect to their applications, Designer has all the necessary expertise to create and implement safeguards that (1) anticipate dangerous
consequences of failures, (2) monitor failures and their consequences, and (3) lessen the likelihood of failures that might cause harm and
take appropriate actions. Designer agrees that prior to using or distributing any applications that include TI products, Designer will
thoroughly test such applications and the functionality of such TI products as used in such applications.
TI’s provision of technical, application or other design advice, quality characterization, reliability data or other services or information,
including, but not limited to, reference designs and materials relating to evaluation modules, (collectively, “TI Resources”) are intended to
assist designers who are developing applications that incorporate TI products; by downloading, accessing or using TI Resources in any
way, Designer (individually or, if Designer is acting on behalf of a company, Designer’s company) agrees to use any particular TI Resource
solely for this purpose and subject to the terms of this Notice.
TI’s provision of TI Resources does not expand or otherwise alter TI’s applicable published warranties or warranty disclaimers for TI
products, and no additional obligations or liabilities arise from TI providing such TI Resources. TI reserves the right to make corrections,
enhancements, improvements and other changes to its TI Resources. TI has not conducted any testing other than that specifically
described in the published documentation for a particular TI Resource.
Designer is authorized to use, copy and modify any individual TI Resource only in connection with the development of applications that
include the TI product(s) identified in such TI Resource. NO OTHER LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE
TO ANY OTHER TI INTELLECTUAL PROPERTY RIGHT, AND NO LICENSE TO ANY TECHNOLOGY OR INTELLECTUAL PROPERTY
RIGHT OF TI OR ANY THIRD PARTY IS GRANTED HEREIN, including but not limited to any patent right, copyright, mask work right, or
other intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information
regarding or referencing third-party products or services does not constitute a license to use such products or services, or a warranty or
endorsement thereof. Use of TI Resources may require a license from a third party under the patents or other intellectual property of the
third party, or a license from TI under the patents or other intellectual property of TI.
TI RESOURCES ARE PROVIDED “AS IS” AND WITH ALL FAULTS. TI DISCLAIMS ALL OTHER WARRANTIES OR
REPRESENTATIONS, EXPRESS OR IMPLIED, REGARDING RESOURCES OR USE THEREOF, INCLUDING BUT NOT LIMITED TO
ACCURACY OR COMPLETENESS, TITLE, ANY EPIDEMIC FAILURE WARRANTY AND ANY IMPLIED WARRANTIES OF
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NON-INFRINGEMENT OF ANY THIRD PARTY INTELLECTUAL
PROPERTY RIGHTS. TI SHALL NOT BE LIABLE FOR AND SHALL NOT DEFEND OR INDEMNIFY DESIGNER AGAINST ANY CLAIM,
INCLUDING BUT NOT LIMITED TO ANY INFRINGEMENT CLAIM THAT RELATES TO OR IS BASED ON ANY COMBINATION OF
PRODUCTS EVEN IF DESCRIBED IN TI RESOURCES OR OTHERWISE. IN NO EVENT SHALL TI BE LIABLE FOR ANY ACTUAL,
DIRECT, SPECIAL, COLLATERAL, INDIRECT, PUNITIVE, INCIDENTAL, CONSEQUENTIAL OR EXEMPLARY DAMAGES IN
CONNECTION WITH OR ARISING OUT OF TI RESOURCES OR USE THEREOF, AND REGARDLESS OF WHETHER TI HAS BEEN
ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
Unless TI has explicitly designated an individual product as meeting the requirements of a particular industry standard (e.g., ISO/TS 16949
and ISO 26262), TI is not responsible for any failure to meet such industry standard requirements.
Where TI specifically promotes products as facilitating functional safety or as compliant with industry functional safety standards, such
products are intended to help enable customers to design and create their own applications that meet applicable functional safety standards
and requirements. Using products in an application does not by itself establish any safety features in the application. Designers must
ensure compliance with safety-related requirements and standards applicable to their applications. Designer may not use any TI products in
life-critical medical equipment unless authorized officers of the parties have executed a special contract specifically governing such use.
Life-critical medical equipment is medical equipment where failure of such equipment would cause serious bodily injury or death (e.g., life
support, pacemakers, defibrillators, heart pumps, neurostimulators, and implantables). Such equipment includes, without limitation, all
medical devices identified by the U.S. Food and Drug Administration as Class III devices and equivalent classifications outside the U.S.
TI may expressly designate certain products as completing a particular qualification (e.g., Q100, Military Grade, or Enhanced Product).
Designers agree that it has the necessary expertise to select the product with the appropriate qualification designation for their applications
and that proper product selection is at Designers’ own risk. Designers are solely responsible for compliance with all legal and regulatory
requirements in connection with such selection.
Designer will fully indemnify TI and its representatives against any damages, costs, losses, and/or liabilities arising out of Designer’s noncompliance with the terms and provisions of this Notice.
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