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CSD19505KTT
SLPS587 – MARCH 2016
CSD19505KTT 80 V N-Channel NexFET™ Power MOSFET
1 Features
•
•
•
•
•
•
•
1
Product Summary
Ultra-Low Qg and Qgd
Low Thermal Resistance
Avalanche Rated
Pb-Free Terminal Plating
RoHS Compliant
Halogen Free
D2PAK Plastic Package
TA = 25°C
TYPICAL VALUE
Drain-to-Source Voltage
80
V
Qg
Gate Charge Total (10 V)
76
nC
Qgd
Gate Charge Gate to Drain
11
RDS(on)
Drain-to-Source On Resistance
VGS(th)
Threshold Voltage
nC
VGS = 6 V
2.9
mΩ
VGS = 10 V
2.6
mΩ
2.6
V
Device Information(1)
2 Applications
•
•
UNIT
VDS
Secondary Side Synchronous Rectifier
Motor Control
DEVICE
QTY
MEDIA
PACKAGE
SHIP
CSD19505KTT
500
CSD19505KTTT
50
13-Inch
Reel
D2PAK Plastic Package
Tape &
Reel
3 Description
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
This 80-V, 2.6-mΩ, D2PAK (TO-263) NexFET™
power MOSFET is designed to minimize losses in
power conversion applications.
TA = 25°C
VALUE
UNIT
SPACE
VDS
Drain-to-Source Voltage
80
V
VGS
Gate-to-Source Voltage
±20
V
Continuous Drain Current (Package
Limited)
200
A
Continuous Drain Current (Silicon Limited),
TC = 25°C
212
A
Continuous Drain Current (Silicon Limited),
TC = 100°C
150
A
IDM
Pulsed Drain Current(1)
400
A
PD
Power Dissipation
300
W
TJ,
Tstg
Operating Junction,
Storage Temperature
–55 to 175
°C
EAS
Avalanche Energy, Single Pulse
ID = 101 A, L = 0.1 mH, RG = 25 Ω
510
mJ
Absolute Maximum Ratings
Drain (Pin 2)
ID
Gate
(Pin 1)
Source (Pin 3)
.
(1) Max RθJC = 0.5°C/W, pulse duration ≤100 μs, duty cycle ≤1%.
.
.
RDS(on) vs VGS
Gate Charge
10
TC = 25° C, I D = 100 A
TC = 125° C, I D = 100 A
9
VGS - Gate-to-Source Voltage (V)
RDS(on) - On-State Resistance (m:)
10
8
7
6
5
4
3
2
1
ID = 100 A
9 VDS = 40 V
8
7
6
5
4
3
2
1
0
0
0
2
4
6
8
10
12
14
16
VGS - Gate-to-Source Voltage (V)
18
20
D007
0
10
20
30
40
50
Qg - Gate Charge (nC)
60
70
80
D004
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
CSD19505KTT
SLPS587 – MARCH 2016
www.ti.com
Table of Contents
1
2
3
4
5
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Specifications.........................................................
6.1
6.2
6.3
6.4
1
1
1
2
3
7
5.1 Electrical Characteristics........................................... 3
5.2 Thermal Information .................................................. 3
5.3 Typical MOSFET Characteristics.............................. 4
6
Community Resources..............................................
Trademarks ...............................................................
Electrostatic Discharge Caution ................................
Glossary ....................................................................
7
7
7
7
Mechanical, Packaging, and Orderable
Information ............................................................. 8
7.1 KTT Package Dimensions ........................................ 8
7.2 Recommended PCB Pattern..................................... 9
7.3 Recommended Stencil Opening (0.125 mm Stencil
Thickness).................................................................. 9
Device and Documentation Support.................... 7
4 Revision History
2
DATE
REVISION
NOTES
March 2016
*
Initial release.
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SLPS587 – MARCH 2016
5 Specifications
5.1 Electrical Characteristics
(TA = 25°C unless otherwise stated)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
STATIC CHARACTERISTICS
BVDSS
Drain-to-source voltage
VGS = 0 V, ID = 250 μA
IDSS
Drain-to-source leakage current
VGS = 0 V, VDS = 64 V
1
μA
IGSS
Gate-to-source leakage current
VDS = 0 V, VGS = 20 V
100
nA
VGS(th)
Gate-to-source threshold voltage
VDS = VGS, ID = 250 μA
RDS(on)
Drain-to-source on-resistance
gfs
Transconductance
80
2.2
V
2.6
3.2
V
VGS = 6 V, ID = 100 A
2.9
3.8
mΩ
VGS = 10 V, ID = 100 A
2.6
3.1
mΩ
VDS = 8 V, ID = 100 A
262
S
DYNAMIC CHARACTERISTICS
Ciss
Input capacitance
Coss
Output capacitance
Crss
Reverse transfer capacitance
RG
Series gate resistance
Qg
Gate charge total (10 V)
76
nC
Qgd
Gate charge gate-to-drain
11
nC
Qgs
Gate charge gate-to-source
25
nC
Qg(th)
Gate charge at Vth
15
nC
Qoss
Output charge
214
nC
td(on)
Turn on delay time
11
ns
tr
Rise time
5
ns
td(off)
Turn off delay time
22
ns
tf
Fall time
3
ns
VGS = 0 V, VDS = 40 V, ƒ = 1 MHz
VDS = 40 V, ID = 100 A
VDS = 40 V, VGS = 0 V
VDS = 40 V, VGS = 10 V,
IDS = 100 A, RG = 0 Ω
6090
7920
pF
1600
2080
pF
26
34
pF
1.4
2.8
Ω
DIODE CHARACTERISTICS
VSD
Diode forward voltage
ISD = 100 A, VGS = 0 V
0.9
1.1
V
Qrr
Reverse recovery charge
nC
Reverse recovery time
VDS= 40 V, IF = 100 A,
di/dt = 300 A/μs
400
trr
88
ns
5.2 Thermal Information
(TA = 25°C unless otherwise stated)
MAX
UNIT
RθJC
Junction-to-case thermal resistance
THERMAL METRIC
MIN
TYP
0.5
°C/W
RθJA
Junction-to-ambient thermal resistance
62
°C/W
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SLPS587 – MARCH 2016
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5.3 Typical MOSFET Characteristics
(TA = 25°C unless otherwise stated)
200
200
175
175
IDS - Drain-to-Source Current (A)
IDS - Drain-to-Source Current (A)
Figure 1. Transient Thermal Impedance
150
125
100
75
50
VGS = 6 V
VGS = 8 V
VGS = 10 V
25
0
TC = 125° C
TC = 25° C
TC = -55° C
150
125
100
75
50
25
0
0
0.1
0.2
0.3
0.4
0.5
VDS - Drain-to-Source Voltage (V)
0.6
0.7
1
D002
2
3
4
5
VGS - Gate-to-Source Voltage (V)
6
7
D003
VDS = 5 V
Figure 2. Saturation Characteristics
4
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Figure 3. Transfer Characteristics
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SLPS587 – MARCH 2016
Typical MOSFET Characteristics (continued)
(TA = 25°C unless otherwise stated)
100000
9
10000
8
C - Capacitance (pF)
VGS - Gate-to-Source Voltage (V)
10
7
6
5
4
3
1000
100
10
2
Ciss = Cgd + Cgs
Coss = Cds + Cgd
Crss = Cgd
1
1
0
0
10
20
30
40
50
Qg - Gate Charge (nC)
VDS = 40 V
60
70
0
80
10
20
30
40
50
60
VDS - Drain-to-Source Voltage (V)
D004
D005
Figure 5. Capacitance
3.2
10
3
9
RDS(on) - On-State Resistance (m:)
VGS(th) - Threshold Voltage (V)
80
ID = 100 A
Figure 4. Gate Charge
2.8
2.6
2.4
2.2
2
1.8
1.6
1.4
1.2
-75
70
TC = 25° C, I D = 100 A
TC = 125° C, I D = 100 A
8
7
6
5
4
3
2
1
0
-50
-25
0
0
25 50 75 100 125 150 175 200
TC - Case Temperature (° C)
D006
2
4
6
8
10
12
14
16
VGS - Gate-to-Source Voltage (V)
18
20
D007
ID = 250 µA
Figure 6. Threshold Voltage vs Temperature
Figure 7. On-State Resistance vs Gate-to-Source Voltage
100
2.2
VGS = 6 V
VGS = 10 V
ISD - Source-to-Drain Current (A)
Normalized On-State Resistance
2.4
2
1.8
1.6
1.4
1.2
1
0.8
TC = 25° C
TC = 125° C
10
1
0.1
0.01
0.001
0.6
0.4
-75
0.0001
-50
-25
0
25 50 75 100 125 150 175 200
TC - Case Temperature (° C)
D008
0
0.2
0.4
0.6
0.8
VSD - Source-to-Drain Voltage (V)
1
D009
ID = 100 A
Figure 8. Normalized On-State Resistance vs Temperature
Figure 9. Typical Diode Forward Voltage
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SLPS587 – MARCH 2016
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Typical MOSFET Characteristics (continued)
(TA = 25°C unless otherwise stated)
500
IAV - Peak Avalanche Current (A)
IDS - Drain-to-Source Current (A)
1000
100
10
1
DC
10 ms
0.1
0.1
1 ms
100 µs
10 µs
1
10
VDS - Drain-to-Source Voltage (V)
100
TC = 25qC
TC = 125qC
100
10
0.01
0.1
TAV - Time in Avalanche (ms)
D010
1
D011
Single Pulse, Max RθJC = 0.5°C/W
Figure 10. Maximum Safe Operating Area
Figure 11. Single Pulse Unclamped Inductive Switching
IDS - Drain-to-Source Current (A)
225
200
175
150
125
100
75
50
25
0
-50
-25
0
25
50
75 100 125
TC - Case Temperature (° C)
150
175
200
D012
Figure 12. Maximum Drain Current vs Temperature
6
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SLPS587 – MARCH 2016
6 Device and Documentation Support
6.1 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
6.2 Trademarks
NexFET, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
6.3 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
6.4 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
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CSD19505KTT
SLPS587 – MARCH 2016
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7 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
7.1 KTT Package Dimensions
15.5
14.7
9.25
9.05
A
B
3
10.26
10.06
2X 5.08
2
1
2[.0]X 1.36
1.23
2[.0]X 0.9
0.77
1.75 MAX
0.25
C A
B
1.4
1.17
0.47
0.34
C
4.7
4.4
8
0
0.25
0
1.32
1.22
2.6
2
0.25
GAGE PLANE
7.48
7.08
8°
0°
8.55
8.15
0.25
GAGE PLANE
NOTE 3
2.6
2
OPTIONAL LEAD FORM
EXPOSED
THERMAL PAD
Notes:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning
and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Features may not exist and shape may vary per different assembly sites.
Pin Configuration
POSITION
8
DESIGNATION
Pin 1
Gate
Pin 2 / Tab
Drain
Pin 3
Source
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SLPS587 – MARCH 2016
7.2 Recommended PCB Pattern
PKG
(3.4)
(6.9)
(R0.05) TYP
PKG
SYMM
(5.08)
(8.55)
2X (1.05)
2X (3.82)
(7.48)
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
0.07 MIN
ALL AROUND
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
For recommended circuit layout for PCB designs, see application note SLPA005 – Reducing Ringing Through
PCB Layout Techniques.
7.3 Recommended Stencil Opening (0.125 mm Stencil Thickness)
(1.17) TYP
42X (0.97)
(0.48) TYP
2X (3.82)
2X (1.05)
42X (0.95)
(R0.05) TYP
(1.15) TYP
SYMM
(5.08)
(6.9)
PKG
Notes:
1. This package is designed to be soldered to a thermal pad on the board. See application notes, PowerPAD
Thermally Enhanced Package (SLMA002)
and PowerPAD
Made Easy (SLMA004) for more information.
2. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525
may have alternate design recommendations.
3. Board assembly site may have different recommendations for stencil design.
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
(3)
Device Marking
(4/5)
(6)
CSD19505KTT
ACTIVE
DDPAK/
TO-263
KTT
3
500
RoHS-Exempt
& Green
SN
Level-2-260C-1 YEAR
-55 to 175
CSD19505KTT
CSD19505KTTT
ACTIVE
DDPAK/
TO-263
KTT
3
50
RoHS-Exempt
& Green
SN
Level-2-260C-1 YEAR
-55 to 175
CSD19505KTT
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of