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CSD22204W
SLPS559 – MARCH 2015
CSD22204W –8 V P-Channel NexFET™ Power MOSFET
1 Features
•
•
•
•
•
•
•
1
Product Summary
Low Resistance
Small Footprint 1.5 mm × 1.5 mm
Pb Free
Gate ESD Protection
RoHS Compliant
Halogen Free
Gate-Source Voltage Clamp
TA = 25°C
TYPICAL VALUE
VDS
Drain-to-Source Voltage
Qg
Gate Charge Total (–4.5 V)
Qgd
Gate Charge Gate-to-Drain
RDS(on)
Drain-to-Source On-Resistance
VGS(th)
Threshold Voltage
Battery Management
Battery Protection
Load Switch Applications
This –8 V, 8.2 mΩ, 1.5 mm × 1.5 mm device is
designed to deliver the lowest on resistance and gate
charge in the smallest outline possible with excellent
thermal characteristics in an ultra low profile. Low onresistance coupled with the small footprint and low
profile make the device ideal for battery operated
space constrained applications.
S
S
S
nC
11.5
mΩ
VGS = –4.5 V
8.2
mΩ
–0.7
V
Device
Qty
Media
Package
Ship
CSD22204W
3000
7-Inch Reel
CSD22204WT
250
7-Inch Reel
1.5 mm × 1.5 mm
Wafer BGA
Package
Tape and
Reel
TA = 25°C
VALUE
UNIT
VDS
Drain-to-Source Voltage
–8
V
VGS
Gate-to-Source Voltage
–6
V
Continuous Drain Current(1)
–5
A
Pulsed Drain Current(2)
–80
A
PD
Power Dissipation
1.7
W
TJ,
Tstg
Operating Junction and
Storage Temperature Range
–55 to 150
°C
ID
Source
S
4.2
VGS = –2.5 V
.
Absolute Maximum Ratings
Top View and Circuit Configuration
S
nC
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
3 Description
G
V
18.9
Ordering Information(1)
2 Applications
•
•
•
UNIT
–8
(1) Device operating at a temperature of 105ºC.
(2) Typ RθJA = 75°C/W, Pulse width ≤100 μs, duty cycle ≤1%.
Gate
D
D
D
Drain
RDS(on) vs VGS
Gate Charge
4.5
TC = 25° C, I D = -2 A
TC = 125° C, I D = -2 A
28
-VGS - Gate-to-Source Voltage (V)
RDS(on) - On-State Resistance (m:)
32
24
20
16
12
8
4
0
0.5
ID = -2 A
VDS = -4 V
4
3.5
3
2.5
2
1.5
1
0.5
0
1
1.5
2
2.5 3 3.5 4 4.5 5
-VGS - Gate-To-Source Voltage (V)
5.5
6
D007
0
2
4
6
8
10
12
14
Qg - Gate Charge (nC)
16
18
20
D004
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
CSD22204W
SLPS559 – MARCH 2015
www.ti.com
Table of Contents
1
2
3
4
5
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Specifications.........................................................
1
1
1
2
3
6
Device and Documentation Support.................... 7
6.1 Trademarks ............................................................... 7
6.2 Electrostatic Discharge Caution ................................ 7
6.3 Glossary .................................................................... 7
7
5.1 Electrical Characteristics........................................... 3
5.2 Thermal Information .................................................. 3
5.3 Typical MOSFET Characteristics.............................. 4
Mechanical, Packaging, and Orderable
Information ............................................................. 8
7.1 CSD22204W Package Dimensions .......................... 8
7.2 Recommended Land Pattern .................................... 9
7.3 Tape and Reel Information ....................................... 9
4 Revision History
2
DATE
REVISION
NOTES
March 2015
*
Initial release.
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SLPS559 – MARCH 2015
5 Specifications
5.1 Electrical Characteristics
(TA = 25°C unless otherwise stated)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
STATIC CHARACTERISTICS
BVDSS
Drain-to-Source Voltage
VGS = 0 V, IDS = –250 μA
–8
BVGSS
Gate-to-Source Voltage
VDS = 0 V, IG = –5 μA
–6
IDSS
Drain-to-Source Leakage Current
VGS = 0 V, VDS = –6.4 V
IGSS
Gate-to-Source Leakage Current
VDS = 0 V, VGS = –6 V
VGS(th)
Gate-to-Source Threshold Voltage
VDS = VGS, IDS = –250 μA
RDS(on)
Drain-to-Source On-Resistance
gƒs
Transconductance
–0.45
V
V
–1
μA
–4
μA
–0.7
–0.95
V
VGS = –2.5 V, IDS = –2 A
11.5
14.0
mΩ
VGS = –4.5 V, IDS = –2 A
8.2
9.9
mΩ
VDS = –0.8 V, IDS = –2 A
18
S
DYNAMIC CHARACTERISTICS
CISS
Input Capacitance
VGS = 0 V, VDS = –4 V,
ƒ = 1 MHz
870
1130
pF
COSS
Output Capacitance
445
580
pF
CRSS
Reverse Transfer Capacitance
204
265
pF
RG
Series Gate Resistance
300
Qg
Gate Charge Total (–4.5 V)
18.9
Qgd
Gate Charge - Gate-to-Drain
4.2
nC
Qgs
Gate Charge - Gate-to-Source
3.2
nC
Qg(th)
Gate Charge at Vth
0.7
nC
QOSS
Output Charge
3.1
nC
td(on)
Turn On Delay Time
58
ns
tr
Rise Time
600
ns
td(off)
Turn Off Delay Time
3450
ns
tƒ
Fall Time
2290
ns
VDS = –4 V,
ID = –2 A
VDS = –4 V, VGS = 0 V
VDS = –4 V, VGS = –4.5 V,
IDS = –2 A, RG = 0 Ω
Ω
24.6
nC
DIODE CHARACTERISTICS
VSD
Diode Forward Voltage
IDS = –2 A, VGS = 0 V
–0.7
–1.0
V
5.2 Thermal Information
(TA = 25°C unless otherwise stated)
THERMAL METRIC
RθJA
(1)
(2)
TYPCIAL VALUES
(1)
75
Junction-to-Ambient Thermal Resistance (2)
230
Junction-to-Ambient Thermal Resistance
UNIT
°C/W
Device mounted on FR4 material with 1 inch2 (6.45 cm2), 2 oz. (0.071 mm thick) Cu.
Device mounted on FR4 material with minimum Cu mounting area.
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CSD22204W
SLPS559 – MARCH 2015
www.ti.com
Typ RθJA = 230°C/W
when mounted on
minimum pad area of
2 oz. Cu.
Typ RθJA = 75°C/W
when mounted on
1inch2 of 2 oz. Cu.
M0149-01
M0150-01
5.3 Typical MOSFET Characteristics
(TA = 25°C unless otherwise stated)
Figure 1. Transient Thermal Impedance
4
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SLPS559 – MARCH 2015
Typical MOSFET Characteristics (continued)
(TA = 25°C unless otherwise stated)
20
-IDS - Drain-To-Source Current (A)
-IDS - Drain-to-Source Current (A)
20
16
12
8
4
VGS = -2.5 V
VGS = -4.5 V
0
0
0.05
0.1
0.15
0.2
0.25
-VDS - Drain-to-Source Voltage (V)
TC = 125° C
TC = 25° C
TC = -55° C
16
12
8
4
0
0.2
0.3
0.4
0.6
0.8
1
1.2
1.4
1.6
-VGS - Gate-To-Source Voltage (V)
D002
1.8
2
D003
VDS = –4 V
Figure 2. Saturation Characteristics
Figure 3. Transfer Characteristics
1200
4
1000
3.5
C - Capacitance (pF)
-VGS - Gate-to-Source Voltage (V)
4.5
3
2.5
2
1.5
800
Ciss = Cgd + Cgs
Coss = Cds + Cgd
Crss = Cgd
600
400
1
200
0.5
0
0
0
2
4
6
8
10
12
14
Qg - Gate Charge (nC)
ID = –2 A
16
18
0
20
1
D004
8
D005
Figure 5. Capacitance
32
1.1
RDS(on) - On-State Resistance (m:)
1
-VGS(th) - Threshold Voltage (V)
7
VDS = –4 V
Figure 4. Gate Charge
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
-75
2
3
4
5
6
-VDS - Drain-to-Source Voltage (V)
-50
-25
0
25
50
75 100
TC - Case Temperature (qC)
125
150
175
TC = 25° C, I D = -2 A
TC = 125° C, I D = -2 A
28
24
20
16
12
8
4
0
0.5
1
D006
1.5
2 2.5 3 3.5 4 4.5 5
-VGS - Gate-To-Source Voltage (V)
5.5
6
D007
ID = –250 µA
Figure 6. Threshold Voltage vs Temperature
Figure 7. On-State Resistance vs Gate-to-Source Voltage
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CSD22204W
SLPS559 – MARCH 2015
www.ti.com
Typical MOSFET Characteristics (continued)
(TA = 25°C unless otherwise stated)
10
1.3
VGS = -2.5 V
VGS = -4.5 V
-ISD - Source-To-Drain Current (A)
Normalized On-State Resistance
1.4
1.2
1.1
1
0.9
0.8
0.7
-75
TC = 25qC
TC = 125qC
1
0.1
0.01
0.001
0.0001
-50
-25
0
25
50
75 100
TC - Case Temperature (qC)
125
150
0
175
0.2
0.4
0.6
0.8
-VSD - Source-To-Drain Voltage (V)
D008
1
D009
ID = –2 A
Figure 8. Normalized On-State Resistance vs Temperature
Figure 9. Typical Diode Forward Voltage
6
-IDS - Drain-to-Source Current (A)
-IDS - Drain-To-Source Current (A)
100
10
1
100 ms
10 ms
0.1
0.1
1 ms
100 µs
1
-VDS - Drain-To-Source Voltage (V)
10
5
4
3
2
1
0
-55
-30
D010
-5
20
45
70
95
120
TC - Case Temperature (qC)
145
170
D011
Single Pulse, Max RθJA = 75°C/W
Figure 10. Maximum Safe Operating Area
6
Figure 11. Maximum Drain Current vs Temperature
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CSD22204W
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SLPS559 – MARCH 2015
6 Device and Documentation Support
6.1 Trademarks
NexFET is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
6.2 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
6.3 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
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CSD22204W
SLPS559 – MARCH 2015
www.ti.com
7 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation
7.1 CSD22204W Package Dimensions
Solder Ball
Ø 0.31 ±0.075
Pin 1
Mark
1
2
3
3
2
1
A
B
1.50
B
1.00
+0.00
–0.08
0.50
A
C
C
1.50
+0.00
–0.08
0.62 Max
Top View
0.50
Bottom View
0.04
0.62 Max
0.35 ±0.10
Side View
Seating Plate
Front View
M0171-01
NOTE: All dimensions are in mm (unless otherwise specified)
Pinout
8
POSITION
DESIGNATION
A1
Gate
A2, A3, B1, B2,
B3
Source
C1, C2, C3
Drain
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SLPS559 – MARCH 2015
7.2 Recommended Land Pattern
Ø 0.25
1
2
3
1.00
0.50
A
B
C
0.50
M0172-01
NOTE: All dimensions are in mm (unless otherwise specified)
7.3 Tape and Reel Information
4.00 ±0.10
2.00 ±0.05
4.00 ±0.10
Ø 0.50 ±0.05
0.86 ±0.05
1.60 ±0.05
5° Max
3.50 ±0.05
8.00
+0.30
–0.10
1.75 ±0.10
Ø 1.50 ±0.10
0.254 ±0.02
1.60 ±0.05
5° Max
M0173-01
NOTES: 1. 10-sprocket hole-pitch cumulative tolerance ±0.2
2. Camber not to exceed 1mm in 100 mm, noncumulative over 250 mm
3. Material: black static-dissipative polystyrene
4. All dimensions are in mm (unless otherwise specified)
5. Thickness: 0.30 ±0.05 mm
6. MSL1 260°C (IR and convection) PbF reflow compatible
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9
PACKAGE OPTION ADDENDUM
www.ti.com
1-Dec-2015
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
CSD22204W
ACTIVE
DSBGA
YZF
9
3000
Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
22204
CSD22204WT
ACTIVE
DSBGA
YZF
9
250
Green (RoHS
& no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
22204
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
1-Dec-2015
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
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