CSD23381F4T

CSD23381F4 SLPS450G – OCTOBER 2013 – REVISED JANUARY 2022 CSD23381F4 12-V P-Channel FemtoFET™ MOSFET Product Summary (continued) 1 Features • • • • • • • • TA = 25°C Ultra-low on-resistance Ultra-low Qg and Qgd High operating drain current Ultra-small footprint (0402 case size) – 1.0 mm × 0.6 mm Ultra-low profile – Maximum height: 0.36 mm Integrated ESD protection diode – Rated > 4-kV HBM – Rated > 2-kV CDM Lead and halogen free RoHS compliant VGS(th) • • Qty CSD23381F4 3000 CSD23381F4T 250 Media Package Ship 7-inch reel Femto(0402) 1.0-mm × 0.6-mm Land Grid Array (LGA) Tape and reel For all available packages, see the orderable addendum at the end of the data sheet. TA = 25°C Drain-to-source voltage –12 V Gate-to-source voltage –8 V ID Continuous drain current(1) –2.3 A IDM Pulsed drain current(2) –9 A Continuous gate clamp current –35 Pulsed gate clamp current(2) –350 Power dissipation(1) PD Product Summary UNIT VGS IG This 150 mΩ, 12 V P-Channel FemtoFET™ MOSFET is designed and optimized to minimize the footprint in many handheld and mobile applications. This technology is capable of replacing standard small signal MOSFETs while providing at least a 60% reduction in footprint size. VALUE VDS V(ESD) TJ, Tstg (1) (2) mA 500 mW Human body model (HBM) 4 kV Charged device model (CDM) 2 kV –55 to 150 °C Operating junction and storage temperature range Typical RθJA = 85°C/W on 1-inch2 (6.45 cm2), 2-oz. (0.071-mm thick) Cu pad on a 0.06-inch (1.52 mm) thick FR4 PCB. Pulse duration ≤ 300 μs, duty cycle ≤ 2% . TYPICAL VALUE UNIT . VDS Drain-to-source voltage –12 V Qg Gate charge total (–4.5 V) 1140 pC . Qgd Gate charge gate-to-drain pC . Drain-to-source on-resistance V . Absolute Maximum Ratings 3 Description RDS(on) –0.95 Threshold voltage Device(1) (1) Optimized for load switch applications Optimized for general purpose switching applications Battery applications Handheld and mobile applications TA = 25°C UNIT Ordering Information 2 Applications • • TYPICAL VALUE 190 VGS = –1.8 V 480 mΩ VGS = –2.5 V 250 mΩ VGS = –4.5 V 150 mΩ . D 0.36 mm 0.60 mm 1.00 mm G S Typical Device Dimensions Top View An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. CSD23381F4 www.ti.com SLPS450G – OCTOBER 2013 – REVISED JANUARY 2022 Table of Contents 1 Features............................................................................1 2 Applications..................................................................... 1 3 Description.......................................................................1 4 Revision History.............................................................. 2 5 Specifications.................................................................. 3 5.1 Electrical Characteristics.............................................3 5.2 Thermal Information....................................................3 5.3 Typical MOSFET Characteristics................................ 4 6 Device and Documentation Support..............................6 6.1 Trademarks................................................................. 6 6.2 Electrostatic Discharge Caution..................................6 6.3 Glossary......................................................................6 7 Mechanical, Packaging, and Orderable Information.... 7 7.1 Mechanical Dimensions.............................................. 7 7.2 Recommended Minimum PCB Layout........................8 7.3 Recommended Stencil Pattern................................... 8 7.4 CSD23381F4 Embossed Carrier Tape Dimensions....9 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision F (October 2021) to Revision G (January 2022) Page • Changed Maximum height from "0.35 mm" to "0.36 mm" in Features ...............................................................1 • Changed height dimension from "0.35 mm" to "0.36 mm" in Typical Device Dimensions ................................. 1 • Changed maximum height dimension from "0.35 mm" to "0.36 mm" in Mechanical Dimensions ..................... 7 Changes from Revision E (May 2015) to Revision F (October 2021) Page • Added footnote with link to support document....................................................................................................8 Changes from Revision D (September 2014) to Revision E (May 2015) Page • Corrected typo for IDSS Test Condition ...............................................................................................................3 • Corrected typo for IGSS Test Condition ...............................................................................................................3 2 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: CSD23381F4 CSD23381F4 www.ti.com SLPS450G – OCTOBER 2013 – REVISED JANUARY 2022 5 Specifications 5.1 Electrical Characteristics (TA = 25°C unless otherwise stated) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT –100 nA STATIC CHARACTERISTICS BVDSS Drain-to-Source Voltage VGS = 0 V, IDS = –250 μA IDSS Drain-to-Source Leakage Current VGS = 0 V, VDS = –9.6 V IGSS Gate-to-Source Leakage Current VDS = 0 V, VGS = –8 V VGS(th) Gate-to-Source Threshold Voltage VDS = VGS, IDS = –250 μA RDS(on) Drain-to-Source On-Resistance gfs Transconductance –12 V –50 nA –0.95 –1.20 V VGS = –1.8 V, IDS = –0.1 A 480 970 mΩ VGS = –2.5 V, IDS = –0.5 A 250 300 mΩ VGS = –4.5 V, IDS = –0.5 A 150 175 mΩ –0.7 VDS = –6 V, IDS = –0.5 A 2 S 236 pF 98 pF DYNAMIC CHARACTERISTICS Ciss Input Capacitance Coss Output Capacitance Crss Reverse Transfer Capacitance 6.9 pF RG Series Gate Resistance 20 Ω Qg Gate Charge Total (4.5 V) 1140 pC Qgd Gate Charge Gate-to-Drain 190 pC Qgs Gate Charge Gate-to-Source 300 pC Qg(th) Gate Charge at Vth 145 pC Qoss Output Charge 1290 pC td(on) Turn On Delay Time 4.5 ns tr Rise Time 3.9 ns td(off) Turn Off Delay Time 18 ns tf Fall Time 7 ns VGS = 0 V, VDS = –6 V, ƒ = 1 MHz VDS = –6 V, IDS = –0.5 A VDS = –6 V, VGS = 0 V VDS = –6 V, VGS = –4.5 V, IDS = –0.5 A, RG = 2 Ω DIODE CHARACTERISTICS VSD Diode Forward Voltage Qrr Reverse Recovery Charge trr Reverse Recovery Time ISD = –0.5 A, VGS = 0 V VDS= –10 V, IF = –0.5 A, di/dt = 100 A/μs –0.75 V 1260 pC 7.9 ns 5.2 Thermal Information (TA = 25°C unless otherwise stated) THERMAL METRIC RθJA (1) (2) TYPICAL VALUES Junction-to-Ambient Thermal Resistance(1) 85 Junction-to-Ambient Thermal Resistance(2) 245 UNIT °C/W Device mounted on FR4 material with 1-inch2 (6.45 cm2), 2-oz. (0.071 mm thick) Cu. Device mounted on FR4 material with minimum Cu mounting area. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: CSD23381F4 3 CSD23381F4 www.ti.com SLPS450G – OCTOBER 2013 – REVISED JANUARY 2022 5.3 Typical MOSFET Characteristics (TA = 25°C unless otherwise stated) − IDS - Drain-to-Source Current (A) 5.5 Figure 5-1. Transient Thermal Impedance VGS = −4.5V VGS = −2.5V VGS = −1.8V 5 4.5 4 3.5 3 2.5 2 1.5 1 0.5 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 − VDS - Drain-to-Source Voltage (V) 1.8 2 G001 Figure 5-2. Saturation Characteristics − IDS - Drain-to-Source Current (A) 5.5 VDS = −5V 5 4.5 4 3.5 3 2.5 2 1.5 TC = 125°C TC = 25°C TC = −55°C 1 0.5 0 0 0.5 1 1.5 2 2.5 3 − VGS - Gate-to-Source Voltage (V) 3.5 4 G001 Figure 5-3. Transfer Characteristics 300 ID = −0.5A VDS = −6V 4 270 240 3.5 C − Capacitance (pF) − VGS - Gate-to-Source Voltage (V) 4.5 3 2.5 2 1.5 1 Ciss = Cgd + Cgs Coss = Cds + Cgd Crss = Cgd 180 150 120 90 60 0.5 0 210 30 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 Qg - Gate Charge (nC) 1 1.1 1.2 0 0 1 G001 Figure 5-4. Gate Charge 4 2 3 4 5 6 7 8 9 10 − VDS - Drain-to-Source Voltage (V) 11 12 G001 Figure 5-5. Capacitance Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: CSD23381F4 CSD23381F4 www.ti.com SLPS450G – OCTOBER 2013 – REVISED JANUARY 2022 5.3 Typical MOSFET Characteristics (continued) (TA = 25°C unless otherwise stated) 1.25 600 RDS(on) - On-State Resistance (mΩ) − VGS(th) - Threshold Voltage (V) ID = −250uA 1.15 1.05 0.95 0.85 0.75 0.65 0.55 0.45 −75 −25 25 75 125 TC - Case Temperature (ºC) 360 300 240 180 120 60 0 1 2 3 4 5 6 − VGS - Gate-to- Source Voltage (V) 7 8 G001 Figure 5-7. On-State Resistance vs Gate-to-Source Voltage 1.4 10 VGS = −4.5V, ID = −0.5A − ISD − Source-to-Drain Current (A) Normalized On-State Resistance 420 G001 Figure 5-6. Threshold Voltage vs Temperature 1.3 1.2 1.1 1 0.9 0.8 0.7 −75 −25 25 75 125 TC - Case Temperature (ºC) 175 TC = 25°C TC = 125°C 1 0.1 0.01 0.001 0.0001 0 0.2 0.4 0.6 0.8 − VSD − Source-to-Drain Voltage (V) G001 Figure 5-8. Normalized On-State Resistance vs Temperature 1 G001 Figure 5-9. Typical Diode Forward Voltage 100 3.0 1ms 10ms 100ms 1s DC − IDS - Drain- to- Source Current (A) − IDS - Drain-to-Source Current (A) 480 0 175 TC = 25°C, ID = −0.5A TC = 125°C, ID = −0.5A 540 10 1 0.1 Single Pulse Typical RthetaJA =245ºC/W(min Cu) 0.01 0.01 0.1 1 10 − VDS - Drain-to-Source Voltage (V) Figure 5-10. Maximum Safe Operating Area 50 2.5 2.0 1.5 1.0 0.5 Typical RthetaJA = 85ºC/W(max Cu) 0.0 −50 G001 −25 0 25 50 75 100 125 TA - AmbientTemperature (ºC) 150 175 G001 Figure 5-11. Maximum Drain Current vs Temperature Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: CSD23381F4 5 CSD23381F4 www.ti.com SLPS450G – OCTOBER 2013 – REVISED JANUARY 2022 6 Device and Documentation Support 6.1 Trademarks FemtoFET™ is a trademark of Texas Instruments. All trademarks are the property of their respective owners. 6.2 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 6.3 Glossary TI Glossary 6 This glossary lists and explains terms, acronyms, and definitions. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: CSD23381F4 CSD23381F4 www.ti.com SLPS450G – OCTOBER 2013 – REVISED JANUARY 2022 7 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 7.1 Mechanical Dimensions 1.04 0.96 A B PIN 1 INDEX AREA 0.64 0.56 0.36 MAX C SEATING PLANE 0.65 0.325 0.175 2 3 0.35 0.51 0.49 1 0.015 A. B. C. 0.16 2X 0.14 C B A 2X 0.26 0.24 0.26 0.24 0.015 C A B All linear dimensions are in millimeters (dimensions and tolerancing per AME T14.5M-1994). This drawing is subject to change without notice. This package is a PB free solder land design. Pin Configuration Position Designation Pin 1 Gate Pin 2 Source Pin 3 Drain Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: CSD23381F4 7 CSD23381F4 www.ti.com SLPS450G – OCTOBER 2013 – REVISED JANUARY 2022 7.2 Recommended Minimum PCB Layout (0.25) 2X (0.25) PKG 0.05 MIN ALL AROUND 2X (0.15) 1 3 SYMM (0.35) (0.5) EXAMPLE STENCIL DESIGN YJC0003A(R0.05) TYP 2 PicoStar TM - 0.35 mm max height SOLDER MASK OPENING (0.65) LAND PATTERN EXAMPLE A. B. PicoStar TM METAL UNDER SOLDER MASK SOLDER MASK DEFINED All dimensions are in millimeters. SCALE:50X For more information, see FemtoFET Surface Mount Guide (SLRA003D). 7.3 Recommended Stencil Pattern 2X (0.25) 2X (0.2) PKG (0.25) 1 SYMM (0.4) (0.5) 3 2 2X (0.15) (R0.05) TYP (0.65) 2X SOLDER MASK EDGE A. All dimensions are in millimeters. SOLDER PASTE EXAMPLE ON 0.075 - 0.1 mm THICK STENCIL SCALE:50X 4220651/B 08/2015 NOTES: (continued) 4. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). www.ti.com 8 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: CSD23381F4 CSD23381F4 www.ti.com SLPS450G – OCTOBER 2013 – REVISED JANUARY 2022 7.4 CSD23381F4 Embossed Carrier Tape Dimensions A. Pin 1 is oriented in the top-right quadrant of the tape enclosure (quadrant 2), closest to the carrier tape sprocket holes. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: CSD23381F4 9 PACKAGE OPTION ADDENDUM www.ti.com 26-Jan-2022 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) CSD23381F4 ACTIVE PICOSTAR YJC 3 3000 RoHS & Green NIAU Level-1-260C-UNLIM -55 to 150 DS CSD23381F4T ACTIVE PICOSTAR YJC 3 250 RoHS & Green NIAU Level-1-260C-UNLIM -55 to 150 DS (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of