CSD25310Q2

Sample & Buy Product Folder Support & Community Tools & Software Technical Documents CSD25310Q2 SLPS459A – JANUARY 2014 – REVISED JUNE 2014 CSD25310Q2 20 V P-Channel NexFET™ Power MOSFETs 1 Features • • • • • • • 1 Product Summary Ultra-Low Qg and Qgd Low On Resistance Low Thermal Resistance Pb-Free RoHS Compliant Halogen Free SON 2-mm × 2-mm Plastic Package TA = 25°C TYPICAL VALUE Drain-to-Source Voltage –20 V Qg Gate Charge Total (–4.5 V) 3.6 nC Qgd Gate Charge Gate to Drain RDS(on) VGS(th) nC VGS = –1.8 V 59.0 mΩ VGS = –2.5 V 27.0 mΩ VGS = –4.5 V 19.9 mΩ Threshold Voltage -0.85 V . Ordering Information(1) Battery Management Load Management Battery Protection 3 Description This 19.9 mΩ, –20 V P-Channel device is designed to deliver the lowest on resistance and gate charge in the smallest outline possible with excellent thermal characteristics in an ultra-low profile. Its low on resistance coupled with an extremely small footprint in a SON 2 mm × 2 mm plastic package make the device ideal for battery operated space constrained operations. Top View S 0.5 Drain-to-Source On Resistance 2 Applications • • • UNIT VDS 1 6 S Device Media Qty Package Ship CSD25310Q2 7-Inch Reel 3000 CSD25310Q2T 7-Inch Reel 250 SON 2 x 2 mm Plastic Package Tape and Reel (1) For all available packages, see the orderable addendum at the end of the data sheet. Absolute Maximum Ratings TA = 25°C VALUE UNIT VDS Drain-to-Source Voltage –20 V VGS Gate-to-Source Voltage ±8 V Continuous Drain Current (Package Limit) –20 A Continuous Drain Current(1) –9.6 A ID IDM Pulsed Drain Current(2) 48 A PD Power Dissipation(1) 2.9 W TJ, Tstg Operating Junction and Storage Temperature Range –55 to 150 °C S S 2 G 3 D 5 S 4 D (1) RθJA = 43°C/W on 1 in² Cu (2 oz.) on .060-inch thick FR4 PCB. (2) Pulse duration 10 μs, duty cycle ≤2% P0112-01 RDS(on) vs VGS Gate Charge 5 TC = 25°C, I D = −5A TC = 125°C, I D = −5A 72 − VGS - Gate-to-Source Voltage (V) RDS(on) - On-State Resistance (mΩ) 80 64 56 48 40 32 24 16 8 0 0 1 2 3 4 5 6 − VGS - Gate-to- Source Voltage (V) 7 8 G001 ID = −5A VDS = −10V 4.5 4 3.5 3 2.5 2 1.5 1 0.5 0 0 0.5 1 1.5 2 2.5 3 3.5 Qg - Gate Charge (nC) 4 4.5 5 G001 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. CSD25310Q2 SLPS459A – JANUARY 2014 – REVISED JUNE 2014 www.ti.com Table of Contents 1 2 3 4 5 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Specifications......................................................... 1 1 1 2 3 5.1 Electrical Characteristics.......................................... 3 5.2 Thermal Information .................................................. 3 5.3 Typical MOSFET Characteristics.............................. 4 6 Device and Documentation Support.................... 7 6.1 Trademarks ............................................................... 7 6.2 Electrostatic Discharge Caution ................................ 7 6.3 Glossary .................................................................... 7 7 Mechanical, Packaging, and Orderable Information ............................................................. 8 7.1 7.2 7.3 7.4 Q2 Package Dimensions .......................................... 9 Recommended PCB Pattern................................... 10 Recommended Stencil Pattern ............................... 10 Q2 Tape and Reel Information................................ 11 4 Revision History Changes from Original (January 2014) to Revision A Page • Revised "Pb-Free Terminal Plating" to Only State "Pb-Free" ................................................................................................ 1 • Added small reel option to the Ordering Information Table ................................................................................................... 1 2 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: CSD25310Q2 CSD25310Q2 www.ti.com SLPS459A – JANUARY 2014 – REVISED JUNE 2014 5 Specifications 5.1 Electrical Characteristics TA = 25°C, unless otherwise specified PARAMETER TEST CONDITIONS MIN TYP MAX UNIT STATIC CHARACTERISTICS BVDSS Drain-to-Source Voltage VGS = 0 V, ID = –250 μA IDSS Drain-to-Source Leakage Current VGS = 0 V, VDS = –16 V IGSS Gate-to-Source Leakage Current VDS = 0 V, VGS = –8 V VGS(th) Gate-to-Source Threshold Voltage VDS = VGS, IDS = –250 μA RDS(on) Drain-to-Source On Resistance gfs Transconductance –20 –0.55 V –1 μA –100 nA –0.85 –1.10 V VGS = –1.8 V, IDS = –5 A 59.0 89.0 mΩ VGS = –2.5 V, IDS = –5 A 27.0 32.5 mΩ VGS = –4.5 V, IDS = –5 A 19.9 23.9 mΩ VDS = –16 V, IDS = –5 A 34 S DYNAMIC CHARACTERISTICS CISS Input Capacitance 504 COSS Output Capacitance CRSS Reverse Transfer Capacitance Rg Series Gate Resistance 1.9 Qg Gate Charge Total (–4.5 V) 3.6 Qgd Gate Charge Gate to Drain 0.5 nC Qgs Gate Charge Gate to Source 1.1 nC Qg(th) Gate Charge at Vth 0.6 nC QOSS Output Charge 5.0 nC td(on) Turn On Delay Time 8 ns tr Rise Time 15 ns td(off) Turn Off Delay Time 15 ns tf Fall Time 5 ns VGS = 0 V, VDS = –10 V, f = 1 MHz VDS = –10 V, IDS = –5 A VDS = –10 V, VGS = 0 V 655 pF 281 365 pF 16.7 21.7 pF VDS = –10 V, VGS = –4.5 V, IDS = –5 A RG = 2 Ω Ω 4.7 nC DIODE CHARACTERISTICS VSD Diode Forward Voltage Qrr Reverse Recovery Charge IDS = –5 A, VGS = 0 V trr Reverse Recovery Time –0.8 VDD = –10 V, IF = –5 A, di/dt = 200 A/μs –1.0 V 9.2 nC 13 ns 5.2 Thermal Information (TA = 25°C unless otherwise stated) THERMAL METRIC MIN TYP MAX RθJC Thermal Resistance Junction to Case (1) 4.5 RθJA Thermal Resistance Junction to Ambient (1) (2) 55 (1) (2) UNIT °C/W RθJC is determined with the device mounted on a 1-inch2 (6.45-cm2), 2-oz. (0.071-mm thick) Cu pad on a 1.5-inch × 1.5-inch (3.81-cm × 3.81-cm), 0.06-inch (1.52-mm) thick FR4 PCB. RθJC is specified by design, whereas RθJA is determined by the user’s board design. Device mounted on FR4 material with 1-inch2 (6.45-cm2), 2-oz. (0.071-mm thick) Cu. Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: CSD25310Q2 3 CSD25310Q2 SLPS459A – JANUARY 2014 – REVISED JUNE 2014 GATE www.ti.com GATE Source Source Max RθJA = 55 when mounted on 1 inch2 (6.45 cm2) of 2-oz. (0.071-mm thick) Cu. Max RθJA = 215 when mounted on minimum pad area of 2-oz. (0.071-mm thick) Cu. DRAIN DRAIN M0161-02 M0161-01 5.3 Typical MOSFET Characteristics (TA = 25°C unless otherwise stated) Figure 1. Transient Thermal Impedance 4 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: CSD25310Q2 CSD25310Q2 www.ti.com SLPS459A – JANUARY 2014 – REVISED JUNE 2014 Typical MOSFET Characteristics (continued) (TA = 25°C unless otherwise stated) 50 − IDS - Drain-to-Source Current (A) − IDS - Drain-to-Source Current (A) 50 45 40 35 30 VGS = −4.5V VGS = −2.5V VGS = −1.8V 25 20 15 10 5 0 0 1 2 3 4 − VDS - Drain-to-Source Voltage (V) 40 35 30 25 20 15 TC = 125°C TC = 25°C TC = −55°C 10 5 0 5 VDS = −5V 45 0 0.5 G001 Figure 2. Saturation Characteristics 4 G001 10000 Ciss = Cgd + Cgs Coss = Cds + Cgd Crss = Cgd ID = −5A VDS = −10V 4.5 4 1000 C − Capacitance (nF) − VGS - Gate-to-Source Voltage (V) 3.5 Figure 3. Transfer Characteristics 5 3.5 3 2.5 2 1.5 100 10 1 0.5 0 0 0.5 1 1.5 2 2.5 3 3.5 Qg - Gate Charge (nC) 4 4.5 1 5 0 2 4 6 8 10 12 14 16 − VDS - Drain-to-Source Voltage (V) G001 Figure 4. Gate Charge 18 20 G001 Figure 5. Capacitance 1.15 80 RDS(on) - On-State Resistance (mΩ) ID = −250uA − VGS(th) - Threshold Voltage (V) 1 1.5 2 2.5 3 − VGS - Gate-to-Source Voltage (V) 1.05 0.95 0.85 0.75 0.65 0.55 0.45 −75 −25 25 75 125 TC - Case Temperature (ºC) Figure 6. Threshold Voltage vs Temperature 175 TC = 25°C, I D = −5A TC = 125°C, I D = −5A 72 64 56 48 40 32 24 16 8 0 0 G001 1 2 3 4 5 6 − VGS - Gate-to- Source Voltage (V) 7 8 G001 Figure 7. On-State Resistance vs Gate-to-Source Voltage Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: CSD25310Q2 5 CSD25310Q2 SLPS459A – JANUARY 2014 – REVISED JUNE 2014 www.ti.com Typical MOSFET Characteristics (continued) (TA = 25°C unless otherwise stated) 100 1.5 ID = −5A − ISD − Source-to-Drain Current (A) Normalized On-State Resistance 1.6 1.4 1.3 1.2 1.1 1 0.9 0.8 VGS = −4.5V VGS = −2.5V 0.7 0.6 −75 −25 25 75 125 TC - Case Temperature (ºC) 175 TC = 25°C TC = 125°C 10 1 0.1 0.01 0.001 0.0001 0 Figure 8. Normalized On-State Resistance vs Temperature G001 24.0 1ms 10ms 100ms 1s DC − IDS - Drain- to- Source Current (A) − IDS - Drain-to-Source Current (A) 1 Figure 9. Typical Diode Forward Voltage 1000 100 10 1 0.1 Single Pulse Typical RthetaJA =170ºC/W(min Cu) 0.01 0.01 0.1 1 10 − VDS - Drain-to-Source Voltage (V) Figure 10. Maximum Safe Operating Area 6 0.2 0.4 0.6 0.8 − VSD − Source-to-Drain Voltage (V) G001 50 20.0 16.0 12.0 8.0 4.0 0.0 −50 G001 −25 0 25 50 75 100 125 TC - Case Temperature (ºC) 150 175 G001 Figure 11. Maximum Drain Current vs Temperature Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: CSD25310Q2 CSD25310Q2 www.ti.com SLPS459A – JANUARY 2014 – REVISED JUNE 2014 6 Device and Documentation Support 6.1 Trademarks NexFET is a trademark of Texas Instruments. All other trademarks are the property of their respective owners. 6.2 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 6.3 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms and definitions. Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: CSD25310Q2 7 CSD25310Q2 SLPS459A – JANUARY 2014 – REVISED JUNE 2014 www.ti.com 7 Mechanical, Packaging, and Orderable Information The following pages include mechanical packaging and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 8 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: CSD25310Q2 CSD25310Q2 www.ti.com SLPS459A – JANUARY 2014 – REVISED JUNE 2014 7.1 Q2 Package Dimensions D2 D K3 K1 K K2 4 1 2 3 4 5 6 3 2 1 K4 E E1 E2 5 E3 6 L Pin 1 Dot Top View Pin 1 ID e b D1 A A1 C Bottom View Front View M0165-01 DIM MILLIMETERS INCHES MIN NOM MAX MIN NOM MAX A 0.700 0.750 0.800 0.028 0.030 0.032 A1 0.000 0.050 0.000 b 0.250 0.350 0.010 C 0.203 TYP D D1 0.300 0.950 0.080 TYP 1.000 0.036 0.038 D2 0.300 TYP 0.012 TYP E 2.000 TYP 0.080 TYP E1 0.900 1.000 1.100 0.036 0.040 E2 0.280 TYP 0.0112 TYP E3 0.470 TYP 0.0188 TYP e 0.650 TYP 0.026 TYP K 0.280 TYP 0.0112 TYP K1 0.350 TYP 0.014 TYP K2 0.200 TYP 0.008 TYP K3 0.200 TYP 0.008 TYP K4 0.470 TYP 0.0188 TYP L 0.200 0.25 0.014 0.008 TYP 2.000 TYP 0.900 0.002 0.012 0.300 0.008 0.010 0.040 0.044 0.012 Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: CSD25310Q2 9 CSD25310Q2 SLPS459A – JANUARY 2014 – REVISED JUNE 2014 www.ti.com 7.2 Recommended PCB Pattern For recommended circuit layout for PCB designs, see application note SLPA005 – Reducing Ringing Through PCB Layout Techniques. 7.3 Recommended Stencil Pattern Note: 10 All dimensions are in mm, unless otherwise specified. Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: CSD25310Q2 CSD25310Q2 www.ti.com SLPS459A – JANUARY 2014 – REVISED JUNE 2014 7.4 Q2 Tape and Reel Information 4.00 ±0.10 Ø 1.50 ±0.10 4.00 ±0.10 Ø 1.00 ±0.25 1.00 ±0.05 2.30 ±0.05 10° Max 3.50 ±0.05 8.00 +0.30 –0.10 1.75 ±0.10 2.00 ±0.05 0.254 ±0.02 2.30 ±0.05 10° Max M0168-01 Notes: 1. Measured from centerline of sprocket hole to centerline of pocket 2. Cumulative tolerance of 10 sprocket holes is ±0.20 3. Other material available 4. Typical SR of form tape Max 109 OHM/SQ 5. All dimensions are in mm, unless otherwise specified. Submit Documentation Feedback Copyright © 2014, Texas Instruments Incorporated Product Folder Links: CSD25310Q2 11 PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) CSD25310Q2 ACTIVE WSON DQK 6 3000 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -55 to 150 2530 CSD25310Q2T ACTIVE WSON DQK 6 250 RoHS & Green SN Level-1-260C-UNLIM -55 to 150 2530 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of