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CSD25402Q3A
SLPS454B – DECEMBER 2013 – REVISED JANUARY 2016
CSD25402Q3A –20 V P-Channel NexFET™ Power MOSFET
1 Features
•
•
•
•
•
•
1
Product Summary
Ultra-Low Qg and Qgd
Low Thermal Resistance
Low RDS(on)
Pb and Halogen Free
RoHS Compliant
SON 3.3 mm × 3.3 mm Plastic Package
TA = 25°C
•
•
•
•
–20
V
Qg
Gate charge total (–4.5 V)
7.5
nC
Qgd
Gate charge gate to drain
Vth
DC-DC Converters
Battery Management
Load Switch
Battery Protection
UNIT
Drain-to-source voltage
RDS(on)
2 Applications
TYPICAL VALUE
VDS
1.1
Drain-to-source on resistance
nC
VGS = –1.8 V
74
mΩ
VGS = –2.5 V
13.3
mΩ
VGS = –4.5 V
7.7
mΩ
Threshold voltage
–0.9
V
Ordering Information(1)
DEVICE
QTY
CSD25402Q3A
MEDIA
2500 13-Inch Reel
CSD25402Q3AT
250
7-Inch Reel
PACKAGE
SHIP
SON 3.3 mm × 3.3
mm Plastic Package
Tape and
Reel
3 Description
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
This –20-V, 7.7-mΩ NexFET™ power MOSFET is
designed to minimize losses in power conversion load
management applications with a SON 3.3 mm × 3.3
mm package that offers an excellent thermal
performance for the size of the device.
TA = 25°C
Top View
D
VALUE
UNIT
VDS
Drain-to-source voltage
–20
V
VGS
Gate-to-source voltage
+12 or –12
V
Continuous drain current, TC = 25°C
–76
A
Continuous drain current (package limit)
–35
A
Continuous drain current(1)
–15
A
Pulsed drain current(2)
–148
A
ID
8
1
Absolute Maximum Ratings
S
IDM
D
2
7
D
3
6
S
Power dissipation
PD
4
S
(1)
2.8
Power dissipation, TC = 25°C
S
W
69
TJ
Operating junction temperature
–55 to 150
°C
Tstg
Storage temperature
–55 to 150
°C
5
G
S
2
(1) Typical RθJA = 45°C/W on 1 inch Cu (2 oz.) on 0.060 inch
thick FR4 PCB.
(2) Max RθJC = 2.3°C/W, pulse duration ≤100 μs, duty cycle ≤1%
RDS(on) vs VGS
Gate Charge
8
TC = 25° C, I D = -10 A
TC = 125° C, I D = -10 A
21
-VGS - Gate-to-Source Voltage (V)
RDS(on) - On-State Resistance (m:)
24
18
15
12
9
6
3
0
ID = -10 A
VDS = -10 V
7
6
5
4
3
2
1
0
0
2
4
6
8
10
-VGS - Gate-To-Source Voltage (V)
12
D007
0
2
4
6
8
10
Qg - Gate Charge (nC)
12
14
D004
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
CSD25402Q3A
SLPS454B – DECEMBER 2013 – REVISED JANUARY 2016
www.ti.com
Table of Contents
1
2
3
4
5
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Specifications.........................................................
1
1
1
2
3
5.1 Electrical Characteristics........................................... 3
5.2 Thermal Information .................................................. 3
5.3 Typical MOSFET Characteristics.............................. 4
6
Device and Documentation Support.................... 7
6.1
6.2
6.3
6.4
7
Community Resources..............................................
Trademarks ...............................................................
Electrostatic Discharge Caution ................................
Glossary ....................................................................
7
7
7
7
Mechanical, Packaging, and Orderable
Information ............................................................. 8
7.1
7.2
7.3
7.4
Q3A Package Dimensions ........................................ 8
Q3A Recommended PCB Pattern ............................ 9
Q3A Recommended Stencil Pattern ......................... 9
Q3A Tape and Reel Information ............................. 10
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (July 2015) to Revision B
Page
•
Updated Package Dimensions drawing.................................................................................................................................. 8
•
Updated PCB drawing. .......................................................................................................................................................... 9
•
Updated Stencil Pattern drawing. .......................................................................................................................................... 9
Changes from Original (December 2013) to Revision A
Page
•
Added part number to title. .................................................................................................................................................... 1
•
Added 7-inch reel to Ordering Information table .................................................................................................................... 1
•
Lowered typical RθJA from 55 to 45°C/W in Absolute Maximum Ratings Table footnote. ..................................................... 1
•
Increased max pulsed current to –148 A. ............................................................................................................................. 1
•
Added line for max power dissipation with the case temperature held to 25°C in Absolute Maximum Ratings Table. ........ 1
•
Updated pulsed current conditions. ....................................................................................................................................... 1
•
Updated Figure 1 to a normalized RθJC curve. ...................................................................................................................... 4
•
Updated SOA in Figure 10 ..................................................................................................................................................... 6
2
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SLPS454B – DECEMBER 2013 – REVISED JANUARY 2016
5 Specifications
5.1 Electrical Characteristics
(TA = 25°C unless otherwise stated)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
STATIC CHARACTERISTICS
BVDSS
Drain-to-source voltage
VGS = 0 V, ID = –250 μA
IDSS
Drain-to-source leakage current
VGS = 0 V, VDS = –16 V
–1
μA
IGSS
Gate-to-source leakage current
VDS = 0 V, VGS = ±12 V
–100
nA
VGS(th)
Gate-to-source threshold voltage
VDS = VGS, ID = –250 μA
–20
–0.65
V
–0.90
–1.15
74
300
mΩ
VGS = –2.5 V, ID = –10 A
13.3
15.9
mΩ
VGS = –4.5 V, ID = –10 A
7.7
8.9
mΩ
VDS = –10 V, ID = –10 A
59
VGS = –1.8 V, ID = –1 A
RDS(on)
Drain-to-source on resistance
gfs
Transconductance
V
S
DYNAMIC CHARACTERISTICS
CISS
Input capacitance
VGS = 0 V, VDS = –10 V,
ƒ = 1 MHz
1380
1790
pF
COSS
Output capacitance
763
992
pF
CRSS
Reverse transfer capacitance
39
51
pF
RG
Series gate resistance
3.7
7.4
Ω
Qg
Gate charge total (–4.5 V)
7.5
9.7
nC
Qgd
Gate charge gate to drain
1.1
nC
Qgs
Gate charge gate to source
2.4
nC
Qg(th)
Gate charge at Vth
1.0
nC
QOSS
Output charge
7.6
nC
td(on)
Turn on delay time
10
ns
tr
Rise time
7
ns
td(off)
Turn off delay time
25
ns
tf
Fall time
12
ns
VDS = –10 V, ID = –10 A
VDS = –10 V, VGS = 0 V
VDS = –10 V, VGS = –4.5 V,
ID = –10 A , RG = 5 Ω
DIODE CHARACTERISTICS
VSD
Diode forward voltage
Qrr
Reverse recovery charge
trr
Reverse recovery time
IS = –10 A, VGS = 0 V
–0.8
VDS = –8.5 V, IF = –10 A,
di/dt = 200 A/μs
10.3
–1
nC
V
21
ns
5.2 Thermal Information
(TA = 25°C unless otherwise stated)
MAX
UNIT
RθJC
Junction-to-case thermal resistance (1)
THERMAL METRIC
2.3
°C/W
RθJA
Junction-to-ambient thermal resistance (1) (2)
55
°C/W
(1)
(2)
MIN
TYP
RθJC is determined with the device mounted on a 1 inch2 (6.45 cm2), 2 oz. (0.071 mm thick) Cu pad on a 1.5 inch × 1.5 inch (3.81 cm ×
3.81 cm), 0.06 inch (1.52 mm) thick FR4 PCB. RθJC is specified by design, whereas RθJA is determined by the user’s board design.
Device mounted on FR4 material with 1 inch2 (6.45 cm2), 2 oz. (0.071 mm thick) Cu.
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3
CSD25402Q3A
SLPS454B – DECEMBER 2013 – REVISED JANUARY 2016
GATE
www.ti.com
GATE
DRAIN
DRAIN
Max RθJA = 175°C/W
when mounted on
minimum pad area of
2 oz. Cu.
Max RθJA = 55°C/W
when mounted on
1 inch2 of 2 oz. Cu.
SOURCE
SOURCE
M0137-02
M0137-01
5.3 Typical MOSFET Characteristics
(TA = 25°C unless otherwise stated)
Figure 1. Transient Thermal Impedance
4
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SLPS454B – DECEMBER 2013 – REVISED JANUARY 2016
Typical MOSFET Characteristics (continued)
(TA = 25°C unless otherwise stated)
100
VGS = -1.8 V
VGS = -2.5 V
VGS = -4.5 V
90
80
70
60
50
40
30
20
10
TC = 125° C
TC = 25° C
TC = -55° C
90
-IDS - Drain-To-Source Current (A)
-IDS - Drain-to-Source Current (A)
100
80
70
60
50
40
30
20
10
0
0
0
0.2
0.4 0.6 0.8
1
1.2 1.4 1.6
-VDS - Drain-to-Source Voltage (V)
1.8
2
0
0.5
D002
1
1.5
2
2.5
3
-VGS - Gate-To-Source Voltage (V)
3.5
4
D003
VDS = –5 V
Figure 2. Saturation Characteristics
Figure 3. Transfer Characteristics
10000
7
6
C - Capacitance (pF)
-VGS - Gate-to-Source Voltage (V)
8
5
4
3
2
1000
Ciss = Cgd + Cgs
Coss = Cds + Cgd
Crss = Cgd
100
1
10
0
0
2
4
6
8
10
Qg - Gate Charge (nC)
ID = –10 A
12
0
14
2
4
D004
Figure 4. Gate Charge
20
D005
Figure 5. Capacitance
24
RDS(on) - On-State Resistance (m:)
1.2
-VGS(th) - Threshold Voltage (V)
18
VDS = –10 V
1.3
1.1
1
0.9
0.8
0.7
0.6
0.5
0.4
-75
6
8
10
12
14
16
-VDS - Drain-to-Source Voltage (V)
TC = 25° C, I D = -10 A
TC = 125° C, I D = -10 A
21
18
15
12
9
6
3
0
-50
-25
0
25
50
75 100
TC - Case Temperature (qC)
125
150
175
0
D006
2
4
6
8
10
-VGS - Gate-To-Source Voltage (V)
12
D007
ID = –250 µA
Figure 6. Threshold Voltage vs Temperature
Figure 7. On-State Resistance vs Gate-to-Source Voltage
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CSD25402Q3A
SLPS454B – DECEMBER 2013 – REVISED JANUARY 2016
www.ti.com
Typical MOSFET Characteristics (continued)
(TA = 25°C unless otherwise stated)
100
1.3
VGS = -2.5 V
VGS = -4.5 V
-ISD - Source-To-Drain Current (A)
Normalized On-State Resistance
1.4
1.2
1.1
1
0.9
0.8
0.7
-75
TC = 25qC
TC = 125qC
10
1
0.1
0.01
0.001
0.0001
-50
-25
0
25
50
75 100
TC - Case Temperature (qC)
125
150
0
175
0.2
0.4
0.6
0.8
-VSD - Source-To-Drain Voltage (V)
D008
1
D009
ID = –10 A
Figure 8. Normalized On-State Resistance vs Temperature
Figure 9. Typical Diode Forward Voltage
40
-IDS - Drain-to-Source Current (A)
-IDS - Drain-to-Source Current (A)
1000
100
10
1
DC
10 ms
0.1
0.1
1 ms
100 µs
1
10
-VDS - Drain-to-Source Voltage (V)
50
35
30
25
20
15
10
5
0
-50
-25
D010
0
25
50
75
100 125
TC - Case Temperature (qC)
150
175
D011
Single Pulse, Max RθJC = 2.3°C/W
Figure 10. Maximum Safe Operating Area
6
Figure 11. Maximum Drain Current vs Temperature
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SLPS454B – DECEMBER 2013 – REVISED JANUARY 2016
6 Device and Documentation Support
6.1 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
6.2 Trademarks
NexFET, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
6.3 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
6.4 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
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CSD25402Q3A
SLPS454B – DECEMBER 2013 – REVISED JANUARY 2016
www.ti.com
7 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
7.1 Q3A Package Dimensions
3.1
2.9
B
A
PIN 1 INDEX AREA
3.25
3.05
2X 0.15 MAX
2X (0.2)
3.5
TYP
3.1
C
0.9 MAX
SEATING PLANE
0.05
0.00
(0.2)
1.74±0.1
4X
0.52
0.32
0.565±0.1
(0.15) TYP
EXPOSED THERMAL PAD
NOTE 3
4
5
9
2X 1.95
2.45±0.1
0.65 TYP
8
1
4X
0.55
0.25
8X
4X 1.45
2X
NOTE 4
0.35
0.25
0.1
0.05
C B
C
A
4222499/A 12/2015
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning
and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical
performance.
4. Metalized features are supplier options and may not be on the package.
5. All dimensions do not include mold flash or protrusions.
8
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SLPS454B – DECEMBER 2013 – REVISED JANUARY 2016
7.2 Q3A Recommended PCB Pattern
(1.775)
PKG
0.05 MIN
ALL SIDES
(0.635)
TYP
(0.56)
4X (0.3)
4X (0.6)
1
8
4X (0.3)
(R0.05)
TYP
(0.975)
TYP
9
SYMM
(2.45)
3X (0.65)
3X (0.65)
4
5
(R0.05) TYP
SOLDER MASK
OPENING
(0.207)
METAL UNDER
SOLDER MASK
(0.245)
( 0.2) VIA
TYP
(0.905)
TYP
(1.55)
LAND PATTERN EXAMPLE
1. This package is designed to be soldered to a thermal pad on the board. For more information, see QFN/SON
PCB Attachment application report, SLUA271.
2. Vias are optional depending on application, refer to device data sheet. If some or all are implemented,
recommended via locations are shown.
text added for spacing
For recommended circuit layout for PCB designs, see application note SLPA005 – Reducing Ringing Through
PCB Layout Techniques.
7.3 Q3A Recommended Stencil Pattern
(0.905)
PKG
8X (0.6)
(0.208)
SOLDER MASK EDGE
1
8
8X (0.3)
(0.663)
SYMM
9
(1.325)
6X (0.65)
4X 1.125
5
4
(R0.05) TYP
4X 0.705
METAL
TYP
(3.1)
1. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525
may have alternate design recommendations.
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CSD25402Q3A
SLPS454B – DECEMBER 2013 – REVISED JANUARY 2016
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1.75 ±0.10
7.4 Q3A Tape and Reel Information
4.00 ±0.10 (See Note 1)
Ø 1.50
+0.10
–0.00
1.30
3.60
5.50 ±0.05
12.00
+0.30
–0.10
8.00 ±0.10
2.00 ±0.05
3.60
M0144-01
Notes: 1. 10-sprocket hole-pitch cumulative tolerance ±0.2
2. Camber not to exceed 1 mm in 100 mm, noncumulative over 250 mm
3. Material: black static-dissipative polystyrene
4. All dimensions are in mm, unless otherwise specified
5. Thickness: 0.30 ±0.05 mm
6. MSL1 260°C (IR and convection) PbF reflow compatible
10
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
CSD25402Q3A
ACTIVE
VSONP
DNH
8
2500
RoHS & Green
SN
Level-1-260C-UNLIM
-55 to 150
25402
CSD25402Q3AT
ACTIVE
VSONP
DNH
8
250
RoHS & Green
SN
Level-1-260C-UNLIM
-55 to 150
25402
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
