CSD25480F3

CSD25480F3 SLPS578B – APRIL 2016 – REVISED FEBRUARY 2022 CSD25480F3 –20-V P-Channel FemtoFET™ MOSFET 1 Features • • • • • • • Product Summary TA = 25°C Low on-resistance Ultra-low Qg and Qgd Ultra-small footprint – 0.73 mm × 0.64 mm Low profile – 0.36-mm max height Integrated ESD protection diode Lead and halogen free RoHS compliant • • –20 V Qg Gate Charge Total (–4.5 V) 0.7 nC Qgd Gate Charge Gate-to-Drain 0.10 nC RDS(on) Drain-to-Source On-Resistance VGS(th) Threshold Voltage VGS = –1.8 V 420 VGS = –2.5 V 203 VGS = –4.5 V 132 VGS = –8.0 V 110 –0.95 mΩ V Device Information(1) Optimized for load switch applications Optimized for general purpose switching applications Battery applications Handheld and mobile applications DEVICE QTY CSD25480F3 3000 CSD25480F3T (1) 3 Description 250 MEDIA PACKAGE SHIP 7-Inch Reel Femto 0.73-mm × 0.64-mm Land Grid Array (LGA) Tape and Reel For all available packages, see the orderable addendum at the end of the data sheet. Absolute Maximum Ratings This –20-V, 110-mΩ, P-Channel FemtoFET™ MOSFET is designed and optimized to minimize the footprint in many handheld and mobile applications. This technology is capable of replacing standard small signal MOSFETs while providing a substantial reduction in footprint size. TA = 25°C (unless otherwise stated) VALUE UNIT –20 V Gate-to-Source Voltage –12 V Continuous Drain Current(1) –1.7 A IDM Pulsed Drain Current(1) (2) –10.6 A PD Power Dissipation(1) 500 mW Human-Body Model (HBM) 4000 Charged-Device Model (CDM) 2000 VDS Drain-to-Source Voltage VGS ID V(ESD) 0.36 mm TJ, Tstg (1) (2) 0.64 mm UNIT Drain-to-Source Voltage 2 Applications • • TYPICAL VALUE VDS Operating Junction, Storage Temperature –55 to 150 V °C Typical RθJA = 255°C/W mounted on FR4 material with minimum Cu mounting area. Pulse duration ≤100 μs, duty cycle ≤1%. 0.73 mm Typical Part Dimensions............... G D S Top View......... An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. CSD25480F3 www.ti.com SLPS578B – APRIL 2016 – REVISED FEBRUARY 2022 Table of Contents 1 Features............................................................................1 2 Applications..................................................................... 1 3 Description.......................................................................1 4 Revision History.............................................................. 2 5 Specifications.................................................................. 3 5.1 Electrical Characteristics.............................................3 5.2 Thermal Information....................................................3 5.3 Typical MOSFET Characteristics................................ 4 6 Device and Documentation Support..............................7 6.1 Receiving Notification of Documentation Updates......7 6.2 Trademarks................................................................. 7 7 Mechanical, Packaging, and Orderable Information.... 8 7.1 Mechanical Dimensions.............................................. 8 7.2 Recommended Minimum PCB Layout........................9 7.3 Recommended Stencil Pattern................................... 9 4 Revision History Changes from Revision A (August 2017) to Revision B (February 2022) Page • Changed ultra-low profile bullet from 0.35 mm to 0.36 mm in height................................................................. 1 • Updated ultra-low profile image height from 0.35 mm to 0.36 mm..................................................................... 1 • Changed ultra-low profile image height from 0.35 mm to 0.36 mm.................................................................... 8 • Added FemtoFET Surface Mount Guide note.................................................................................................... 9 Changes from Revision * (April 2016) to Revision A (August 2017) Page • Added the Section 6.1 section in Section 6 ....................................................................................................... 7 • Added Recommended Minimum PCB Layout ................................................................................................... 9 • Updated the Section 7.3 .................................................................................................................................... 9 2 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: CSD25480F3 CSD25480F3 www.ti.com SLPS578B – APRIL 2016 – REVISED FEBRUARY 2022 5 Specifications 5.1 Electrical Characteristics TA = 25°C (unless otherwise stated) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT –50 nA STATIC CHARACTERISTICS BVDSS Drain-to-source voltage VGS = 0 V, IDS = –250 μA IDSS Drain-to-source leakage current VGS = 0 V, VDS = –16 V IGSS Gate-to-source leakage current VDS = 0 V, VGS = –12 V VGS(th) Gate-to-source threshold voltage VDS = VGS, IDS = –250 μA RDS(on) Drain-to-source on-resistance gfs Transconductance –20 V –25 nA –0.95 –1.20 V VGS = –1.8 V, IDS = –0.1 A 420 840 VGS = –2.5 V, IDS = –0.4 A 203 260 VGS = –4.5 V, IDS = –0.4 A 132 159 VGS = –8 V, IDS = –0.4 A 110 132 VDS = –10 V, IDS = –0.4 A 8.0 –0.70 mΩ S DYNAMIC CHARACTERISTICS Ciss Input capacitance 119 Coss Output capacitance Crss Reverse transfer capacitance RG Series gate resistance Qg Gate charge total (–4.5 V) Qgd Gate charge gate-to-drain Qgs Gate charge gate-to-source Qg(th) Gate charge at Vth Qoss Output charge td(on) tr td(off) Turnoff delay time tf Fall time VGS = 0 V, VDS = –10 V, ƒ = 1 MHz 155 pF 48 62 pF 3.6 4.7 pF 0.91 nC 16 0.70 Ω 0.10 nC 0.26 nC 0.15 nC 1.3 nC Turnon delay time 9 ns Rise time 5 ns 13 ns 7 ns VDS = –10 V, IDS = –0.4 A VDS = –10 V, VGS = 0 V VDS = –10 V, VGS = –4.5 V, IDS = –0.4 A, RG = 10 Ω DIODE CHARACTERISTICS VSD Diode forward voltage Qrr Reverse recovery charge trr Reverse recovery time ISD = –0.4 A, VGS = 0 V VDS= –10 V, IF = –0.4 A, di/dt = 100 A/μs –0.78 –1.0 V 1.2 nC 6.4 ns 5.2 Thermal Information TA = 25°C (unless otherwise stated) THERMAL METRIC RθJA (1) (2) TYPICAL VALUES resistance(1) 90 Junction-to-ambient thermal resistance(2) 255 Junction-to-ambient thermal UNIT °C/W Device mounted on FR4 material with 1-in2 (6.45-cm2), 2-oz. (0.071-mm) thick Cu. Device mounted on FR4 material with minimum Cu mounting area. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: CSD25480F3 3 CSD25480F3 www.ti.com SLPS578B – APRIL 2016 – REVISED FEBRUARY 2022 5.3 Typical MOSFET Characteristics 10 5 9 4.5 -IDS - Drain-To-Source Current (A) -IDS - Drain-to-Source Current (A) TA = 25°C (unless otherwise stated) 8 7 6 5 4 3 2 VGS = -2.5 V VGS = -4.5 V VGS = -8.0 V 1 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 -VDS - Drain-to-Source Voltage (V) 1.8 4 3.5 3 2.5 2 1.5 1 0.5 0 0 0 TC = 125° C TC = 25° C TC = -55° C 2 0 0.5 D002 1 1.5 2 2.5 -VGS - Gate-To-Source Voltage (V) Figure 5-1. Saturation Characteristics 3 D003 VDS = –5 V Figure 5-2. Transfer Characteristics Figure 5-3. Transient Thermal Impedance 4 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: CSD25480F3 CSD25480F3 www.ti.com SLPS578B – APRIL 2016 – REVISED FEBRUARY 2022 1000 Ciss = Cgd + Cgs Coss = Cds + Cgd Crss = Cgd 7 6 C - Capacitance (pF) -VGS - Gate-to-Source Voltage (V) 8 5 4 3 2 100 10 1 2 0 0 0.2 0.4 0.6 0.8 1 Qg - Gate Charge (nC) ID = –0.4 A 1.2 0 1.4 2 D004 4 6 8 10 12 14 16 -VDS - Drain-to-Source Voltage (V) 18 20 D005 Figure 5-5. Capacitance VDS = –10 V Figure 5-4. Gate Charge 400 RDS(on) - On-State Resistance (m:) -VGS(th) - Threshold Voltage (V) 1.25 1.15 1.05 0.95 0.85 0.75 0.65 0.55 -75 -50 -25 0 25 50 75 100 TC - Case Temperature (qC) 125 150 200 150 100 50 0 2 4 6 8 10 -VGS - Gate-To-Source Voltage (V) 12 D007 Figure 5-7. On-State Resistance vs Gate-to-Source Voltage 1.4 10 VGS = -2.5 V VGS = -8.0 V -ISD - Source-To-Drain Current (A) Normalized On-State Resistance 250 D006 Figure 5-6. Threshold Voltage vs Temperature 1.2 1.1 1 0.9 0.8 0.7 -75 300 0 175 ID = –250 µA 1.3 TC = 25° C, ID = -0.4 A TC = 125° C, ID = -0.4 A 350 TC = 25qC TC = 125qC 1 0.1 0.01 0.001 0.0001 0 -50 -25 0 25 50 75 100 TC - Case Temperature (qC) 125 150 175 D008 ID = –0.4 A 0.2 0.4 0.6 0.8 -VSD - Source-To-Drain Voltage (V) 1 D009 Figure 5-9. Typical Diode Forward Voltage Figure 5-8. Normalized On-State Resistance vs Temperature Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: CSD25480F3 5 CSD25480F3 www.ti.com SLPS578B – APRIL 2016 – REVISED FEBRUARY 2022 3 -IDS - Drain-to-Source Current (A) -IDS - Drain-To-Source Current (A) 100 10 1 0.1 100 ms 10 ms 0.01 0.1 1 ms 100 µs 10 µs 1 10 -VDS - Drain-To-Source Voltage (V) 100 2 1.5 1 0.5 0 -50 -25 D010 Single pulse, max RθJA = 245°C/W Figure 5-10. Maximum Safe Operating Area 6 2.5 0 25 50 75 100 125 TA - Ambient Temperature (qC) 150 175 D011 Figure 5-11. Maximum Drain Current vs Temperature Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: CSD25480F3 CSD25480F3 www.ti.com SLPS578B – APRIL 2016 – REVISED FEBRUARY 2022 6 Device and Documentation Support 6.1 Receiving Notification of Documentation Updates To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. 6.2 Trademarks FemtoFET™ is a trademark of Texas Instruments. All trademarks are the property of their respective owners. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: CSD25480F3 7 CSD25480F3 www.ti.com SLPS578B – APRIL 2016 – REVISED FEBRUARY 2022 7 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 7.1 Mechanical Dimensions 0.73 0.65 A B PIN 1 INDEX AREA 0.64 0.56 0.36 MAX C SEATING PLANE 0.4 0.225 2 3 0.175 0.51 0.49 0.35 1 0.015 0.16 2X 0.14 C B A 2X A. B. C. 0.16 0.14 0.015 C A B 0.26 0.24 All linear dimensions are in millimeters (dimensions and tolerancing per AME T14.5M-1994). This drawing is subject to change without notice. This package is a lead-free solder land design. Table 7-1. Pin Configuration 8 POSITION DESIGNATION Pin 1 Gate Pin 2 Source Pin 3 Drain Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: CSD25480F3 CSD25480F3 www.ti.com SLPS578B – APRIL 2016 – REVISED FEBRUARY 2022 7.2 Recommended Minimum PCB Layout (0.15) 2X (0.25) 2X (0.15) 0.05 MIN ALL AROUND TYP 1 3 SYMM (0.35) (0.5) EXAMPLE STENCIL DESIGN 2 YJM0003A (R0.05) TYP SOLDER MASK TM PicoStar OPENING TYP PKG METAL UNDER SOLDER MASK TYP (0.175) - 0.35 mm max height PicoStar TM (0.4) A. B. All dimensions are in millimeters. LAND PATTERN EXAMPLE SOLDER MASK DEFINED For more information, see FemtoFET Surface Mount Guide (SLRA003D). SCALE:50X 7.3 Recommended Stencil Pattern 2X (0.25) 2X (0.2) (0.15) 1 3 SYMM (0.4) 2X (0.15) (0.5) 2 PKG (R0.05) TYP 2X SOLDER MASK EDGE (0.175) (0.4) A. 4222304/A 09/2015 All dimensions are in millimeters. NOTES: (continued) SOLDER PASTE EXAMPLE ON 0.075 - 0.1 mm THICK STENCIL 4. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). SCALE:50X www.ti.com Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: CSD25480F3 9 PACKAGE MATERIALS INFORMATION www.ti.com 8-Sep-2021 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) CSD25480F3 PICOST AR YJM 3 3000 180.0 8.4 CSD25480F3 PICOST AR YJM 3 3000 178.0 CSD25480F3T PICOST AR YJM 3 250 CSD25480F3T PICOST AR YJM 3 250 0.7 0.79 0.44 4.0 8.0 Q2 8.4 0.7 0.79 0.44 4.0 8.0 Q2 178.0 8.4 0.7 0.79 0.44 4.0 8.0 Q2 180.0 8.4 0.7 0.79 0.44 4.0 8.0 Q2 Pack Materials-Page 1 W Pin1 (mm) Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 8-Sep-2021 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) CSD25480F3 PICOSTAR YJM 3 3000 182.0 182.0 20.0 CSD25480F3 PICOSTAR YJM 3 3000 220.0 220.0 35.0 CSD25480F3T PICOSTAR YJM 3 250 220.0 220.0 35.0 CSD25480F3T PICOSTAR YJM 3 250 182.0 182.0 20.0 Pack Materials-Page 2 IMPORTANT NOTICE AND DISCLAIMER TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. 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