CSD25481F4T

CSD25481F4 SLPS420F – SEPTEMBER 2013 – REVISED FEBRUARY 2022 CSD25481F4 20 V P-Channel FemtoFET™ MOSFET Product Summary 1 Features • • • • • • • • TA = 25°C Ultra-low on resistance Ultra-low Qg and Qgd High operating drain current Ultra-small footprint (0402 Case Size) – 1 mm × 0.6 mm Ultra-low profile – 0.36 mm max height Integrated ESD protection diode – Rated >4 kV HBM – Rated >2 kV CDM Lead and halogen free RoHS compliant • • • • Optimized for load switch applications Optimized for general purpose switching applications Battery applications Handheld and mobile applications 3 Description This 90-mΩ, 20-V P-Channel FemtoFET™ MOSFET is designed and optimized to minimize the footprint in many handheld and mobile applications. This technology is capable of replacing standard small signal MOSFETs while providing at least a 60% reduction in footprint size. . Drain-to-Source Voltage –20 V Qg Gate Charge Total (–4.5 V) 913 pC Qgd Gate Charge Gate-to-Drain RDS(on) Drain-to-Source On-Resistance VGS(th) Threshold Voltage pC 395 mΩ VGS = –2.5 V 145 mΩ VGS = –4.5 V 90 mΩ V Ordering Information Qty Media CSD25481F4 3000 7-Inch Reel 250 7-Inch Reel (1) Package Ship Femto(0402) 1.0 mm × 0.6 mm Land Grid Array (LGA) Tape and Reel For all available packages, see the orderable addendum at the end of the data sheet. Absolute Maximum Ratings TA = 25°C unless otherwise stated VALUE UNIT VDS Drain-to-Source Voltage –20 V VGS Gate-to-Source Voltage –12 V ID Continuous Drain Current(1) –2.5 A –13.1 A IDM IG PD V(ESD) (1) (2) 0.60 mm 153 VGS = –1.8 V –0.95 Device(1) TJ, Tstg 0.36 mm UNIT VDS CSD25481F4T 2 Applications TYPICAL VALUE Pulsed Drain Current(2) Continuous Gate Clamp Current –35 Pulsed Gate Clamp Current(2) –350 Power Dissipation(1) mA 500 mW Human Body Model (HBM) 4 kV Charged Device Model (CDM) 2 kV –55 to 150 °C Operating Junction and Storage Temperature Range Typical RθJA = 90°C/W on 1 inch2 (6.45 cm2), 2 oz. (0.071 mm thick) Cu pad on a 0.06 inch (1.52 mm) thick FR4 PCB. Pulse duration ≤ 100 μs, duty cycle ≤ 1%. 1.00 mm D Figure 3-1. Typical Part Dimensions . . G S Figure 3-2. Top View An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. CSD25481F4 www.ti.com SLPS420F – SEPTEMBER 2013 – REVISED FEBRUARY 2022 Table of Contents 1 Features............................................................................1 2 Applications..................................................................... 1 3 Description.......................................................................1 4 Revision History.............................................................. 2 5 Specifications.................................................................. 3 5.1 Electrical Characteristics.............................................3 5.2 Thermal Information....................................................3 5.3 Typical MOSFET Characteristics................................ 4 6 Device and Documentation Support..............................7 6.1 Support Resources..................................................... 7 6.2 Trademarks................................................................. 7 6.3 Electrostatic Discharge Caution..................................7 6.4 Glossary......................................................................7 7 Mechanical, Packaging, and Orderable Information.... 8 7.1 Mechanical Dimensions.............................................. 8 7.2 Recommended Minimum PCB Layout........................9 7.3 Recommended Stencil Pattern................................... 9 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision E (December 2017) to Revision F (February 2022) Page • Changed ultra-low profile bullet from 0.35 mm to 0.36 mm in height................................................................. 1 • Updated ultra-low profile image height from 0.35 mm to 0.36 mm..................................................................... 1 • Changed ultra-low profile image height from 0.35 mm to 0.36 mm.................................................................... 8 • Added FemtoFET Surface Mount Guide note.................................................................................................... 9 Changes from Revision D (October 2014) to Revision E (December 2017) Page • Changed the Pulsed Drain Current value From: –10 A To: –13.1 A in the Absolute Maximum Ratings table ...1 • Changed Note 1 From: Typical RθJA = 85°C/W To: Typical RθJA = 90°C/W....................................................... 1 • Changed Note 2 From: Pulse duration ≤ 300 μs, duty cycle ≤ 2% To: Pulse duration ≤ 100 μs, duty cycle ≤ 1% ......................................................................................................................................................................1 • Changed the typical RθJA values in the Thermal Information table ....................................................................3 • Updated Figure 5-1. ...........................................................................................................................................4 • Updated Figure 5-10 with newly measured data. .............................................................................................. 4 • Updated all mechanical drawings, increased the size of the pads in the Section 7.3 section. .......................... 8 2 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: CSD25481F4 CSD25481F4 www.ti.com SLPS420F – SEPTEMBER 2013 – REVISED FEBRUARY 2022 5 Specifications 5.1 Electrical Characteristics (TA = 25°C unless otherwise stated) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT –100 nA STATIC CHARACTERISTICS BVDSS Drain-to-Source Voltage VGS = 0 V, IDS = –250 μA IDSS Drain-to-Source Leakage Current VGS = 0 V, VDS = –16 V IGSS Gate-to-Source Leakage Current VDS = 0 V, VGS = –12 V VGS(th) Gate-to-Source Threshold Voltage VDS = VGS, IDS = –250 μA RDS(on) gfs Drain-to-Source On-Resistance Transconductance –20 V –50 nA –0.95 –1.2 V VGS = –1.8 V, IDS = –0.1 A 395 800 mΩ VGS = –2.5 V, IDS = –0.5 A 145 174 mΩ VGS = –4.5 V, IDS = –0.5 A 90 105 mΩ VGS = –8 V, IDS = –0.5 A 75 88 mΩ VDS = –10 V, IDS = –0.5 A 3.3 S 189 pF 78 pF 5.5 pF –0.7 DYNAMIC CHARACTERISTICS Ciss Input Capacitance Coss Output Capacitance Crss Reverse Transfer Capacitance RG Series Gate Resistance Qg Gate Charge Total (4.5 V) Qgd Gate Charge Gate-to-Drain Qgs Gate Charge Gate-to-Source Qg(th) Gate Charge at Vth Qoss Output Charge td(on) tr td(off) Turn Off Delay Time tf Fall Time VGS = 0 V, VDS = –10 V, ƒ = 1 MHz VDS = –10 V, IDS = –0.5 A 20 Ω 913 pC 153 pC 240 pC 116 pC 1030 pC Turn On Delay Time 4.1 ns Rise Time 3.6 ns 16.9 ns 6.7 ns –0.75 V 1010 pC 7.5 ns VDS = –10 V, VGS = 0 V VDS = –10 V, VGS = –4.5 V, IDS = –0.5 A,RG = 2 Ω DIODE CHARACTERISTICS VSD Diode Forward Voltage Qrr Reverse Recovery Charge trr Reverse Recovery Time ISD = –0.5 A, VGS = 0 V VDS= –10 V, IF = –0.5 A, di/dt = 100 A/μs 5.2 Thermal Information (TA = 25°C unless otherwise stated) THERMAL METRIC RθJA (1) (2) TYPICAL VALUES Resistance(1) 90 Junction-to-Ambient Thermal Resistance(2) 250 Junction-to-Ambient Thermal UNIT °C/W Device mounted on FR4 material with 1 inch2 (6.45 cm2), 2 oz. (0.071 mm thick) Cu. Device mounted on FR4 material with minimum Cu mounting area. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: CSD25481F4 3 CSD25481F4 www.ti.com SLPS420F – SEPTEMBER 2013 – REVISED FEBRUARY 2022 5.3 Typical MOSFET Characteristics (TA = 25°C unless otherwise stated) Figure 5-1. Transient Thermal Impedance 10 VGS = −8V VGS = −4.5V VGS = −2.5V VGS = −1.8V 9 8 7 − IDS - Drain-to-Source Current (A) − IDS - Drain-to-Source Current (A) 10 6 5 4 3 2 1 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 − VDS - Drain-to-Source Voltage (V) 1.8 Figure 5-2. Saturation Characteristics 4 2 VDS = −5V 9 8 7 6 5 4 3 TC = 125°C TC = 25°C TC = −55°C 2 1 0 0 G001 0.5 1 1.5 2 2.5 3 − VGS - Gate-to-Source Voltage (V) 3.5 4 G001 Figure 5-3. Transfer Characteristics Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: CSD25481F4 CSD25481F4 www.ti.com SLPS420F – SEPTEMBER 2013 – REVISED FEBRUARY 2022 200 ID = −0.5A VDS = −10V 7 180 160 6 C − Capacitance (pF) − VGS - Gate-to-Source Voltage (V) 8 5 4 3 2 120 100 80 60 40 1 0 Ciss = Cgd + Cgs Coss = Cds + Cgd Crss = Cgd 140 20 0 0.2 0.4 0.6 0.8 1 1.2 Qg - Gate Charge (nC) 1.4 0 1.6 0 Figure 5-4. Gate Charge RDS(on) - On-State Resistance (mΩ) − VGS(th) - Threshold Voltage (V) 1.15 1.05 0.95 0.85 0.75 0.65 0.55 −25 25 75 125 TC - Case Temperature (ºC) 20 G001 TC = 25°C, ID = −0.5A TC = 125°C, ID = −0.5A 360 320 280 240 200 160 120 80 40 0 175 0 G001 Figure 5-6. Threshold Voltage vs Temperature 2 4 6 8 10 − VGS - Gate-to- Source Voltage (V) 12 G001 Figure 5-7. On-State Resistance vs Gate-to-Source Voltage 1.4 10 VGS = −4.5V, ID = −0.5A − ISD − Source-to-Drain Current (A) Normalized On-State Resistance 18 400 ID = −250uA 1.3 1.2 1.1 1 0.9 0.8 0.7 −75 4 6 8 10 12 14 16 − VDS - Drain-to-Source Voltage (V) Figure 5-5. Capacitance 1.25 0.45 −75 2 G001 −25 25 75 125 TC - Case Temperature (ºC) 175 TC = 25°C TC = 125°C 1 0.1 0.01 0.001 0.0001 0 G001 Figure 5-8. Normalized On-State Resistance vs Temperature 0.2 0.4 0.6 0.8 − VSD − Source-to-Drain Voltage (V) 1 G001 Figure 5-9. Typical Diode Forward Voltage Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: CSD25481F4 5 CSD25481F4 www.ti.com SLPS420F – SEPTEMBER 2013 – REVISED FEBRUARY 2022 5.0 -IDS - Drain-to-Source Current (A) -IDS - Drain-To-Source Current (A) 100 10 1 0.1 100 ms 10 ms 0.01 0.1 1 ms 100 µs 1 10 -VDS - Drain-To-Source Voltage (V) 50 4.5 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 -50 -25 D010 Single Pulse Typical RθJA =250°C/W (min Cu) Figure 5-10. Maximum Safe Operating Area 6 0 25 50 75 100 125 TC - Case Temperature (qC) 150 175 D011 Typical RθJA = 90°C/W (max Cu) Figure 5-11. Maximum Drain Current vs Temperature Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: CSD25481F4 CSD25481F4 www.ti.com SLPS420F – SEPTEMBER 2013 – REVISED FEBRUARY 2022 6 Device and Documentation Support 6.1 Support Resources TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. 6.2 Trademarks FemtoFET™ is a trademark of Texas Instruments. TI E2E™ are trademarks of Texas Instruments. All trademarks are the property of their respective owners. 6.3 Electrostatic Discharge Caution This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 6.4 Glossary TI Glossary This glossary lists and explains terms, acronyms, and definitions. Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: CSD25481F4 7 CSD25481F4 www.ti.com SLPS420F – SEPTEMBER 2013 – REVISED FEBRUARY 2022 7 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 7.1 Mechanical Dimensions 1.04 0.96 A B PIN 1 INDEX AREA 0.64 0.56 0.36 MAX C SEATING PLANE 0.65 0.325 0.175 2 3 0.35 0.51 0.49 1 0.015 A. B. C. 0.16 2X 0.14 C B A 2X 0.26 0.24 0.26 0.24 0.015 C A B All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. This drawing is subject to change without notice. This package is a Pb-free bump design. Bump finish may vary. To determine the exact finish, refer to the device data sheet or contact a local TI representative. Table 7-1. Pin Configuration 8 Position Designation Pin 1 Gate Pin 2 Source Pin 3 Drain Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: CSD25481F4 CSD25481F4 www.ti.com SLPS420F – SEPTEMBER 2013 – REVISED FEBRUARY 2022 7.2 Recommended Minimum PCB Layout (0.25) 2X (0.25) PKG 0.05 MIN ALL AROUND 2X (0.15) 1 3 SYMM (0.35) (0.5) EXAMPLE STENCIL DESIGN 2 YJC0003A(R0.05) TYP TM PicoStar - 0.35 mm max height SOLDER MASK OPENING (0.65) LAND PATTERN EXAMPLE A. B. PicoStar TM METAL UNDER SOLDER MASK SOLDER MASK DEFINED SCALE:50X All dimensions are in millimeters. For more information, see FemtoFET Surface Mount Guide (SLRA003D). 7.3 Recommended Stencil Pattern 2X (0.25) 2X (0.2) PKG (0.25) 1 SYMM (0.4) (0.5) 3 2 2X (0.15) (R0.05) TYP (0.65) 2X SOLDER MASK EDGE SOLDER PASTE EXAMPLE A. B. BASED ON 0.075 - 0.1 mm THICK STENCIL All dimensions are in millimeters. SCALE:50X Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design 4220651/B 08/2015 recommendations. NOTES: (continued) 4. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). www.ti.com Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: CSD25481F4 9 PACKAGE OPTION ADDENDUM www.ti.com 11-Jan-2022 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) CSD25481F4 ACTIVE PICOSTAR YJC 3 3000 RoHS & Green NIAU Level-1-260C-UNLIM -55 to 150 CS CSD25481F4T ACTIVE PICOSTAR YJC 3 250 RoHS & Green NIAU Level-1-260C-UNLIM -55 to 150 CS (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of