CSD75204W15
www.ti.com
SLPS221A – OCTOBER 2009 – REVISED OCTOBER 2010
Dual P-Channel NexFET™ Power MOSFET
Check for Samples: CSD75204W15
FEATURES
1
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•
•
•
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PRODUCT SUMMARY
Dual P-Ch MOSFETs
Common Source Configuration
Small Footprint 1.5-mm × 1.5-mm
Gate-Source Voltage Clamp
Gate ESD Protection –3kV
Pb Free
RoHS Compliant
Halogen Free
VD1D2
Drain to Drain Voltage
–20
V
Qg
Gate Charge Total (-4.5V)
2.8
nC
Qgd
Gate Charge Gate to Drain
RD1D2(on) Drain to Drain On Resistance
VGS(th)
nC
140
mΩ
VGS = –2.5V
105
mΩ
VGS = –4.5V
80
mΩ
Threshold Voltage
–0.7
V
ORDERING INFORMATION
Device
Package
Media
CSD75204W15
1.5-mm × 1.5-mm
Wafer Level Package
7-Inch
Reel
APPLICATIONS
•
•
0.6
VGS = –1.8V
Battery Management
Battery Protection
Qty
Ship
3000
Tape and
Reel
ABSOLUTE MAXIMUM RATINGS
DESCRIPTION
TA = 25°C unless otherwise stated
The device has been designed to deliver the lowest
on resistance and gate charge in the smallest outline
possible with excellent thermal characteristics in an
ultra low profile. Low on resistance coupled with the
small footprint and low profile make the device ideal
for battery operated space constrained applications.
VGS
ID1D2
IS
Top View
IG
G1
D1
D2
D1
G2
D2
D2
UNIT
–20
V
Gate to Source Voltage
-6
V
Continuous Drain to Drain Current,
TC = 25°C(1)
–3
A
Pulsed Drain to Drain Current,
TC = 25°C(2)
-28
A
Continuous Source Pin Current
-1.2
A
Pulsed Source Pin Current(2)
-15
A
Continuous Gate Clamp Current
-0.5
A
(2)
Pulsed Gate Clamp Current
-7
A
PD
Power Dissipation(1)
0.7
W
TJ,
TSTG
Operating Junction and Storage
Temperature Range
–55 to 150
°C
D1
SS
VALUE
VD1D2 Drain to Drain Voltage
(1) Per device, both sides in conduction
(2) Pulse duration 10ms, duty cycle ≤2%
P0109-01
Gate Charge (Per MOSFET)
300
6
ID1D2 = −1A
−VGS − Gate to Source Voltage − V
RD1D2(on) − On-State Resistance − mΩ
RD1D2(on) vs VGS
250
200
TJ = 125°C
TJ = 25°C
150
100
50
0
0
1
2
3
4
−VGS − Gate to Source Voltage − V
5
6
G006
5
ID1D2 = −1A
VD1D2 = −10V
4
3
2
1
0
0.0
0.5
1.0
1.5
2.0
Qg − Gate Charge − nC
2.5
3.0
G003
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2009–2010, Texas Instruments Incorporated
CSD75204W15
SLPS221A – OCTOBER 2009 – REVISED OCTOBER 2010
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ELECTRICAL CHARACTERISTICS
(TA = 25°C unless otherwise stated). Specifications and graphs are Per MOSFET unless otherwise stated. Drain to Drain
measurements are done with both MOSFETs in series (common source configuration.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Static Characteristics
BVD1D2
Drain to Drain Voltage
VGS = 0V, ID1D2 = –250mA
–20
BVGSS
Gate to Source Voltage
VD1D2 = 0V, IG = -250mA
-6.1
IDDS
Drain to Drain Leakage Current
VGS = 0V, VD1D2 = –16V
IGSS
Gate to Source Leakage Current
VD1D2 = 0V, VGS = -6V
VGS(th)
Gate to Source Threshold Voltage
VD1D2 = VGS, IDS = –250mA
RD1D2(on)
Drain to Drain On Resistance
gfs
Transconductance
–0.5
V
-7.2
V
–1
mA
–100
nA
–0.7
–0.9
V
VGS = –1.8V, ID1D2 = –1A
140
175
mΩ
VGS = –2.5V, ID1D2 = –1A
105
130
mΩ
VGS = –4.5V, ID1D2 = –1A
80
100
mΩ
VD1D2 = –10V, ID1D2 = –1A
5.3
S
Dynamic Characteristics
CISS
Input Capacitance
COSS
Output Capacitance
315
410
pF
128
165
CRSS
pF
Reverse Transfer Capacitance
43
55
pF
Qg
Gate Charge Total (–4.5V)
2.8
3.9
nC
Qgd
Gate Charge - Gate to Drain
Qgs
Gate Charge - Gate to Source
Qg(th)
Gate Charge at Vth
QOSS
Output Charge
td(on)
Turn On Delay Time
tr
Rise Time
td(off)
Turn Off Delay Time
tf
Fall Time
VGS = 0V, VD1D2 = –10V,
f = 1MHz
VD1D2 = –10V,
ID1D2 = –1A
VD1D2 = –9.5V, VGS = 0V
VD1D2 = –10V, VGS = –4.5V,
ID1D2 = –1A, RG = 30Ω
0.6
nC
0.5
nC
0.2
nC
2.2
nC
7.8
ns
6.7
ns
45
ns
26
ns
Diode Characteristics
VSD
Diode Forward Voltage
ID1D2 = –1A, VGS = 0V
0.75
1
V
Qrr
Reverse Recovery Charge
Vdd = –9.5V, IF = –1A, di/dt = 200A/ms
10.5
nC
trr
Reverse Recovery Time
Vdd = –9.5V, IF = –1A, di/dt = 200A/ms
23
ns
THERMAL CHARACTERISTICS
(TA = 25°C unless otherwise stated)
PARAMETER
R qJA
(1)
(2)
(3)
2
Thermal Resistance Junction to Ambient
Thermal Resistance Junction to Ambient
(1) (2)
(3) (2)
MIN
TYP
MAX
UNIT
200
°C/W
94
°C/W
Device mounted on FR4 material with Minimum Cu mounting area.
Measured with both devices biased in a parallel condition.
Device mounted on FR4 material with 1-inch2 of Cu (2oz).
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CSD75204W15
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SLPS221A – OCTOBER 2009 – REVISED OCTOBER 2010
Max RqJA = 94°C/W
when mounted on
1 inch2 (6.45 cm2) of
2-oz. (0.071-mm thick)
Cu.
G1 S G2 D2 D1
Max RqJA = 200°C/W
when mounted on
minimum pad area of
2-oz. (0.071-mm thick)
Cu.
G1 S G2 D2 D1
M0169-01
M0170-01
TYPICAL MOSFET CHARACTERISTICS
Graphs are Per MOSFET at TA = 25°C, unless stated otherwise. Drain to Drain measurements are done with both MOSFETs
in series (common source configuration).
ZθJA − Normalized Thermal Impedance
10
1
0.5
0.3
0.1
0.1
0.05
Duty Cycle = t1/t2
0.02
0.01
0.01
P
t1
Single Pulse
t2
0.001
Typical RqJA = 161oC/W (min Cu)
TJ = P x ZqJA x RqJA
0.0001
0.0001
0.001
0.01
0.1
1
10
100
t P − Pulse Duration − s
1k
G012
Figure 1. Transient Thermal Impedance
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CSD75204W15
SLPS221A – OCTOBER 2009 – REVISED OCTOBER 2010
www.ti.com
TYPICAL MOSFET CHARACTERISTICS (continued)
Graphs are Per MOSFET at TA = 25°C, unless stated otherwise. Drain to Drain measurements are done with both MOSFETs
in series (common source configuration).
5.0
−ID1D2 − Drain to Drain Current − A
−ID1D2 − Drain to Drain Current − A
5.0
4.5
4.0
VGS = −1.8V
VGS = −2V
3.5
3.0
2.5
2.0
VGS = −1.5V
VGS = −2.5V
1.5
1.0
VGS = −4.5V
0.5
0.0
0.0
0.5
1.0
1.5
2.0
2.5
4.0
3.5
TJ = 125°C
3.0
2.5
2.0
TJ = 25°C
1.5
1.0
TJ = −55°C
0.5
0.0
0.50
3.0
−VD1D2 − Drain to Drain Voltage − V
VD1D2 = −5V
4.5
0.75
C − Capacitance − pF
−VGS − Gate to Source Voltage − V
3
2
1
300
250
COSS = CDS + CGD
CISS = CGD + CGS
200
150
CRSS = CGD
100
50
0
0.5
1.0
1.5
2.0
2.5
3.0
0
5
RD1D2(on) − On-State Resistance − mΩ
ID1D2 = −250µA
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
−25
25
75
15
20
G004
Figure 5. Capacitance
1.0
0.9
10
−VD1D2 − Drain to Drain Voltage − V
G003
Figure 4. Gate Charge
−VGS(th) − Threshold Voltage − V
G002
f = 1MHz
VGS = 0V
350
Qg − Gate Charge − nC
125
175
TJ − Junction Temperature − °C
300
ID1D2 = −1A
250
200
TJ = 125°C
TJ = 25°C
150
100
50
0
0
1
2
3
4
−VGS − Gate to Source Voltage − V
G005
Figure 6. Threshold Voltage vs. Temperature
4
1.75
400
ID1D2 = −1A
VD1D2 = −10V
4
0.0
−75
1.50
Figure 3. Transfer Characteristics
6
0
0.0
1.25
−VGS − Gate to Source Voltage − V
G001
Figure 2. Saturation Characteristics
5
1.00
5
6
G006
Figure 7. On-State Resistance vs. Gate to Source Voltage
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Copyright © 2009–2010, Texas Instruments Incorporated
Product Folder Link(s): CSD75204W15
CSD75204W15
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SLPS221A – OCTOBER 2009 – REVISED OCTOBER 2010
TYPICAL MOSFET CHARACTERISTICS (continued)
Graphs are Per MOSFET at TA = 25°C, unless stated otherwise. Drain to Drain measurements are done with both MOSFETs
in series (common source configuration).
10
1.4
ID1D2 = −1A
VGS = −4.5V
−ISD − Source to Drain Current − A
Normalized On-State Resistance
1.6
1.2
1.0
0.8
0.6
0.4
0.2
0.0
−75
TJ = 125°C
1
0.1
TJ = 25°C
0.01
0.001
0.0001
−25
25
75
125
TJ − Case Temperature − °C
175
0.0
0.8
1.0
1.2
1.4
G008
4.5
−ID1D2 − Drain to Drain Current − A
−ID1D2 − Drain to Drain Current − A
0.6
Figure 9. Typical Diode Forward Voltage
100
10
1ms
1
10ms
0.01
0.1
0.4
−VSD − Source to Drain Voltage − V
G007
Figure 8. Normalized On-State Resistance vs. Temperature
0.1
0.2
Area Limited
by RD1D2(on)
100ms
Single Pulse
Typical RqJA = 161oC/W (min Cu)
1
DC
10
100
−VD1D2 − Drain to Drain Voltage − V
Figure 10. Maximum Safe Operating Area
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
−50
−25
0
25
50
75
100
125
150
175
TJ − Junction Temperature − °C
G009
G011
Figure 11. Maximum Drain Current vs. Temperature
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CSD75204W15
SLPS221A – OCTOBER 2009 – REVISED OCTOBER 2010
www.ti.com
MECHANICAL DATA
CSD75204W15 Package Dimensions
Solder Ball
Ø 0.31 ±0.075
Pin 1
Mark
1
2
3
2
3
1
A
B
1.50
B
1.00
+0.00
–0.08
0.50
A
C
C
1.50
+0.00
–0.08
0.62 Max
Top View
0.50
Bottom View
0.04
0.62 Max
0.35 ±0.10
Side View
Seating Plate
Front View
M0171-01
NOTE: All dimensions are in mm (unless otherwise specified)
Pinout
POSITION
6
DESIGNATION
A1
Gate1
A2, A3, B3
Drain1
C1
Gate2
C2, C3, B2
Drain2
B1
Source Sense
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Copyright © 2009–2010, Texas Instruments Incorporated
Product Folder Link(s): CSD75204W15
CSD75204W15
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SLPS221A – OCTOBER 2009 – REVISED OCTOBER 2010
Land Pattern Recommendation
Ø 0.25
1
2
3
1.00
0.50
A
B
C
0.50
M0172-01
NOTE: All dimensions are in mm (unless otherwise specified)
Tape and Reel Information
4.00 ±0.10
Ø 1.50 ±0.10
4.00 ±0.10
Ø 0.50 ±0.05
0.86 ±0.05
1.60 ±0.05
5° Max
3.50 ±0.05
8.00
+0.30
–0.10
1.75 ±0.10
2.00 ±0.05
0.254 ±0.02
1.60 ±0.05
5° Max
M0173-01
NOTE: All dimensions are in mm (unless otherwise specified)
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CSD75204W15
SLPS221A – OCTOBER 2009 – REVISED OCTOBER 2010
www.ti.com
REVISION HISTORY
Changes from Original (October 2009) to Revision A
•
8
Page
Deleted the Package Marking Information sectiom .............................................................................................................. 7
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Product Folder Link(s): CSD75204W15
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