CSD85312Q3E

CSD85312Q3E www.ti.com SLPS457 – NOVEMBER 2013 Dual 20 V N-Channel NexFET™ Power MOSFETs FEATURES . 1 • • • • • • • • • Common Source Connection Low Drain to Drain On-Resistance Space Saving SON 3.3 x 3.3 mm Plastic Package Optimized for 5 V Gate Drive Low Thermal Resistance Avalanche Rated Pb-Free Terminal Plating RoHS Compliant Halogen Free PRODUCT SUMMARY TA = 25°C TYPICAL VALUE VDS Drain to Source Voltage Qg Gate Charge Total (4.5 V) Qgd Gate Charge Gate to Drain RDD(on) Drain to Drain On Resistance (Q1 + Q2) VGS(th) Threshold Voltage UNIT 20 V 11.7 nC 1.6 nC VGS = 4.5 V 11.7 mΩ VGS = 8 V 10.3 mΩ 1.1 V ORDERING INFORMATION Device Package Media CSD85312Q3E SON 3.3 x 3.3 mm Plastic Package 13 Inch Reel Qty Ship 2500 Tape and Reel APPLICATIONS • Adaptor or USB Input Protection for Notebook PCs and Tablets ABSOLUTE MAXIMUM RATINGS TA = 25°C VALUE UNIT VDS Drain to Source Voltage 20 V DESCRIPTION VGS Gate to Source Voltage +10/–8 V The CSD85312Q3E is a 20 V common-source, dual N-channel device designed for adaptor or USB input protection. This SON 3.3 x 3.3 mm device has low drain to drain on-resistance that minimizes losses and offers low component count for space constrained multi-cell battery charging applications. ID Continuous Drain Current (Package Limited) 39 A Continuous Drain Current (1) 12 A IDM Pulsed Drain Current (2) 76 A PD Power Dissipation 2.5 W TJ, TSTG Operating Junction and Storage Temperature Range –55 to 150 °C EAS Avalanche Energy, Single Pulse ID = 38 A, L = 0.1 mH, RG = 25 Ω 72 mJ Top View D1 1 D1 2 8 D2 7 D2 (1) Typical RθJA =63°C/W on 1 inch2 (2 oz.) on 0.060 inch thick FR4PCB (2) Pulse duration ≤ 300 μs, duty cycle ≤ 2% TEXT ADDED FOR SPACING VGS vs. RDD(on) S 3 6 D2 NC 4 5 G Circuit Image Common Source Drain 1 Drain 2 30 RDD(on) - On-State Resistance (mΩ) D1 24 21 18 15 12 9 6 3 0 Common Gate TC = 25°C, Id = 10A TC = 125ºC, Id = 10A 27 0 1 2 3 4 5 6 7 8 VGS - Gate-to- Source Voltage (V) 9 10 G001 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2013, Texas Instruments Incorporated CSD85312Q3E SLPS457 – NOVEMBER 2013 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise stated) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Static Characteristics BVDSS Drain to Source Voltage VGS = 0 V, ID = 250 μA IDSS Drain to Source Leakage Current VGS = 0 V, VDS = 16 V IGSS Gate to Source Leakage Current VDS = 0 V, VGS = +10/–8 V VGS(th) Gate to Source Threshold Voltage VDS = VGS, ID = 250 μA RDD(on) gfs 20 0.85 V 1 μA 100 nA 1.10 1.40 V Drain to Drain On Resistance (Q1 + Q2) VGS = 4.5 V, ID = 10 A 11.7 14.0 mΩ VGS = 8 V, ID = 10 A 10.3 12.4 mΩ Transconductance VDS = 10 V, ID = 10 A 99 S Dynamic Characteristics (1) Ciss Input Capacitance 1840 2390 pF Coss Output Capacitance Crss Reverse Transfer Capacitance 492 640 pF 31 40 RG Series Gate Resistance pF 5.5 11 Ω Qg Qgd Gate Charge Total (4.5 V) 11.7 15.2 nC Gate Charge Gate to Drain 1.6 Qgs Gate Charge Gate to Source nC 3.5 nC Qg(th) Gate Charge at Vth Qoss Output Charge 1.8 nC 8.9 td(on) nC Turn On Delay Time 11 ns tr Rise Time 27 ns td(off) Turn Off Delay Time 24 ns tf Fall Time 6 ns VGS = 0 V, VDS = 10 V, f = 1 MHz VDS = 10 V, ID = 10 A VDS = 10 V, VGS = 0 V VDS = 10 V, VGS = 4.5 V, IDS = 10 A, RG = 2 Ω Diode Characteristics (1) VSD Diode Forward Voltage Qrr Reverse Recovery Charge trr Reverse Recovery Time (1) ISD = 10 A, VGS = 0 V 0.8 VDS= 10 V, IF = 10 A, di/dt = 300 A/μs 1 V 15 nC 23 ns All Dynamic and Diode Characteristics were measured with respect to one of the two drains, with the other left floating. THERMAL CHARACTERISTICS (TA = 25°C unless otherwise stated) PARAMETER RθJC Thermal Resistance Junction to Case (1) RθJA Thermal Resistance Junction to Ambient (1) (2) (1) (2) 2 MIN 2 TYP MAX UNIT 3.0 °C/W 63 °C/W 2 RθJC is determined with the device mounted on a 1 inch (6.45 cm ), 2-oz. (0.071 mm thick) Cu pad on a 1.5 inch × 1.5 inch (3.81 cm × 3.81 cm), 0.06 inch (1.52 mm) thick FR4 PCB. RθJC is specified by design, whereas RθJA is determined by the user’s board design. Device mounted on FR4 material with 1 inch2 (6.45 cm2), 2 oz. (0.071 mm thick) Cu. Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated CSD85312Q3E www.ti.com GATE SLPS457 – NOVEMBER 2013 GATE DRAIN DRAIN Max RθJA = 63°C/W when mounted on 1 inch2 (6.45 cm2) of 2 oz. (0.071 mm thick) Cu. Max RθJA = 150°C/W when mounted on a minimum pad area of 2 oz. (0.071 mm thick) Cu. SOURCE SOURCE M0137-02 M0137-01 TYPICAL MOSFET CHARACTERISTICS (TA = 25°C unless otherwise stated) Figure 1. Transient Thermal Impedance Copyright © 2013, Texas Instruments Incorporated Submit Documentation Feedback 3 CSD85312Q3E SLPS457 – NOVEMBER 2013 www.ti.com TYPICAL MOSFET CHARACTERISTICS (continued) (TA = 25°C unless otherwise stated) TEXT ADDED FOR SPACING TEXT ADDED FOR SPACING 60 VDD = 5V 90 IDD - Drain-to- Drain Current (A) IDD - Drain-to-Drain Current (A) 100 80 70 60 50 40 30 VGS = 8V VGS = 6V VGS = 4.5V 20 10 0 0 0.4 0.8 1.2 1.6 VDD - Drain-to-Drain Voltage (V) 50 40 30 20 0 2 TC = 125°C TC = 25°C TC = −55°C 10 0 1 G001 Figure 2. Saturation Characteristics TEXT ADDED FOR SPACING TEXT ADDED FOR SPACING 6 1000 C − Capacitance (pF) VGS - Gate-to-Source Voltage (V) ID = 10A VDS =10V 7 5 4 3 2 100 10 Ciss = Cgd + Cgs Coss = Cds + Cgd Crss = Cgd 1 0 3 6 9 12 15 Qg - Gate Charge (nC) 18 21 1 24 0 2 4 G001 6 8 10 12 14 16 VDS - Drain-to-Source Voltage (V) 18 20 G001 Figure 5. Capacitance TEXT ADDED FOR SPACING TEXT ADDED FOR SPACING 1.5 30 ID = 250uA 1.4 RDD(on) - On-State Resistance (mΩ) VGS(th) - Threshold Voltage (V) G001 10000 Figure 4. Gate Charge 1.3 1.2 1.1 1 0.9 0.8 0.7 0.6 0.5 −75 −25 25 75 125 TC - Case Temperature (ºC) Figure 6. Threshold Voltage vs. Temperature 4 5 Figure 3. Transfer Characteristics 8 0 2 3 4 VGS - Gate-to-Source Voltage (V) Submit Documentation Feedback 175 G001 TC = 25°C, Id = 10A TC = 125ºC, Id = 10A 27 24 21 18 15 12 9 6 3 0 0 1 2 3 4 5 6 7 8 VGS - Gate-to- Source Voltage (V) 9 10 G001 Figure 7. On-State Resistance vs. Gate-to-Source Voltage Copyright © 2013, Texas Instruments Incorporated CSD85312Q3E www.ti.com SLPS457 – NOVEMBER 2013 TYPICAL MOSFET CHARACTERISTICS (continued) (TA = 25°C unless otherwise stated) TEXT ADDED FOR SPACING TEXT ADDED FOR SPACING 100 VGS = 8V VGS = 4.5V 1.75 ID =10A ISD − Source-to-Drain Current (A) Normalized On-State Resistance 2 1.5 1.25 1 0.75 0.5 0.25 −75 −25 25 75 125 TC - Case Temperature (ºC) 175 TC = 25°C TC = 125°C 10 1 0.1 0.01 0.001 0.0001 0 0.2 0.4 0.6 0.8 VSD − Source-to-Drain Voltage (V) G001 Figure 8. Normalized On-State Resistance vs. Temperature G001 Figure 9. Typical Diode Forward Voltage TEXT ADDED FOR SPACING TEXT ADDED FOR SPACING 100 1000 1ms 10ms 100ms 1s DC IAV - Peak Avalanche Current (A) IDS - Drain-to-Source Current (A) 1 100 10 1 0.1 Single Pulse Typical RthetaJA =120ºC/W(min Cu) 0.01 0.01 0.1 1 10 VDS - Drain-to-Source Voltage (V) 50 TC = 25ºC TC = 125ºC 10 1 0.01 0.1 TAV - Time in Avalanche (mS) G001 Figure 10. Maximum Safe Operating Area 1 G001 Figure 11. Single Pulse Unclamped Inductive Switching TEXT ADDED FOR SPACING IDD - Drain- to- Drain Current (A) 45.0 40.0 35.0 30.0 25.0 20.0 15.0 10.0 5.0 0.0 −50 −25 0 25 50 75 100 125 TC - Case Temperature (ºC) 150 175 G001 Figure 12. Maximum Drain Current vs. Temperature Copyright © 2013, Texas Instruments Incorporated Submit Documentation Feedback 5 CSD85312Q3E SLPS457 – NOVEMBER 2013 www.ti.com MECHANICAL DATA CSD85312Q3E Package Dimensions Table 1. Pin Configuration 6 Submit Documentation Feedback Position Designation Pin 1 – 3 Drain 1 Pin 4 No Connect Pin 5 Gate Pin 6 – 8 Drain 2 Pin 9 (Thermal Pad) Source Copyright © 2013, Texas Instruments Incorporated CSD85312Q3E www.ti.com SLPS457 – NOVEMBER 2013 Recommended PCB Pattern Recommended Stencil Opening 1. All Dimensions are in millimeters (inches) 2. Stencil Opening Thickness 4 mils . For recommended circuit layout for PCB designs, see application note SLPA005 – Reducing Ringing Through PCB Layout Techniques. Copyright © 2013, Texas Instruments Incorporated Submit Documentation Feedback 7 CSD85312Q3E SLPS457 – NOVEMBER 2013 www.ti.com 1.75 ±0.10 Q3E Tape and Reel Information 4.00 ±0.10 (See Note 1) Ø 1.50 +0.10 –0.00 3.60 1.30 3.60 5.50 ±0.05 12.00 +0.30 –0.10 8.00 ±0.10 2.00 ±0.05 M0144-01 Notes: 1. 10 sprocket hole pitch cumulative tolerance ±0.2 2. Camber not to exceed 1 mm IN 100 mm, noncumulative over 250 mm 3. Material:black static dissipative polystyrene 4. All dimensions are in mm (unless otherwise specified) 5. Thickness: 0.30 ±0.05 mm 6. MSL1 260°C (IR and Convection) PbF Reflow Compatible 8 Submit Documentation Feedback Copyright © 2013, Texas Instruments Incorporated PACKAGE OPTION ADDENDUM www.ti.com 10-Dec-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan (2) Lead finish/ Ball material MSL Peak Temp Op Temp (°C) Device Marking (3) (4/5) (6) CSD85312Q3E ACTIVE VSON DPA 8 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 150 85312E (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of