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CSD87313DMS
SLPS642 – APRIL 2017
CSD87313DMS 30-V Dual N-Channel NexFET™ Power MOSFETs
1 Features
•
•
•
•
•
•
•
•
•
•
1
Low-Source-to-Source On Resistance
Dual Common Drain N-Channel MOSFETs
Optimized for 5-V Gate Drive
Low Qg and Qgd
Low-Thermal Resistance
Avalanche Rated
Lead-Free Terminal Plating
RoHS Compliant
Halogen Free
SON 3.3-mm × 3.3-mm Plastic Package
2 Applications
•
•
•
USB Type-C™ and Power Delivery (PD) VBus
Protection
Battery Protection
Load Switch
Product Summary
TA = 25°C
VALUE
UNIT
VS1S2
Source1-to-Source2 Voltage
30
V
Qg
Gate Charge Total (4.5 V)
28
nC
Qgd
Gate Charge Gate-to-Drain
RS1S2(on)
Max Source1-to-Source2 On
Resistance
VGS(th)
Threshold Voltage
6.0
nC
VGS = 2.5 V
9.6
VGS = 4.5 V
5.5
0.9
mΩ
V
Device Information(1)
DEVICE
QTY
MEDIA
PACKAGE
SHIP
CSD87313DMS
2500
13-Inch Reel
CSD87313DMST
250
7-Inch Reel
SON
3.30-mm × 3.30-mm
Plastic Package
Tape
and
Reel
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Absolute Maximum Ratings
VALUE
UNIT
VS1S2
Source1-to-Source2 Voltage
30
V
3 Description
VGS
Gate-to-Source Voltage(1)
±10
V
The CSD87313DMS is a 30-V common drain, dual Nchannel device designed for USB Type-C/PD and
battery protection. This SON 3.3-mm × 3.3-mm
device has low-source-to-source on resistance that
minimizes losses and offers low-component count for
space constrained applications.
IS1S2
Continuous Source Current(2)
17
A
ISM
Pulsed Source Current, TA = 25°C(2)(3)
120
A
Power Dissipation(2)
2.7
Power Dissipation(4)
1
Schematic
TA = 25°C unless otherwise stated
PD
TJ,
Tstg
Operating Junction,
Storage Temperature
EAS
Avalanche Energy, Single Pulse,
ID = 37 A, L = 0.1 mH, RG = 25 Ω
W
–55 to 150
°C
67
mJ
(1) VG1S1 should not exceed ±10 V and VG2S2 should not exceed
±10 V.
(2) Typical RθJA = 45°C/W when mounted on a 1-in2 (6.45-cm2),
2-oz (0.071-mm) thick Cu pad on a 0.06-in (1.52-mm) thick
FR4 PCB.
(3) Duty cycle ≤ 2%, pulse duration ≤ 300 µs.
(4) Typical RθJA = 125°C/W on a minimum 2-oz Cu pad.
S1
G1
D
G2
S2
RS1S2(ON) vs VGS
Gate Charge
8
TC = 25° C, I D = 23 A
TC = 125° C, I D = 23 A
18
VGS1S2 - Gate-to-Source Voltage (V)
RS1S2(on) - On-State Resistance (m:)
20
16
14
12
10
8
6
4
2
ID = 23 A
7 VDS = 15 V
6
5
4
3
2
1
0
0
0
1
2
3
4
5
6
7
8
VGS - Gate-To-Source Voltage (V)
9
10
D006
0
5
10
15
20
25
30
35
Qg - Gate Charge (nC)
40
45
50
D010
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
CSD87313DMS
SLPS642 – APRIL 2017
www.ti.com
Table of Contents
1
2
3
4
5
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Specifications.........................................................
6.1
6.2
6.3
6.4
6.5
1
1
1
2
3
7
5.1 Electrical Characteristics........................................... 3
5.2 Thermal Information .................................................. 3
5.3 Typical MOSFET Characteristics.............................. 4
6
Receiving Notification of Documentation Updates....
Community Resources..............................................
Trademarks ...............................................................
Electrostatic Discharge Caution ................................
Glossary ....................................................................
8
8
8
8
8
Mechanical, Packaging, and Orderable
Information ............................................................. 9
7.1 DMS Package Dimensions ....................................... 9
7.2 Recommended PCB Pattern................................... 10
7.3 Recommended Stencil Opening ............................. 11
Device and Documentation Support.................... 8
4 Revision History
2
DATE
REVISION
NOTES
April 2017
*
Initial release.
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SLPS642 – APRIL 2017
Specifications
5.1 Electrical Characteristics
TA = 25°C (unless otherwise stated)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
STATIC CHARACTERISTICS
IS1S2
Source1-to-Source2 leakage current
VG1S1 = 0 V, VG2S2 = 0 V, VS1S2 = 24 V
IGSS
Gate-to-source leakage current
VS1S2 = 0 V, VGS = 10 V
VGS(th)
Gate-to-source threshold voltage
VS1S2 = VGS, IS1S2 = 250 μA
RS1S2(on)
Source1-to-Source2 on resistance
gfs
Transconductance
DYNAMIC CHARACTERISTICS
1
μA
100
nA
0.9
1.2
V
VGS = 2.5 V, IS1S2 = 20 A
6.7
9.6
VGS = 4.5 V, IS1S2 = 23 A
4.6
5.5
VS1S2 = 3 V, IS1S2 = 23 A
149
0.6
mΩ
S
(1)
CISS
Input capacitance
COSS
Output capacitance
CRSS
Reverse transfer capacitance
Qg
Gate charge total (4.5 V)
Qgd
Gate charge gate-to-drain
Qgs
VGS = 0 V, VS1S2 = 15 V, ƒ = 1 MHz
3300
4290
pF
281
365
pF
154
200
pF
28
nC
6.0
nC
Gate charge gate-to-source
6.3
nC
Qg(th)
Gate charge at Vth
3.2
nC
td(on)
Turnon delay time
9
ns
tr
Rise time
27
ns
td(off)
Turnoff delay time
41
ns
tf
Fall time
13
ns
VS1S2 = 15 V, IS1S2 = 23 A
VG1S1 = 4.5 V, VG2S2 = 0 V
VS1S2 = 15 V, IS1S2 = 23 A
VGS = 4.5 V, RGEN = 0 Ω
DIODE CHARACTERISTICS
Ifss
Maximum continuous Source1-to-Source2
diode forward current (2)
Vfss
Source1-to-Source2 diode forward voltage VG1S1 = 0 V, VG2S2 = 4.5 V, Ifss = 23 A
(1)
(2)
VG1S1 = 0 V, VG2S2 = 4.5 V
0.8
2
A
1.0
V
Dynamic characteristic measurements are for a single FET.
Typical RθJA = 125°C/W on a minimum 2-oz Cu pad.
5.2 Thermal Information
TA = 25°C (unless otherwise stated)
THERMAL METRIC
RθJA
RθJA
(1)
(2)
UNIT
Junction-to-case thermal resistance (1)
Junction-to-ambient thermal resistance
(1) (2)
125
°C/W
45
°C/W
Device mounted on minimum 2-oz (0.071-mm) thick Cu.
Device mounted on FR4 material with 1-in2 (6.45-cm2), 2-oz (0.071-mm) thick Cu.
GATE
GATE
Source
Source
RθJA = 45°C/W when
mounted on 1 in2 (6.45
cm2) of
2-oz (0.071-mm) thick
Cu.
RθJA = 125°C/W when
mounted on a
minimum pad area of
2-oz (0.071-mm) thick
Cu.
DRAIN
DRAIN
M0161-02
M0161-01
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5.3 Typical MOSFET Characteristics
TA = 25°C (unless otherwise stated)
120
IS1S2 - Source1-to-Source2 Current (A)
IS1S2 - Source1-to-Source2 Current (A)
120
108
96
84
72
60
48
36
VG1S1 = 3 V
VG1S1 = 3.5 V
VG1S1 = 4 V
VG1S1 = 4.5 V
24
12
0
108
96
84
72
60
48
36
VGS = 3 V
VGS = 3.5 V
VGS = 4 V
VGS = 4.5 V
24
12
0
0
0.1
0.2 0.3 0.4 0.5 0.6 0.7 0.8
VS1S2 - Source1-to-Source2 Voltage (V)
Pulse width = 250 µs, duty cycle = 0.5%
0.9
1
0
0.1
D001
VG2S2 = 4.5 V
Normalized Source1-to-Source2 RS1S2(ON)
Normalized Source1-to-Source2 RS1S2(ON)
1
0.75
VG1S1 = 4 V
VG1S1 = 4.5 V
0.5
10
1.5
1.25
1
0.75
VGS = 3 V
VGS = 3.5 V
VG2S2 = 4.5 V
10
Figure 4. Saturation Characteristics
VGS = 2.5 V
VGS = 4.5 V
RS1S2(on) - On-State Resistance (m:)
Normalized On-State Resistance
20
1.4
1.2
1
0.8
0.6
TC = 25° C, I D = 23 A
TC = 125° C, I D = 23 A
18
16
14
12
10
8
6
4
2
0
-50
-25
0
25
50
75 100
TC - Case Temperature (° C)
IS1S2 = 23 A
125
150
175
0
1
D008
2
3
4
5
6
7
8
VGS - Gate-To-Source Voltage (V)
9
10
D006
VGS = 15 V
Figure 5. Normalized On-State Resistance vs Temperature
4
20 30 40 50 60 70 80 90 100 110 120
IS1S2 - Source1-to-Source2 Current (A)
D004
Pulse width = 250 µs, duty cycle = 0.5%
Figure 3. Saturation Characteristics
0.4
-75
VGS = 4 V
VGS = 4.5 V
0.5
0
1.8
1.6
D002
1.75
20 30 40 50 60 70 80 90 100 110 120
IS1S2 - Source1-to-Source2 Current (A)
D004
Pulse width = 250 µs, duty cycle = 0.5%
1
Figure 2. Saturation Characteristics
1.25
0
0.9
Pulse width = 250 µs, duty cycle = 0.5%
Figure 1. Saturation Characteristics
1.5
VG1S1 = 3 V
VG1S1 = 3.5 V
0.2 0.3 0.4 0.5 0.6 0.7 0.8
VS1S2 - Source1-to-Source2 Voltage (V)
Figure 6. On-State Resistance vs Gate-to-Source Voltage
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Typical MOSFET Characteristics (continued)
TA = 25°C (unless otherwise stated)
100
TC = 150° C
TC = 25° C
TC = -55° C
108
96
IfSS - Source-to-Drain Current (A)
IS1S2 - Source1-to-Source2 Current (A)
120
84
72
60
48
36
24
TC = -55qC
TC = 25qC
TC = 125qC
10
1
0.1
0.01
0.001
12
0
0.5
0.0001
0.75
1
1.25
1.5
1.75
2
VGS - Gate-to-Source Voltage (V)
2.25
0
2.5
0.2
D007
0.4
0.6
0.8
VfSS - Source-to-Drain Voltage (V)
1
1.2
D009
VS1S2 = 5 V
Figure 7. Transfer Characteristics
Figure 8. Typical Diode Forward Voltage
10000
7
6
C - Capacitance (pF)
VGS1S2 - Gate-to-Source Voltage (V)
8
5
4
3
2
1000
100
Ciss = Cgd + Cgs
Coss = Cds + Cgd
Crss = Cgd
1
10
0
0
5
10
15
20
25
30
35
Qg - Gate Charge (nC)
ID = 23 A
40
45
0
50
5
10
15
20
25
VS1S2 - Source1-to-Source2 Voltage (V)
D010
Figure 10. Capacitance
P(PK) - Peak Transient Power (W)
IS1S2 - Source1-to-Source2 Current (A)
10000
200
100
10
1
0.1
0.001
0.01
D010
VS1S2 = 15 V
Figure 9. Gate Charge
0.01
30
DC
10 s
1s
100 ms
10 ms
1 ms
100 µs
0.1
1
10
VS1S2 - Source1-to-Source2 Voltage (V)
100
1000
100
10
1
0.1
0.0001
0.001
D010
Single pulse, RθJA = 125°C/W
0.01
0.1
1
10
tp - Pulse Duration (s)
100
1000
D013
RθJA = 125 °C/W, TA = 25°C
Figure 11. Maximum Safe Operating Area
Figure 12. Single Pulse Maximum Power Dissipation
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Typical MOSFET Characteristics (continued)
TA = 25°C (unless otherwise stated)
100
1.3
IAV - Peak Avalanche Current (A)
VGS(th) - Threshold Voltage (V)
1.2
1.1
1
0.9
0.8
0.7
0.6
0.5
TC = 25q C
TC = 125q C
10
0.4
0.3
-75
-50
-25
0
25
50
75 100
TC - Case Temperature (qC)
125
150
175
1
0.01
0.1
TAV - Time in Avalanche (ms)
D006
1
D011
ID = 250 µA
Figure 13. Threshold Voltage vs Temperature
Figure 14. Single Pulse Unclamped Inductive Switching
IS1S2 - Source1-to-Source2 Current (A)
24
20
16
12
8
4
0
-50
-25
0
25
50
75
100 125
TA - Ambient Temperature (qC)
150
175
D012
Figure 15. Maximum Source1-to-Source2 Current vs Temperature
6
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Typical MOSFET Characteristics (continued)
TA = 25°C (unless otherwise stated)
Figure 16. Transient Thermal Impedance
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6 Device and Documentation Support
6.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
6.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
6.3 Trademarks
NexFET, E2E are trademarks of Texas Instruments.
USB Type-C is a trademark of USB Implementers Forum.
All other trademarks are the property of their respective owners.
6.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
6.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
8
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7 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
7.1 DMS Package Dimensions
3.4
3.2
B
A
PIN 1 INDEX AREA
3.4
3.2
C
0.8 MAX
SEATING PLANE
0.08 C
1.66 0.1
4X
(0.2) TYP
PKG
1.04
0.84
0.05
0.00
0.3
4X
0.1
4
5
2X
1.28 0.1
2X
1.95
SYMM
EXPOSED
THERMAL PAD
8
1
6X 0.65
8X
PIN 1 ID
(OPTIONAL)
2X (0.2)
0.37
0.27
0.1
0.05
C A B
C
2X (0.4)
4222980/A 05/2016
(1)
All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and
tolerancing per ASME Y14.5M.
(2)
This drawing is subject to change without notice.
(3)
The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
Table 1. Pin Configuration Table
POSITION
DESIGNATION
POSITION
DESIGNATION
1
Gate 1
5
Source 2
2
Drain
6
Source 2
3
Drain
7
Source 1
4
Gate 2
8
Source 1
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7.2 Recommended PCB Pattern
0.05 MIN
ALL AROUND
( 0.2) TYP
2X (1.66)
4X (0.4)
2X (0.62)
4X (1.14)
8
4X (0.32)
1
(1.28)
4X (0.32)
(0.805)
(0.415)
PKG
SYMM
(1.195)
3X (0.65)
2X (0.65)
4
5
(R0.05) TYP
METAL UNDER
SOLDER MASK
TYP
SEE DETAILS
(1.28)
(0.04) TYP
SOLDER MASK
OPENING
TYP
(1.2) TYP
PKG
0.05 MIN
ALL AROUND
0.05 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
NON-SOLDER MASK
DEFINED
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
4222980/A 05/2016
10
(1)
This package is designed to be soldered to a thermal pad on the board. For more information, see QFN/SON PCB
Attachment (SLUA271).
(2)
Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their
locations shown on this view. It is recommended that vias under paste be filled, plugged or tented.
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7.3 Recommended Stencil Opening
2X (1.52)
SOLDER MASK EDGE
TYP
PKG
4X (0.39)
4X (0.97)
8
1
4X (0.32)
2X (1.19)
4X (0.32)
PKG
SYMM
(0.805)
3X
(0.65)
3X (0.65)
4
5
(R0.05) TYP
EXPOSED METAL
TYP
2X (0.55)
(1.37)
(1)
METAL UNDER
SOLDER MASK
TYP
(1.655)
EXPOSED METAL
TYP
Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may
have alternate design recommendations.
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
CSD87313DMS
ACTIVE
WSON
DMS
8
2500
RoHS-Exempt
& Green
SN
Level-1-260C-UNLIM
-55 to 150
CSD87313
CSD87313DMST
ACTIVE
WSON
DMS
8
250
RoHS-Exempt
& Green
SN
Level-1-260C-UNLIM
-55 to 150
CSD87313
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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