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CSD87333Q3D
SLPS350A – FEBRUARY 2014 – REVISED JANUARY 2017
CSD87333Q3D Synchronous Buck NexFET™ Power Block
1 Features
3 Description
•
•
•
•
•
•
•
•
•
•
•
•
•
•
The CSD87333Q3D NexFET™ power block is an
optimized design for synchronous buck and boost
applications offering high-current, high-efficiency, and
high-frequency capability in a small 3.3-mm × 3.3-mm
outline. Optimized for 5-V gate drive applications, this
product offers a flexible solution in high-duty cycle
applications when paired with an external controller or
driver.
1
Half-Bridge Power Block
Optimized for High-Duty Cycle
Up to 24 Vin
94.7% System Efficiency at 8 A
1.5 W PLoss at 8 A
Up to 15-A Operation
High-Frequency Operation (up to 1.5 MHz)
High-Density SON 3.3-mm × 3.3-mm Footprint
Optimized for 5-V Gate Drive
Low-Switching Losses
Ultra-Low Inductance Package
RoHS Compliant
Halogen Free
Lead-Free Terminal Plating
.
Top View
8
VSW
7
VSW
3
6
VSW
4
5
VIN
1
VIN
2
TG
TGR
PGND
(Pin 9)
BG
P0116-01
2 Applications
•
•
•
Device Information(1)
Synchronous Buck Converters
– High-Frequency Applications
– High-Duty Cycle Applications
Synchronous Boost Converters
POL DC-DC Converters
DEVICE
MEDIA
QTY
PACKAGE
SHIP
CSD87333Q3D
13-Inch Reel
2500
CSD87333Q3DT
7-Inch Reel
250
SON
3.30-mm × 3.30-mm
Plastic Package
Tape
and
Reel
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
.
.
Typical Circuit
Typical Power Block Efficiency and Power Loss
VIN
VDD
VIN
ENABLE
PWM
ENABLE
PWM
DRVH
LL
DRVL
TG
TGR
VSW
VOUT
BG
PGND
Driver IC
CSD87333Q3D
Efficiency (%)
GND
5
90
4
80
3
BOOT
VGS = 5V
VIN = 12V
VOUT = 3.3V
LOUT = 1.0µH
fSW = 500kHz
TA = 25ºC
70
60
50
0
3
6
9
Output Current (A)
12
15
2
Power Loss (W)
VDD
100
1
0
G001
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
CSD87333Q3D
SLPS350A – FEBRUARY 2014 – REVISED JANUARY 2017
www.ti.com
Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Specifications.........................................................
1
1
1
2
3
5.1
5.2
5.3
5.4
5.5
5.6
5.7
3
3
3
3
4
5
7
Absolute Maximum Ratings ......................................
Recommended Operating Conditions.......................
Power Block Performance ........................................
Thermal Information ..................................................
Electrical Characteristics...........................................
Typical Power Block Device Characteristics.............
Typical Power Block MOSFET Characteristics.........
Applications ........................................................... 9
6.1 Power Loss Curves ................................................... 9
6.2 Safe Operating Area (SOA) Curves.......................... 9
6.3 Normalized Curves.................................................... 9
6.4 Calculating Power Loss and SOA........................... 10
7
Recommended PCB Design Overview .............. 11
7.1 Electrical Performance ............................................ 11
7.1 Thermal Performance ............................................. 12
8
Device and Documentation Support.................. 13
8.1
8.2
8.3
8.4
8.5
9
Receiving Notification of Documentation Updates.. 13
Community Resources............................................ 13
Trademarks ............................................................. 13
Electrostatic Discharge Caution .............................. 13
Glossary .................................................................. 13
Mechanical, Packaging, and Orderable
Information ........................................................... 14
9.1
9.2
9.3
9.4
9.5
Q3D Package Dimensions......................................
Pinout Configuration................................................
Land Pattern Recommendation ..............................
Stencil Recommendation ........................................
Q3D Tape and Reel Information .............................
14
15
16
16
17
4 Revision History
Changes from Original (February 2014) to Revision A
Page
•
Added pulse duration note to IDM in the Absolute Maximum Ratings table............................................................................ 3
•
Added Receiving Notification of Documentation Updates section and Community Resources section to the Device
and Documentation Support section .................................................................................................................................... 13
2
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SLPS350A – FEBRUARY 2014 – REVISED JANUARY 2017
5 Specifications
5.1 Absolute Maximum Ratings (1)
TA = 25°C (unless otherwise noted)
PARAMETER
CONDITIONS
MIN
MAX
UNIT
–0.8
30
V
VSW to PGND
30
V
VSW to PGND (10 ns)
32
V
VIN to PGND
Voltage
TG to TGR
–0.3
10
V
BG to PGND
–0.3
10
V
Pulsed current rating, IDM (2)
40
A
Power dissipation, PD
6
W
Avalanche energy, EAS
Sync FET, ID = 19, L = 0.1 mH
18
Control FET, ID = 19, L = 0.1 mH
18
mJ
Operating junction temperature, TJ
–55
150
°C
Storage temperature, Tstg
–55
150
°C
(1)
(2)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated in the Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Pulse duration ≤ 50 µS. Duty cycle ≤ 0.01%.
5.2 Recommended Operating Conditions
TA = 25°C (unless otherwise noted)
PARAMETER
VGS
Gate drive voltage
VIN
Input supply voltage
fSW
Switching frequency
CONDITIONS
MIN
MAX
3.3
8
V
24
CBST = 0.1 µF (min)
1500
Operating current
TJ
UNIT
Operating temperature
V
kHz
15
A
125
°C
5.3 Power Block Performance (1)
TA = 25°C (unless otherwise noted)
PARAMETER
CONDITIONS
PLOSS
Power loss (1)
VIN = 12 V, VGS = 5 V, VOUT = 3.3 V,
IOUT = 8 A, fSW = 500 kHz,
LOUT = 1 µH, TJ = 25°C
IQVIN
VIN quiescent current
TG to TGR = 0 V BG to PGND = 0 V
(1)
MIN
TYP
MAX
UNIT
1.5
W
10
µA
Measurement made with six 10-µF (TDK C3216X5R1C106KT or equivalent) ceramic capacitors placed across VIN to PGND pins and
using a high current 5-V driver IC.
5.4 Thermal Information
TA = 25°C (unless otherwise stated)
THERMAL METRIC
RθJA
RθJC
(1)
(2)
Junction-to-ambient thermal resistance (min Cu)
(1)
MIN
TYP
MAX
150
Junction-to-ambient thermal resistance (max Cu) (1) (2)
80
Junction-to-case thermal resistance (top of package) (1)
36
Junction-to-case thermal resistance (PGND pin)
(1)
3.7
UNIT
°C/W
°C/W
RθJC is determined with the device mounted on a 1-in2 (6.45-cm2), 2-oz (0.071-mm) thick Cu pad on a 1.5-in × 1.5-in
(3.81-cm × 3.81-cm), 0.06-in (1.52-mm) thick FR4 board. RθJC is specified by design while RθJA is determined by the user’s board
design.
Device mounted on FR4 material with 1-in2 (6.45-cm2) Cu.
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5.5 Electrical Characteristics
TA = 25°C (unless otherwise stated)
PARAMETER
Q1 Control FET
TEST CONDITIONS
MIN
TYP
Q2 Sync FET
MAX
MIN
TYP
MAX
UNIT
STATIC CHARACTERISTICS
BVDSS
Drain-to-source voltage
VGS = 0 V, IDS = 250 µA
IDSS
Drain-to-source leakage
current
VGS = 0 V, VDS = 20 V
IGSS
Gate-to-source leakage
current
VDS = 0 V, VGS = +10 / –8
V
VGS(th)
Gate-to-source threshold
voltage
VDS = VGS, IDS = 250 µA
RDS(on)
Drain-to-source on
resistance
gfs
Transconductance
30
30
0.75
V
1
1
µA
100
100
nA
0.95
1.20
V
0.95
1.20
VGS = 3.5 V, IDS = 4 A
14.7
17.7
14.7
17.7
VGS = 4.5 V, IDS = 4 A
13.4
16.1
13.4
16.1
VGS = 8 V, IDS = 4 A
11.9
14.3
11.9
14.3
VDS = 15 V, IDS = 4 A
0.75
43
43
mΩ
S
DYNAMIC CHARACTERISTICS
CISS
Input capacitance
COSS
Output capacitance
509
662
509
662
pF
222
289
222
289
CRSS
pF
Reverse transfer capacitance
8.2
10.7
8.2
10.7
pF
RG
Series gate resistance
3.4
6.8
3.4
6.8
Ω
Qg
Gate charge total (4.5 V)
3.5
4.6
3.5
4.6
nC
Qgd
Gate charge gate-to-drain
0.3
0.3
nC
Qgs
Gate charge gate-to-source
1.6
1.6
nC
Qg(th)
Gate charge at Vth
0.6
0.6
nC
QOSS
Output charge
5.3
5.3
nC
td(on)
Turnon delay time
2.1
2.1
ns
tr
Rise time
3.9
3.9
ns
td(off)
Turnoff delay time
9.4
9.4
ns
tf
Fall time
2.2
2.2
ns
VGS = 0 V, VDS = 15 V,
ƒ = 1 MHz
VDS = 15 V,
IDS = 4 A
VDS = 15 V, VGS = 0 V
VDS = 15 V, VGS = 4.5 V,
IDS = 4 A, RG = 2 Ω
DIODE CHARACTERISTICS
VSD
Diode forward voltage
Qrr
Reverse recovery charge
trr
Reverse recovery time
IDS = 4 A, VGS = 0 V
0.80
VDS = 15 V, IF = 4 A,
di/dt = 300 A/µs
10
10
nC
11
11
ns
LD
HD
LS
LG
HG
M0205-01
4
1.0
V
Max RθJA = 150°C/W
when mounted on
minimum pad area of
2-oz (0.071-mm) thick
Cu.
MIN Rev0
MIN Rev0
HS
86330Q3D 3.3x3.3
86330Q3D 3.3x3.3
LG
0.80
LD
HD
Max RθJA = 80°C/W
when mounted on 1 in2
(6.45 cm2) of 2-oz
(0.071-mm) thick Cu.
HG
1.0
HS
LS
M0206-01
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5.6 Typical Power Block Device Characteristics
The typical power block system characteristic curves (Figure 1 through Figure 9) are based on measurements made on a
PCB design with dimensions of 4 in (W) × 3.5 in (L) × 0.062 in (H) and 6 copper layers of 1-oz copper thickness. See
Applications for detailed explanation. TA = 125°C, unless stated otherwise.
6
1.1
VIN = 12V
VGS = 5V
VOUT = 3.3V
fSW = 500kHz
LOUT = 1.0µH
4
1
Power Loss, Normalized
Power Loss (W)
5
3
2
1
0
VIN = 12V
VGS = 5V
VOUT = 3.3V
fSW = 500kHz
LOUT = 1.0µH
0.9
0.8
0.7
0.6
0
3
6
9
Output Current (A)
12
0.5
−50
15
15
15
12
9
6
0
400LFM
200LFM
100LFM
Nat Conv
0
10
20
0
80
125
150
G001
12
9
6
90
0
0
10
20
G001
Figure 3. Safe Operating Area – PCB Horizontal Mount
VIN = 12V
VGS = 5V
VOUT = 3.3V
fSW = 500kHz
LOUT =1.0µH
400LFM
200LFM
100LFM
Nat Conv
3
30
40
50
60
70
Ambient Temperature (ºC)
25
50
75
100
Junction Temperature (ºC)
Figure 2. Power Loss vs Temperature
18
Output Current (A)
Output Current (A)
Figure 1. Power Loss vs Output Current
18
3
−25
G001
30
40
50
60
70
Ambient Temperature (ºC)
80
90
G001
Figure 4. Safe Operating Area – PCB Vertical Mount
20
18
Output Current (A)
16
14
12
10
8
6
4
2
0
0
20
40
60
80
100
Board Temperature (ºC)
120
140
G001
Figure 5. Typical Safe Operating Area
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Typical Power Block Device Characteristics (continued)
The typical power block system characteristic curves (Figure 1 through Figure 9) are based on measurements made on a
PCB design with dimensions of 4 in (W) × 3.5 in (L) × 0.062 in (H) and 6 copper layers of 1-oz copper thickness. See
Applications for detailed explanation. TA = 125°C, unless stated otherwise.
1.8
1.06
1.2
1.03
0.6
1
0.0
0.97
0
200
400
600
800 1000 1200
Switching Frequency (kHz)
1400
VGS = 5V
VOUT = 3.3V
LOUT =1.0µH
fSW = 500kHz
IOUT = 15A
1.15
−0.6
1600
1.1
1.0
1
0.0
0.95
−1.0
0.9
−2.0
0.85
0
Figure 6. Normalized Power Loss vs Switching Frequency
0.72
1.02
0.36
0
1
VIN = 12V
VGS = 5V
fSW = 500kHz
LOUT = 1.0µH
IOUT = 15A
0.96
0.94
0
1
2
3
4
5
Output Voltage (V)
6
7
−0.36
8
6
20
24
28
−3.0
G001
3.99
VIN = 12V
VGS = 5V
VOUT = 3.3V
fSW = 500kHz
IOUT = 15A
1.12
3.19
2.39
1.08
1.6
1.04
0.8
0
1
−0.72
0.96
−1.08
0.92
−0.8
0
400
G001
Figure 8. Normalized Power Loss vs Output Voltage
12
16
Input Voltage (V)
1.16
Power Loss, Normalized
1.04
8
1.2
SOA Temperature Adj (ºC)
Power Loss, Normalized
1.08
0.98
4
Figure 7. Normalized Power Loss vs Input Voltage
1.44
1.06
2.0
1.05
G001
1.08
3.0
SOA Temperature Adj (ºC)
1.09
2.4
Power Loss, Normalized
1.12
4.0
1.2
SOA Temperature Adj (ºC)
Power Loss, Normalized
VIN = 12V
VGS = 5V
VOUT = 3.3V
LOUT = 1.0µH
IOUT = 15A
SOA Temperature Adj (ºC)
3.0
1.15
800
1200
1600
Output Inductance (nH)
2000
−1.6
2400
G001
Figure 9. Normalized Power Loss vs Output Inductance
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5.7 Typical Power Block MOSFET Characteristics
TA = 25°C, unless stated otherwise.
50
45
IDS - Drain-to-Source Current (A)
IDS - Drain-to-Source Current (A)
50
40
35
30
25
20
15
VGS = 8.0V
VGS =6V
VGS = 4.5V
10
5
0
0
0.1
0.2 0.3 0.4 0.5 0.6 0.7 0.8
VDS - Drain-to-Source Voltage (V)
0.9
VDS = 5V
10
1
0.1
0.01
0.001
1
TC = 125°C
TC = 25°C
TC = −55°C
0
Figure 10. MOSFET Saturation Characteristics
3
G001
1000
ID = 4A
VDS = 15V
9
C − Capacitance (nF)
8
7
6
5
4
3
100
10
Ciss = Cgd + Cgs
Coss = Cds + Cgd
Crss = Cgd
2
1
0
0
1
2
3
4
5
Qg - Gate Charge (nC)
6
7
1
8
0
3
Figure 12. MOSFET Gate Charge
9
12
15
18
21
24
VDS - Drain-to-Source Voltage (V)
27
30
G001
Figure 13. MOSFET Capacitance
36
RDS(on) - On-State Resistance (mΩ)
ID = 250µA
1.15
1.05
0.95
0.85
0.75
0.65
0.55
0.45
−75
6
G001
1.25
VGS(th) - Threshold Voltage (V)
1
1.5
2
2.5
VGS - Gate-to-Source Voltage (V)
Figure 11. MOSFET Transfer Characteristics
10
VGS - Gate-to-Source Voltage (V)
0.5
G001
−25
25
75
125
TC - Case Temperature (ºC)
175
TC = 25°C
TC = 125ºC
32
28
24
20
16
12
8
4
0
ID = 4A
0
1
G001
Figure 14. MOSFET VGS(th)
2
3
4
5
6
7
8
VGS - Gate-to- Source Voltage (V)
9
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G001
Figure 15. MOSFET RDS(on) vs VGS
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Typical Power Block MOSFET Characteristics (continued)
TA = 25°C, unless stated otherwise.
100
ID = 4A
VGS = 8V
ISD − Source-to-Drain Current (A)
Normalized On-State Resistance
1.6
1.4
1.2
1
0.8
VGS = 3.5V
VGS = 8V
0.6
−75
−25
25
75
125
TC - Case Temperature - ºC
175
10
1
0.1
0.01
0.001
0.0001
TC = 25°C
TC = 125°C
0
G001
Figure 16. MOSFET Normalized RDS(on)
0.2
0.4
0.6
0.8
VSD − Source-to-Drain Voltage (V)
1
G001
Figure 17. MOSFET Body Diode
I(AV) - Peak Avalanche Current (A)
100
10
TC = 25°C
TC = 125°C
1
0.01
0.1
1
t(AV) - Time in Avalanche (ms)
10
G001
Figure 18. MOSFET Unclamped Inductive Switching
8
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6 Applications
The CSD87333Q3D NexFET power block is an optimized design for synchronous buck applications using 5-V
gate drive. The control FET and sync FET silicon are parametrically tuned to yield the lowest power loss and
highest system efficiency. As a result, a new rating method is needed which is tailored towards a more systemscentric environment. System-level performance curves such as power loss, SOA, and normalized graphs allow
engineers to predict the product performance in the actual application.
6.1 Power Loss Curves
MOSFET centric parameters such as RDS(ON) and Qgd are needed to estimate the loss generated by the devices.
In an effort to simplify the design process for engineers, Texas Instruments has provided measured power loss
performance curves. Figure 1 plots the power loss of the CSD87333Q3D as a function of load current. This curve
is measured by configuring and running the CSD87333Q3D as it would be in the final application (see
Figure 19). The measured power loss is the CSD87333Q3D loss and consists of both input conversion loss and
gate drive loss. Equation 1 is used to generate the power loss curve.
Power loss = (VIN × IIN) + (VDD × IDD) – (VSW_AVG × IOUT)
(1)
The power loss curve in Figure 1 is measured at the maximum recommended junction temperatures of 125°C
under isothermal test conditions.
6.2 Safe Operating Area (SOA) Curves
The SOA curves in the CSD87333Q3D data sheet provides guidance on the temperature boundaries within an
operating system by incorporating the thermal resistance and system power loss. Figure 3 to Figure 5 outline the
temperature and airflow conditions required for a given load current. The area under the curve dictates the safe
operating area. All the curves are based on measurements made on a PCB design with dimensions of 4 in (W) ×
3.5 in (L) × 0.062 in (T) and 6 copper layers of 1-oz copper thickness.
6.3 Normalized Curves
The normalized curves in the CSD87333Q3D data sheet provides guidance on the power loss and SOA
adjustments based on their application specific needs. These curves show how the power loss and SOA
boundaries adjust for a given set of system conditions. The primary Y-axis is the normalized change in power
loss, and the secondary Y-axis is the change is system temperature required in order to comply with the SOA
curve. The change in power loss is a multiplier for the power loss curve and the change in temperature is
subtracted from the SOA curve.
Input Current (IIN)
A
VDD
A
VDD
V
VIN
Gate Drive V
Voltage (VDD)
VIN
BOOT
DRVH
ENABLE
Input Voltage (VIN)
TG
Output Current (IOUT)
LL
PWM
PWM
DRVL
GND
Driver IC
TGR
VSW
A
VOUT
BG
PGND
CSD87333Q3D
Averaging
Circuit
Averaged Switch
V Node Voltage
(VSW_AVG)
Figure 19. Typical Application
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6.4 Calculating Power Loss and SOA
The user can estimate product loss and SOA boundaries by arithmetic means (see Design Example). Though
the power loss and SOA curves in this data sheet are taken for a specific set of test conditions, the following
procedure outlines the steps the user should take to predict product performance for any set of system
conditions.
6.4.1 Design Example
Operating conditions:
• Output current = 10 A
• Input voltage = 20 V
• Output voltage = 1 V
• Switching frequency = 1000 kHz
• Inductor = 0.6 µH
6.4.2 Calculating Power Loss
•
•
•
•
•
•
Power loss at 10 A = 2.6 W (Figure 1)
Normalized power loss for input voltage ≈ 1.1 (Figure 7)
Normalized power loss for output voltage ≈ 0.96 (Figure 8)
Normalized power loss for switching frequency ≈ 1.04 (Figure 6)
Normalized power loss for output inductor ≈ 1.03 (Figure 9)
Final calculated power loss = 2.6 W × 1.1 × 0.96 × 1.04 × 1.03 ≈ 2.9 W
6.4.3 Calculating SOA Adjustments
•
•
•
•
•
SOA adjustment for input voltage ≈ 2°C (Figure 7)
SOA adjustment for output voltage ≈ - 0.2°C (Figure 8)
SOA adjustment for switching frequency ≈ 0.8°C (Figure 6)
SOA adjustment for output inductor ≈ 0.8°C (Figure 9)
Final calculated SOA adjustment = 2 + (-0.2) + 0.8 + 0.8 ≈ 3.4°C
In the Design Example, the estimated power loss of the CSD87333Q3D would increase to 2.9 W. In addition, the
maximum allowable board or ambient temperature, or both, would have to decrease by 3.4°C. Figure 20
graphically shows how the SOA curve would be adjusted accordingly.
1. Start by drawing a horizontal line from the application current to the SOA curve.
2. Draw a vertical line from the SOA curve intercept down to the board or ambient temperature.
3. Adjust the SOA board or ambient temperature by subtracting the temperature adjustment value.
In the design example, the SOA temperature adjustment yields a reduction in allowable board/ambient
temperature of 3.4°C. In the event the adjustment value is a negative number, subtracting the negative number
would yield an increase in allowable board or ambient temperature.
.
Figure 20. Power Block SOA
10
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7 Recommended PCB Design Overview
There are two key system-level parameters that can be addressed with a proper PCB design: electrical and
thermal performance. Properly optimizing the PCB layout yields maximum performance in both areas. A brief
description on how to address each parameter is provided.
7.1 Electrical Performance
The power block has the ability to switch voltages at rates greater than 10 kV/µs. Special care must be then
taken with the PCB layout design and placement of the input capacitors, driver IC, and output inductor.
• The placement of the input capacitors relative to the power block’s VIN and PGND pins should have the
highest priority during the component placement routine. It is critical to minimize these node lengths. As such,
ceramic input capacitors need to be placed as close as possible to the VIN and PGND pins (see Figure 21).
The example in Figure 21 uses 6 × 10-µF ceramic capacitors (TDK part number C3216X5R1C106KT or
equivalent). Notice there are ceramic capacitors on both sides of the board with an appropriate amount of
vias interconnecting both layers. In terms of priority of placement next to the power block, C5, C7, C19, and
C8 should follow in order.
• The driver IC should be placed relatively close to the power block gate pins. TG and BG should connect to the
outputs of the driver IC. The TGR pin serves as the return path of the high-side gate drive circuitry and should
be connected to the phase pin of the IC (sometimes called LX, LL, SW, PH, and so forth). The bootstrap
capacitor for the driver IC will also connect to this pin.
• The switching node of the output inductor should be placed relatively close to the power block VSW pins.
Minimizing the node length between these two components will reduce the PCB conduction losses and
actually reduce the switching noise level.(1) In the event the switch node waveform exhibits ringing that
reaches undesirable levels, the use of a boost resistor or RC snubber can be an effective way to easily
reduce the peak ring level. The recommended boost resistor value will range between 1 Ω to 4.7 Ω
depending on the output characteristics of driver IC used in conjunction with the power block. The RC
snubber values can range from 0.5 Ω to 2.2 Ω for the R and 330 pF to 2200 pF for the C. Please refer to
Snubber Circuits: Theory, Design and Application (SLUP100) for more details on how to properly tune the RC
snubber values. The RC snubber should be placed as close as possible to the Vsw node and PGND (see
Figure 21). (1)
(1)
Keong W. Kam, David Pommerenke, “EMI Analysis Methods for Synchronous Buck Converter EMI Root Cause Analysis”, University of
Missouri – Rolla
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7.1 Thermal Performance
The power block has the ability to utilize the GND planes as the primary thermal path. As such, the use of
thermal vias is an effective way to pull away heat from the device and into the system board. Concerns of solder
voids and manufacturability problems can be addressed by the use of three basic tactics to minimize the amount
of solder attach that will wick down the via barrel:
• Intentionally space out the vias from each other to avoid a cluster of holes in a given area.
• Use the smallest drill size allowed in your design. The example in Figure 21 uses vias with a 10-mil drill hole
and a 16-mil capture pad.
• Tent the opposite side of the via with solder-mask.
The number and drill size of the thermal vias should align with the end user’s PCB design rules and
manufacturing capabilities.
Figure 21. Recommended PCB Layout (Top Down)
12
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8 Device and Documentation Support
8.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
8.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
8.3 Trademarks
NexFET, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
8.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
8.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
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9 Mechanical, Packaging, and Orderable Information
The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
9.1 Q3D Package Dimensions
DIM
INCHES
MIN
MAX
MIN
MAX
A
0.850
1.050
0.033
0.041
b
0.280
0.400
0.011
0.016
b1
0.310 NOM
0.012 NOM
c
0.150
0.250
0.006
0.010
c1
0.150
0.250
0.006
0.010
d
0.940
1.040
0.037
0.041
d1
0.160
0.260
0.006
0.010
d2
0.150
0.250
0.006
0.010
d3
0.250
0.350
0.010
0.014
d4
0.175
0.275
0.007
0.011
D1
3.200
3.400
0.126
0.134
D2
2.650
2.750
0.104
0.108
E
3.200
3.400
0.126
0.134
E1
3.200
3.400
0.126
0.134
E2
1.750
1.850
0.069
0.073
e
0.650 TYP
0.026 TYP
L
0.400
0.500
0.016
0.020
θ
0.000
—
—
—
K
14
MILLIMETERS
0.300 TYP
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0.012 TYP
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9.2 Pinout Configuration
Table 1. Pinout Configuration
POSITION
DESIGNATION
Pin 1
VIN
Pin 2
VIN
Pin 3
TG
Pin 4
TGR
Pin 5
BG
Pin 6
VSW
Pin 7
VSW
Pin 8
VSW
Pin 9
PGND
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9.3 Land Pattern Recommendation
1.900 (0.075)
0.200
(0.008)
0.210
(0.008)
4
0.350 (0.014)
5
0.440
(0.017)
0.650
(0.026)
2.800
(0.110)
2.390
(0.094)
8
0.210
(0.008)
1
1.090
(0.043)
0.300 (0.012)
0.650 (0.026)
0.650 (0.026)
3.600 (0.142)
M0193-01
NOTE: Dimensions are in mm (in).
9.4 Stencil Recommendation
0.160 (0.005)
0.550 (0.022)
0.200 (0.008)
5
4
0.300 (0.012)
0.300
(0.012)
0.340
(0.013)
2.290
(0.090)
0.333
(0.013)
8
1
0.990
(0.039)
0.100
(0.004)
0.300 (0.012)
0.350 (0.014)
0.850 (0.033)
3.500 (0.138)
M0207-01
NOTE: Dimensions are in mm (in).
For recommended circuit layout for PCB designs, see Reducing Ringing Through PCB Layout Techniques
(SLPA005).
16
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1.75 ±0.10
9.5 Q3D Tape and Reel Information
4.00 ±0.10 (See Note 1)
Ø 1.50
+0.10
–0.00
1.30
3.60
5.50 ±0.05
12.00
+0.30
–0.10
8.00 ±0.10
2.00 ±0.05
3.60
M0144-01
NOTES: 1. 10-sprocket hole-pitch cumulative tolerance ± 0.2.
2. Camber not to exceed 1 mm in 100 mm, noncumulative over 250 mm.
3. Material: black static-dissipative polystyrene.
4. All dimensions are in mm, unless otherwise specified.
5. Thickness: 0.3 ± 0.05 mm.
6. MSL1 260°C (IR and convection) PbF reflow compatible.
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
(2)
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
(6)
CSD87333Q3D
ACTIVE
VSON-CLIP
DPB
8
2500
RoHS-Exempt
& Green
NIPDAU | SN
Level-1-260C-UNLIM
-55 to 150
87333D
CSD87333Q3DT
ACTIVE
VSON-CLIP
DPB
8
250
RoHS-Exempt
& Green
NIPDAU | SN
Level-1-260C-UNLIM
-55 to 150
87333D
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of
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