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CSD87350Q5D
SLPS288E – MARCH 2011 – REVISED FEBRUARY 2017
CSD87350Q5D Synchronous Buck NexFET™ Power Block
1 Features
3 Description
•
•
•
•
•
•
•
•
•
•
•
The CSD87350Q5D NexFET™ power block is an
optimized design for synchronous buck applications
offering high-current, high-efficiency, and highfrequency capability in a small 5-mm × 6-mm outline.
Optimized for 5-V gate drive applications, this product
offers a flexible solution capable of offering a highdensity power supply when paired with any 5-V gate
drive from an external controller or driver.
1
Half-Bridge Power Block
90% system Efficiency at 25 A
Up to 40-A Operation
High-Frequency Operation (Up to 1.5 MHz)
High-Density SON 5-mm × 6-mm Footprint
Optimized for 5-V Gate Drive
Low-Switching Losses
Ultra-Low-Inductance Package
RoHS Compliant
Halogen Free
Lead-Free Terminal Plating
Top View
2 Applications
•
•
•
•
Synchronous Buck Converters
– High-Frequency Applications
– High-Current, Low-Duty Cycle Applications
Multiphase Synchronous Buck Converters
POL DC-DC Converters
IMVP, VRM, and VRD Applications
7
VSW
3
6
VSW
4
5
VIN
2
TG
TGR
PGND
(Pin 9)
BG
Device Information(1)
DEVICE
CSD87350Q5D
MEDIA
13-Inch Reel
QTY
PACKAGE
SHIP
2500
SON
5-mm × 6-mm
Plastic Package
Tape and
Reel
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Typical Power Block Efficiency and Power Loss
VIN
VDD
VSW
1
P0116-01
Typical Circuit
VDD
8
VIN
BOOT
96
11
94
10
92
9
VIN
PWM
ENABLE
PWM
LL
DRVL
TG
Control
FET
TGR
VSW
BG
Sync
FET
VOUT
PGND
Driver IC
CSD87350Q5D
90
8
VGS = 5 V
VIN = 12 V
VOUT = 1.3 V
LOUT = 0.3 PH
fSW = 500 kHz
TA = 25qC
88
86
84
82
7
6
5
4
80
3
78
2
76
1
74
0
5
10
15
20
25
Output Current (A)
30
35
Power Loss (W)
ENABLE
DRVH
Efficiency (%)
GND
0
40
D001
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
CSD87350Q5D
SLPS288E – MARCH 2011 – REVISED FEBRUARY 2017
www.ti.com
Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Specifications.........................................................
1
1
1
2
3
5.1
5.2
5.3
5.4
5.5
5.6
5.7
3
3
3
3
4
5
7
Absolute Maximum Ratings ......................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Power Block Performance ........................................
Electrical Characteristics...........................................
Typical Power Block Device Characteristics.............
Typical Power Block MOSFET Characteristics.........
Application and Implementation ........................ 10
6.1 Application Information............................................ 10
6.2 Typical Application .................................................. 13
7
Layout ................................................................... 15
7.1 Layout Guidelines ................................................... 15
7.2 Layout Example ...................................................... 16
8
Device and Documentation Support.................. 17
8.1
8.2
8.3
8.4
8.5
8.6
9
Documentation Support .......................................... 17
Receiving Notification of Documentation Updates.. 17
Community Resources............................................ 17
Trademarks ............................................................. 17
Electrostatic Discharge Caution .............................. 17
Glossary .................................................................. 17
Mechanical, Packaging, and Orderable
Information ........................................................... 18
9.1
9.2
9.3
9.4
Q5D Package Dimensions......................................
Land Pattern Recommendation ..............................
Stencil Recommendation ........................................
Q5D Tape and Reel Information .............................
18
19
19
20
4 Revision History
Changes from Revision D (September 2014) to Revision E
Page
•
Added note for IDM in the Absolute Maximum Ratings table .................................................................................................. 3
•
Added Receiving Notification of Documentation Updates section and Community Resources section in the
Documentation Support section ........................................................................................................................................... 17
Changes from Revision C (October 2011) to Revision D
•
Added Handling Rating table, Application and Implementation section, Layout section, Device and Documentation
Support section, and Mechanical, Packaging, and Orderable Information section................................................................ 1
Changes from Revision B (September 2011) to Revision C
•
Page
Page
Changed "DIM a" Millimeter Max value From: 1.55 To: 1.5 and Inches Max value From: 0.061 To: 0.059........................ 18
Changes from Revision A (August 2011) to Revision B
Page
•
Replaced RDS(on) with ZDS(on) ................................................................................................................................................... 4
•
Added Equivalent System Performance section .................................................................................................................. 10
•
Added the Comparison of RDS(on) vs ZDS(on) table ................................................................................................................. 12
•
Added Electrical Performance bullet .................................................................................................................................... 15
Changes from Original (March 2011) to Revision A
•
2
Page
Changed Power Dissipation, PD in the Absolute Maximum Ratings table From; 13 W to 12 W............................................ 3
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SLPS288E – MARCH 2011 – REVISED FEBRUARY 2017
5 Specifications
5.1 Absolute Maximum Ratings
TA = 25°C (unless otherwise noted) (1)
MIN
MAX
UNIT
–0.8
30
V
TG to TGR
–8
10
V
BG to PGND
–8
10
V
120
A
12
W
VIN to PGND
Voltage
IDM
Pulsed current rating (2)
PD
Power dissipation
Sync FET, ID = 105 A, L = 0.1 mH
551
Control FET, ID = 60 A, L = 0.1 mH
180
EAS
Avalanche energy
TJ
Operating junction temperature
–55
150
°C
Tstg
Storage temperature
–55
150
°C
(1)
(2)
mJ
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated in the Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Pulse duration ≤ 50 µs. Duty cycle ≤ 0.01%.
5.2 Recommended Operating Conditions
TA = 25° (unless otherwise noted)
MIN
VGS
Gate drive voltage
VIN
Input supply voltage
ƒSW
Switching frequency CBST = 0.1 μF (min)
4.5
UNIT
8
V
27
200
Operating current
TJ
MAX
Operating temperature
V
1500
kHz
40
A
125
°C
5.3 Thermal Information
TA = 25°C (unless otherwise stated)
THERMAL METRIC
RθJA
RθJC
(1)
(2)
MAX
UNIT
Junction-to-ambient thermal resistance (min Cu) (1) (2)
102
°C/W
Junction-to-ambient thermal resistance (max Cu) (1) (2)
50
°C/W
Junction-to-case thermal resistance (top of package) (2)
20
°C/W
2
°C/W
Junction-to-case thermal resistance (PGND pin)
2
MIN
TYP
(2)
(6.45-cm2)
2
Device mounted on FR4 material with 1-in
Cu.
RθJC is determined with the device mounted on a 1-in (6.45-cm2), 2-oz (0.071-mm) thick Cu pad on a 1.5-in × 1.5-in
(3.81-cm × 3.81-cm), 0.06-in (1.52-mm) thick FR4 board. RθJC is specified by design while RθJA is determined by the user’s board
design.
5.4 Power Block Performance
TA = 25° (unless otherwise noted)
PARAMETER
TEST CONDITIONS
PLOSS
Power loss (1)
VIN = 12 V VGS = 5 V, VOUT = 1.3 V,
IOUT = 25 A, ƒSW = 500 kHz,
LOUT = 0.3 µH, TJ = 25°C
IQVIN
VIN quiescent current
TG to TGR = 0 V ,BG to PGND = 0 V
(1)
MIN
TYP MAX
UNIT
3
W
10
µA
Measurement made with six 10-µF (TDK C3216X5R1C106KT or equivalent) ceramic capacitors placed across VIN to PGND pins and
using a high-current 5-V driver IC.
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5.5 Electrical Characteristics
TA = 25°C (unless otherwise stated)
PARAMETER
TEST CONDITIONS
Q1 CONTROL FET
MIN
TYP
Q2 SYNC FET
MAX
MIN
TYP MAX
UNIT
STATIC CHARACTERISTICS
BVDSS
Drain-to-source voltage
VGS = 0 V, IDS = 250 μA
IDSS
Drain-to-source leakage current
VGS = 0 V, VDS = 20 V
IGSS
Gate-to-source leakage current
VDS = 0 V, VGS = +10 / –8
VGS(th)
Gate-to-source threshold voltage
VDS = VGS, IDS = 250 μA
ZDS(on) (1)
Effective AC on-impedance
VIN = 12 V, VGS = 5 V,
VOUT = 1.3 V, IOUT = 20 A,
ƒSW = 500 kHz,
LOUT = 0.3 µH
gƒs
Transconductance
VDS = 15 V, IDS = 20 A
30
30
V
1
100
1
2.1
0.75
1
μA
100
nA
1.4
V
5
1.2
mΩ
97
157
S
DYNAMIC CHARACTERISTICS
CISS
Input capacitance
COSS
Output capacitance
1360
1770
2950 3835
pF
565
735
1300 1690
pF
CRSS
RG
Reverse transfer capacitance
19
25
50
65
Series gate resistance
1.3
3
0.8
2
Ω
Qg
Gate charge total (4.5 V)
8.4
10.9
20
26
nC
Qgd
Gate charge gate-to-drain
Qgs
Gate charge gate-to-source
Qg(th)
Gate charge at Vth
QOSS
Output charge
td(on)
Turnon delay time
tr
Rise time
td(off)
Turnoff delay time
tƒ
Fall time
VGS = 0 V, VDS = 15 V,
ƒ = 1 MHz
pF
1.6
3.6
nC
2.6
4.3
nC
1.6
2.3
nC
VDS = 17 V, VGS = 0 V
9.7
28
nC
7
8
ns
VDS = 15 V, VGS = 4.5 V,
IDS = 20 A, RG = 2 Ω
17
10
ns
13
33
ns
2.3
4.7
ns
VDS = 15 V,
IDS = 20 A
DIODE CHARACTERISTICS
VSD
Diode forward voltage
Qrr
Reverse recovery charge
trr
Reverse recovery time
(1)
IDS = 20 A, VGS = 0 V
0.85
Vdd = 17 V, IF = 20 A,
di/dt = 300 A/μs
12.5
0.77
32
1
nC
V
22
28
ns
Equivalent based on application testing. See Equivalent System Performance section for details.
HD
LD
HD
LG
LD
5x6 QFN TTA MIN Rev1
5x6 QFN TTA MIN Rev1
Max RθJA = 50°C/W
when mounted on 1 in2
(6.45 cm2) of
2-oz (0.071-mm) thick
Cu.
HG
Max RθJA = 102°C/W
when mounted on
minimum pad area of
2-oz (0.071-mm) thick
Cu.
HS
LG
LS
HG
M0189-01
4
1
HS
LS
M0190-01
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SLPS288E – MARCH 2011 – REVISED FEBRUARY 2017
5.6 Typical Power Block Device Characteristics
TJ = 125°C, unless stated otherwise. The typical power block system characteristic curves Figure 3, Figure 4, and Figure 5
are based on measurements made on a PCB design with dimensions of 4 in (W) × 3.5 in (L) × 0.062 in (H) and 6 copper
layers of 1-oz copper thickness. See Application and Implementation for detailed explanation.
10
1.05
9
1
Power Loss, Normalized
Power Loss (W)
8
7
6
5
4
3
2
0.95
0.9
0.85
0.8
0.75
0.7
1
0
0
5
10
VIN = 12 V
ƒSW = 500 kHz
15
20
25
Output Current (A)
30
35
0.65
-50
40
VGS = 5 V
LOUT = 0.3 µH
VOUT = 1.3 V
10
30
50
70
90 110
TC - Junction Temperature (qC)
130
150
D003
VGS = 5 V
LOUT = 0.3 µH
VOUT = 1.3 V
Figure 2. Normalized Power Loss vs Temperature
45
40
40
35
35
Output Current (A)
Output Current (A)
Figure 1. Power Loss vs Output Current
30
25
20
15
400 LFM
200 LFM
100 LFM
Nat. conv.
5
-10
VIN = 12 V
ƒSW = 500 kHz
45
10
-30
D002
30
25
20
15
400 LFM
200 LFM
100 LFM
Nat. conv.
10
5
0
0
0
10
VIN = 12 V
ƒSW = 500 kHz
20
30
40
50
60
Ambient Temperature (qC)
70
80
0
90
10
20
D004
VGS = 5 V
LOUT = 0.3 µH
VOUT = 1.3 V
VIN = 12 V
ƒSW = 500 kHz
Figure 3. Safe Operating Area (SOA) – PCB Vertical Mount
30
40
50
60
Ambient Temperature (qC)
70
80
90
D005
VGS = 5 V
LOUT = 0.3 µH
VOUT = 1.3 V
Figure 4. Safe Operating Area (SOA) – PCB Horizontal
Mount
45
1.5
14.7
1.4
11.8
1.3
8.8
1.2
5.9
1.1
2.9
1
0.0
Power Loss, Normalized
Output Current (A)
35
30
25
20
15
10
SOA Temperature Adj. (qC)
40
5
0
0
20
VIN = 12 V
ƒSW = 500 kHz
40
60
80
100
Board Temperature (qC)
VGS = 5 V
LOUT = 0.3 µH
120
140
0.9
200
400
D006
VOUT = 1.3 V
Figure 5. Typical Safe Operating Area (SOA)
600
800
1000
1200
Switching Frequency (kHz)
VIN = 12 V
LOUT = 0.3 µH
VGS = 5 V
IOUT = 40 A
1400
-2.9
1600
D007
VOUT = 1.3 V
Figure 6. Normalized Power Loss vs Switching Frequency
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Typical Power Block Device Characteristics (continued)
TJ = 125°C, unless stated otherwise. The typical power block system characteristic curves Figure 3, Figure 4, and Figure 5
are based on measurements made on a PCB design with dimensions of 4 in (W) × 3.5 in (L) × 0.062 in (H) and 6 copper
layers of 1-oz copper thickness. See Application and Implementation for detailed explanation.
5.9
1.15
4.4
1.1
2.9
1.05
1.5
1
0.0
0.95
2
4
VIN = 12 V
ƒSW = 500 kHz
6
8
10 12 14 16
Input Voltage (V)
18
20
22
-8.8
1.25
-7.3
1.2
-5.9
1.15
-4.4
1.1
-2.9
1.05
-1.5
1
0.0
0.95
1.5
0.9
2.9
0.9 1.1 1.3 1.5 1.7 1.9 2.1 2.3 2.5 2.7 2.9 3.1 3.3 3.5
Output Voltage (V)
D009
-1.5
24
D008
VOUT = 1.3 V
IOUT = 40 A
-10.3
1.3
LOUT = 0.3 µH
Figure 7. Normalized Power Loss vs Input Voltage
VIN = 12 V
LOUT = 0.3 µH
Power Loss, Normalized
ƒSW = 500 kHz
Figure 8. Normalized Power Loss vs Output Voltage
1.125
3.7
1.1
2.9
1.075
2.2
1.05
1.5
1.025
0.7
1
0.0
0.975
-0.7
0.95
-1.5
0.925
-2.2
1.1
0
VIN = 12 V
ƒSW = 500 kHz
VGS = 5 V
IOUT = 40 A
0.1
0.2
0.3
0.4 0.5 0.6 0.7 0.8
Output Inductance (PH)
0.9
1
VGS = 5 V
IOUT = 40 A
SOA Temperature Adj. (qC)
0
Power Loss, Normalized
1.2
-11.7
1.35
SOA Temperature Adj. (qC)
1.4
7.3
SOA Temperature Adj. (qC)
Power Loss, Normalized
1.25
D010
VOUT = 1.3 V
Figure 9. Normalized Power Loss vs Output Inductance
6
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5.7 Typical Power Block MOSFET Characteristics
80
80
70
70
IDS - Drain-to-Source Current (A)
IDS - Drain-to-Source Current (A)
TA = 25°C, unless stated otherwise.
60
50
40
30
20
VGS = 8.0 V
VGS = 4.5 V
VGS = 4.0 V
10
0
60
50
40
30
20
VGS = 8.0 V
VGS = 4.5 V
VGS = 4.0 V
10
0
0
0.05
0.1
0.15 0.2 0.25 0.3 0.35 0.4
VDS - Drain-to-Source Voltage (V)
0.45
0.5
0
0.02 0.04 0.06 0.08 0.1 0.12 0.14 0.16 0.18
VDS - Drain-to-Source Voltage (V)
D011
Figure 10. Control MOSFET Saturation
100
IDS - Drain-to-Source Current (A)
IDS - Drain-to-Source Current (A)
D012
Figure 11. Sync MOSFET Saturation
100
10
1
0.1
0.01
TC = 125qC
TC = 25qC
TC = -55qC
0.001
10
1
0.1
0.01
TC = 125qC
TC = 25qC
TC = -55qC
0.001
0
0.5
1
1.5
2
2.5
3
VGS - Gate-to-Source Voltage (V)
3.5
4
0
0.5
D013
1
1.5
2
VGS - Gate-to-Source Voltage (V)
VDS = 5 V
2.5
3
D014
VDS = 5 V
Figure 12. Control MOSFET Transfer
Figure 13. Sync MOSFET Transfer
8
8
7
7
VGS - Gate-to-Source Voltage (V)
VGS - Gate-to-Source Voltage (V)
0.2
6
5
4
3
2
1
0
6
5
4
3
2
1
0
0
2
ID = 20 A
4
6
8
10
Qg - Gate Charge (nC)
12
14
16
0
5
D015
VDD = 15 V
ID = 20 A
Figure 14. Control MOSFET Gate Charge
10
15
20
25
Qg - Gate Charge (nC)
30
35
D016
VDD = 15 V
Figure 15. Sync MOSFET Gate Charge
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Typical Power Block MOSFET Characteristics (continued)
10
10
1
1
C - Capacitance (nF)
C - Capacitance (nF)
TA = 25°C, unless stated otherwise.
0.1
0.01
0.1
0.01
Ciss = Cgd + Cgs
Coss = Cds + Cgd
Crss = Cgd
Ciss = Cgd + Cgs
Coss = Cds + Cgd
Crss = Cgd
0.001
0.001
0
3
6
ƒ = 1 MHz
9
12
15
18
21
24
VDS - Drain-to-Source Voltage (V)
27
30
0
VGS = 0
1.6
1.2
1.4
1.2
1
0.8
-25
0
25
50
75 100
TC - Case Temperature (°C)
125
150
30
D018
VGS = 0
0.8
0.6
0.4
0.2
-75
175
-50
D019
-25
0
25
50
75 100
TC - Case Temperature (°C)
125
150
175
D020
ID = 250 µA
Figure 18. Control MOSFET VGS(th)
Figure 19. Sync MOSFET VGS(th)
16
8
TC = 25°C
TC = 125°C
14
RDS(on) - On-State Resistance (m:)
RDS(on) - On-State Resistance (m:)
27
1
ID = 250 µA
12
10
8
6
4
2
0
TC = 25°C
TC = 125°C
7
6
5
4
3
2
1
0
1
2
3
4
5
6
7
8
VGS - Gate-to-Source Voltage (V)
9
10
1
2
D021
Figure 20. Control MOSFET RDS(on) vs VGS
8
9
12
15
18
21
24
VDS - Drain-to-Source Voltage (V)
Figure 17. Sync MOSFET Capacitance
1.4
VGS(th) - Threshold Voltage (V)
VGS(th) - Threshold Voltage (V)
Figure 16. Control MOSFET Capacitance
-50
6
ƒ = 1 MHz
1.8
0.6
-75
3
D017
3
4
5
6
7
8
VGS - Gate-to-Source Voltage (V)
9
10
D022
Figure 21. Sync MOSFET RDS(on) vs VGS
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Typical Power Block MOSFET Characteristics (continued)
1.5
1.5
1.4
1.4
Normalized On-State Resistance
Normalized On-State Resistance
TA = 25°C, unless stated otherwise.
1.3
1.2
1.1
1
0.9
0.8
0.7
-75
-50
-25
ID = 20 A
0
25
50
75 100
TC - Case Temperature (°C)
125
150
1.2
1.1
1
0.9
0.8
0.7
-75
175
VGS = 8 V
-25
ID = 20 A
0
25
50
75 100
TC - Case Temperature (°C)
125
150
175
D001
D024
VGS = 8 V
Figure 23. Sync MOSFET Normalized RDS(on)
100
ISD - Source-to-Drain Current (A)
100
10
1
0.1
0.01
0.001
TC = 25°C
TC = 125°C
0.0001
10
1
0.1
0.01
0.001
TC = 25°C
TC = 125°C
0.0001
0
0.2
0.4
0.6
0.8
VSD - Source-to-Drain Voltage (V)
1
0
Figure 24. Control MOSFET Body Diode
0.4
0.6
0.8
VSD - Source-to-Drain Voltage (V)
1
D026
Figure 25. Sync MOSFET Body Diode
1000
IAV - Peak Avalanche Current (A)
TC = 25°C
TC = 125°C
10
1
0.01
0.2
D025
100
IAV - Peak Avalanche Current (A)
-50
D023
Figure 22. Control MOSFET Normalized RDS(on)
ISD - Source-to-Drain Current (A)
1.3
0.1
1
tAV - Time in Avalanche (ms)
10
TC = 25°C
TC = 125°C
100
10
1
0.01
D027
Figure 26. Control MOSFET Unclamped Inductive Switching
0.1
1
tAV - Time in Avalanche (ms)
10
D028
Figure 27. Sync MOSFET Unclamped Inductive Switching
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6 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
6.1 Application Information
The CSD87350Q5D NexFET power block is an optimized design for synchronous buck applications using 5-V
gate drive. The control FET and sync FET silicon are parametrically tuned to yield the lowest power loss and
highest system efficiency. As a result, a new rating method is needed which is tailored towards a more systemscentric environment. System-level performance curves such as power loss, Safe Operating Area (SOA), and
normalized graphs allow engineers to predict the product performance in the actual application.
6.1.1 Equivalent System Performance
Many of today’s high-performance computing systems require low-power consumption in an effort to reduce
system operating temperatures and improve overall system efficiency. This has created a major emphasis on
improving the conversion efficiency of today’s synchronous buck topology. In particular, there has been an
emphasis in improving the performance of the critical power semiconductor in the power stage of this application
(see Figure 28). As such, optimization of the power semiconductors in these applications, needs to go beyond
simply reducing RDS(ON).
Power Stage
Components
Input
Supply
+
-
Power Block
Components
Ci
Control
FET
Driver
PWM
Driver
Switch
Node
Lo
Sync
FET
Co
IL
Load
Figure 28. Equivalent System Schematic
The CSD87350Q5D is part of TI’s power block product family which is a highly optimized product for use in a
synchronous buck topology requiring high current, high efficiency, and high frequency. It incorporates TI’s latest
generation silicon which has been optimized for switching performance, as well as minimizing losses associated
with QGD, QGS, and QRR. Furthermore, TI’s patented packaging technology has minimized losses by nearly
eliminating parasitic elements between the control FET and sync FET connections (see Figure 29). A key
challenge solved by TI’s patented packaging technology is the system level impact of Common Source
Inductance (CSI). CSI greatly impedes the switching characteristics of any MOSFET which in turn increases
switching losses and reduces system efficiency. As a result, the effects of CSI need to be considered during the
MOSFET selection process. In addition, standard MOSFET switching loss equations used to predict system
efficiency need to be modified in order to account for the effects of CSI. Further details behind the effects of CSI
and modification of switching loss equations are outlined in Power Loss Calculation With Common Source
Inductance Consideration for Synchronous Buck Converters (SLPA009).
10
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Application Information (continued)
Input
Supply
RPCB
CESR
LDRAIN
CINPUT
Control
FET
Driver
PWM
CESL
LSOURCE
Switch
Node
Lo
Co
IL
Load
LDRAIN
Sync
FET
Driver
CTOTAL
LSOURCE
Figure 29. Elimination of Parasitic Inductances
The combination of TI’s latest generation silicon and optimized packaging technology has created a
benchmarking solution that outperforms industry standard MOSFET chipsets of similar RDS(ON) and MOSFET
chipsets with lower RDS(ON). Figure 30 and Figure 31 compare the efficiency and power loss performance of the
CSD87350Q5D versus industry standard MOSFET chipsets commonly used in this type of application. This
comparison purely focuses on the efficiency and generated loss of the power semiconductors only. The
performance of CSD87350Q5D clearly highlights the importance of considering the Effective AC On-Impedance
(ZDS(ON)) during the MOSFET selection process of any new design. Simply normalizing to traditional MOSFET
RDS(ON) specifications is not an indicator of the actual in-circuit performance when using TI’s power block
technology.
11
96
Power Block HS/LS RDS(on) = 5 m: / 2.1 m:
Discrete HS/LS RDS(on) = 5 m: / 2.1 m:
Discrete HS/LS RDS(on) = 5 m: / 1.2 m:
10
93
9
8
VGS = 5 V
VIN = 12 V
VOUT = 1.3 V
LOUT = 0.3 PH
fSW = 500 kHz
TA = 25qC
87
84
81
Power Loss (W)
Efficiency (%)
90
7
VGS = 5 V
VIN = 12 V
VOUT = 1.3 V
LOUT = 0.3 PH
fSW = 500 kHz
TA = 25qC
6
5
4
3
78
2
Power Block HS/LS RDS(on) = 5 m: / 2.1 m:
Discrete HS/LS RDS(on) = 5 m: / 2.1 m:
Discrete HS/LS RDS(on) = 5 m: / 1.2 m:
75
1
0
72
0
5
10
15
20
25
30
Output Current (A)
35
40
45
0
5
D029
Figure 30. Efficiency
10
15
20
25
30
Output Current (A)
35
40
45
D030
Figure 31. Power Loss
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Application Information (continued)
Table 1 compares the traditional DC measured RDS(ON) of CSD87350Q5D versus its ZDS(ON). This comparison
takes into account the improved efficiency associated with TI’s patented packaging technology. As such, when
comparing TI’s power block products to individually packaged discrete MOSFETs or dual MOSFETs in a
standard package, the in-circuit switching performance of the solution must be considered. In this example,
individually packaged discrete MOSFETs or dual MOSFETs in a standard package would need to have DC
measured RDS(ON) values that are equivalent to CSD87350Q5D’s ZDS(ON) value in order to have the same
efficiency performance at full load. Mid- to light-load efficiency will still be lower with individually packaged
discrete MOSFETs or dual MOSFETs in a standard package.
Table 1. Comparison of RDS(ON) vs ZDS(ON)
HS
PARAMETER
LS
TYP
MAX
TYP
MAX
Effective AC on-impedance ZDS(ON) (VGS = 5 V)
5
–
1.2
–
DC measured RDS(ON) (VGS = 4.5 V)
5
6.8
2.1
2.8
UNIT
mΩ
6.1.2 Power Loss Curves
MOSFET centric parameters such as RDS(ON) and Qgd are needed to estimate the loss generated by the devices.
In an effort to simplify the design process for engineers, Texas Instruments has provided measured power loss
performance curves. Figure 1 plots the power loss of the CSD87350Q5D as a function of load current. This curve
is measured by configuring and running the CSD87350Q5D as it would be in the final application (see
Figure 32).The measured power loss is the CSD87350Q5D loss and consists of both input conversion loss and
gate drive loss. Equation 1 is used to generate the power loss curve.
(VIN × IIN) + (VDD × IDD) – (VSW_AVG × IOUT) = power loss
(1)
The power loss curve in Figure 1 is measured at the maximum recommended junction temperatures of 125°C
under isothermal test conditions.
6.1.3 Safe Operating Area (SOA) Curves
The SOA curves in the CSD87350Q5D data sheet provides guidance on the temperature boundaries within an
operating system by incorporating the thermal resistance and system power loss. Figure 3 to Figure 5 outline the
temperature and airflow conditions required for a given load current. The area under the curve dictates the safe
operating area. All the curves are based on measurements made on a PCB design with dimensions of
4 in (W) × 3.5 in (L) × 0.062 in (T) and 6 copper layers of 1-oz copper thickness.
6.1.4 Normalized Curves
The normalized curves in the CSD87350Q5D data sheet provides guidance on the power loss and SOA
adjustments based on their application specific needs. These curves show how the power loss and SOA
boundaries will adjust for a given set of system conditions. The primary Y-axis is the normalized change in power
loss and the secondary Y-axis is the change is system temperature required in order to comply with the SOA
curve. The change in power loss is a multiplier for the power loss curve and the change in temperature is
subtracted from the SOA curve.
12
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6.2 Typical Application
Input Current (IIN)
A
VDD
A
VDD
V
VIN
Gate Drive V
Voltage (VDD)
ENABLE
VIN
BOOT
Input Voltage (VIN)
TG
DRVH
Output Current (IOUT)
PWM
PWM
GND
Driver IC
TGR
LL
VSW
A
VOUT
BG
DRVL
PGND
Averaging
Circuit
CSD87350Q5D
Averaged Switch
V Node Voltage
(VSW_AVG)
Figure 32.
6.2.1 Design Example: Calculating Power Loss and SOA
The user can estimate product loss and SOA boundaries by arithmetic means (see Operating Conditions).
Though the power loss and SOA curves in this data sheet are taken for a specific set of test conditions, the
following procedure will outline the steps the user should take to predict product performance for any set of
system conditions.
6.2.2 Operating Conditions
• Output current = 25 A
• Input voltage = 7 V
• Output voltage = 1 V
• Switching frequency = 800 kHz
• Inductor = 0.2 µH
6.2.2.1 Calculating Power Loss
•
•
•
•
•
•
Power Loss at 25 A = 3.5 W (Figure 1)
Normalized Power Loss for input voltage ≈ 1.07 (Figure 7)
Normalized Power Loss for output voltage ≈ 0.95 (Figure 8)
Normalized Power Loss for switching frequency ≈ 1.11 (Figure 6)
Normalized Power Loss for output inductor ≈ 1.07 (Figure 9)
Final calculated Power Loss = 3.5 W × 1.07 × 0.95 × 1.11 × 1.07 ≈ 4.23 W
6.2.2.2 Calculating SOA Adjustments
•
•
•
•
•
SOA adjustment for input voltage ≈ 2°C (Figure 7)
SOA adjustment for output voltage ≈ –1.3°C (Figure 8)
SOA adjustment for switching frequency ≈ 2.8°C (Figure 6)
SOA adjustment for output inductor ≈ 1.6°C (Figure 9)
Final calculated SOA adjustment = 2 + (-1.3) + 2.8 + 1.6 ≈ 5.1°C
In the previous design example, the estimated power loss of the CSD87350Q5D would increase to 4.23 W. In
addition, the maximum allowable board and/or ambient temperature would have to decrease by 5.1°C. Figure 33
graphically shows how the SOA curve would be adjusted accordingly.
1. Start by drawing a horizontal line from the application current to the SOA curve.
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Typical Application (continued)
2. Draw a vertical line from the SOA curve intercept down to the board/ambient temperature.
3. Adjust the SOA board/ambient temperature by subtracting the temperature adjustment value.
In the design example, the SOA temperature adjustment yields a reduction in allowable board/ambient
temperature of 5.1°C. In the event the adjustment value is a negative number, subtracting the negative number
would yield an increase in allowable board/ambient temperature.
Figure 33. Power Block SOA
14
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7 Layout
7.1 Layout Guidelines
There are two key system-level parameters that can be addressed with a proper PCB design: electrical and
thermal performance. Properly optimizing the PCB layout will yield maximum performance in both areas. The
following sections provide a brief description on how to address each parameter.
7.1.1 Electrical Performance
The power block has the ability to switch voltages at rates greater than 10kV/µs. Take special care with the PCB
layout design and placement of the input capacitors, driver IC, and output inductor.
• The placement of the input capacitors relative to the power block’s VIN and PGND pins should have the
highest priority during the component placement routine. It is critical to minimize these node lengths. As such,
ceramic input capacitors need to be placed as close as possible to the VIN and PGND pins (see Figure 34).
The example in Figure 34 uses 6 × 10-µF ceramic capacitors (TDK Part C3216X5R1C106KT or equivalent).
Notice there are ceramic capacitors on both sides of the board with an appropriate amount of vias
interconnecting both layers. In terms of priority of placement next to the power block, C5, C7, C19, and C8
should follow in order.
• The driver IC should be placed relatively close to the power block gate pins. TG and BG should connect to the
outputs of the driver IC. The TGR pin serves as the return path of the high-side gate drive circuitry and should
be connected to the phase pin of the IC (sometimes called LX, LL, SW, PH, etc.). The bootstrap capacitor for
the driver IC will also connect to this pin.
• The switching node of the output inductor should be placed relatively close to the power block VSW pins.
Minimizing the node length between these two components will reduce the PCB conduction losses and
actually reduce the switching noise level.
• In the event the switch node waveform exhibits ringing that reaches undesirable levels, the use of a boost
resistor or RC snubber can be an effective way to reduce the peak ring level. The recommended boost
resistor value will range between 1 Ω to 4.7 Ω depending on the output characteristics of driver IC used in
conjunction with the power block. The RC snubber values can range from 0.5 Ω to 2.2 Ω for the R and 330 pF
to 2200 pF for the C. Refer to Snubber Circuits: Theory , Design and Application (SLUP100) for more details
on how to properly tune the RC snubber values. The RC snubber should be placed as close as possible to
the Vsw node and PGND see Figure 34. (1)
7.1.2 Thermal Considerations
The power block has the ability to use the GND planes as the primary thermal path. As such, the use of thermal
vias is an effective way to pull away heat from the device and into the system board. Concerns of solder voids
and manufacturability problems can be addressed by the use of three basic tactics to minimize the amount of
solder attach that will wick down the via barrel:
• Intentionally space out the vias from each other to avoid a cluster of holes in a given area.
• Use the smallest drill size allowed in your design. The example in Figure 34 uses vias with a 10-mil drill hole
and a 16-mil capture pad.
• Tent the opposite side of the via with solder-mask.
In the end, the number and drill size of the thermal vias should align with the end user’s PCB design rules and
manufacturing capabilities.
(1)
Keong W. Kam, David Pommerenke, “EMI Analysis Methods for Synchronous Buck Converter EMI Root Cause Analysis”, University of
Missouri – Rolla
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7.2 Layout Example
Input Capacitors
Input Capacitors
TGR
TG
VIN
PGND
Output Capacitors
Driver IC
Power Block
BG
V SW
VSW
V SW
RC Snubber
Power Block
Location on Top
Layer
Top Layer
Output Inductor
Bottom Layer
Figure 34. Recommended PCB Layout (Top View)
16
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8 Device and Documentation Support
8.1 Documentation Support
8.1.1 Related Documentation
For related documentation see the following:
• Reducing Ringing Through PCB Layout Techniques
• Power Loss Calculation With Common Source Inductance Consideration for Synchronous Buck Converters
• Snubber Circuits: Theory , Design and Application
8.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
8.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
8.4 Trademarks
NexFET, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
8.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
8.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
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9 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
9.1 Q5D Package Dimensions
E2
K
d2
c1
4
5
4
q
L
d1
L
5
E1
6
3
6
3
b
9
D2
2
7
7
D1
2
E
e
8
1
8
1
d
d3
f
Top View
Bottom View
Side View
Pinout
Position
Exposed Tie Bar May Vary
q
a
c
E1
Front View
Pin 1
Designation
VIN
Pin 2
VIN
Pin 3
TG
Pin 4
TGR
Pin 5
BG
Pin 6
VSW
Pin 7
VSW
Pin 8
VSW
Pin 9
PGND
M0187-01
DIM
INCHES
MIN
MAX
MIN
MAX
a
1.40
1.5
0.055
0.059
b
0.360
0.460
0.014
0.018
c
0.150
0.250
0.006
0.010
c1
0.150
0.250
0.006
0.010
d
1.630
1.730
0.064
0.068
d1
0.280
0.380
0.011
0.015
d2
0.200
0.300
0.008
0.012
d3
0.291
0.391
0.012
0.015
D1
4.900
5.100
0.193
0.201
D2
4.269
4.369
0.168
0.172
E
4.900
5.100
0.193
0.201
E1
5.900
6.100
0.232
0.240
E2
3.106
3.206
0.122
0.126
e
1.27 TYP
0.050
f
0.396
0.496
0.016
0.020
L
0.510
0.710
0.020
0.028
θ
0.00
—
—
—
K
18
MILLIMETERS
0.812
0.032
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9.2 Land Pattern Recommendation
3.480 (0.137)
0.530 (0.021)
0.415 (0.016)
0.345 (0.014)
0.650 (0.026)
5
4
0.650 (0.026)
4.460
(0.176)
0.620
(0.024)
0.620 (0.024)
4.460
(0.176)
1.270
(0.050)
1
1.920
(0.076)
8
0.850 (0.033)
0.400 (0.016)
0.850 (0.033)
6.240 (0.246)
M0188-01
NOTE: Dimensions are in mm (in).
9.3 Stencil Recommendation
0.250 (0.010)
0.300 (0.012)
0.610 (0.024)
0.341 (0.013)
5
4
0.410 (0.016)
Stencil Opening
0.300 (0.012)
0.300 (0.012)
1.710
(0.067)
8
1
1.680
(0.066)
0.950 (0.037)
1.290 (0.051)
PCB Pattern
M0208-01
NOTE: Dimensions are in mm (in).
For recommended circuit layout for PCB designs, see Reducing Ringing Through PCB Layout Techniques
(SLPA005).
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9.4 Q5D Tape and Reel Information
4.00 ±0.10 (See Note 1)
K0
0.30 ±0.05
+0.10
2.00 ±0.05
Ø 1.50 –0.00
1.75 ±0.10
5.50 ±0.05
12.00 ±0.30
B0
R 0.20 MAX
A0
8.00 ±0.10
Ø 1.50 MIN
R 0.30 TYP
A0 = 5.30 ±0.10
B0 = 6.50 ±0.10
K0 = 1.90 ±0.10
M0191-01
NOTES: 1. 10-sprocket hole-pitch cumulative tolerance ±0.2.
2. Camber not to exceed 1 mm in 100 mm, noncumulative over 250 mm.
3. Material: black static-dissipative polystyrene.
4. All dimensions are in mm, unless otherwise specified.
5. Thickness: 0.3 ±0.05 mm.
6. MSL1 260°C (IR and convection) PbF-reflow compatible.
20
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PACKAGE MATERIALS INFORMATION
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11-Nov-2021
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
CSD87350Q5D
Package Package Pins
Type Drawing
LSONCLIP
DQY
8
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
2500
330.0
12.4
Pack Materials-Page 1
5.3
B0
(mm)
K0
(mm)
P1
(mm)
6.3
1.8
8.0
W
Pin1
(mm) Quadrant
12.0
Q2
PACKAGE MATERIALS INFORMATION
www.ti.com
11-Nov-2021
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
CSD87350Q5D
LSON-CLIP
DQY
8
2500
367.0
367.0
35.0
Pack Materials-Page 2
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